remarks are
tiresome.
trying to cure your willful ignorance.
You are the ignorant one here.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Robin Vowels [robi...@dodo.com.au]
Sent: Sunday, June 19, 2022 3:44 PM
record, at the time, Pilot ACE was the fastest machine
in the world. Addition time was 32 + 32n microseconds (n = number of
words).
Not efficient?
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Robin Vowels [robi...@dodo.com.au]
_
* except for about a dozen instructions initiating I/O operations,
or changing the state of the computer.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Robin Vowels
[robi...@dodo.com.au]
Sent: Friday, June 17, 202
@LISTSERV.UGA.EDU]
on behalf of Robin Vowels [robi...@dodo.com.au]
Sent: Friday, June 17, 2022 5:57 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: When did logical instructions appear?
On 2022-06-17 19:02, Seymour J Metz wrote:
I'm not aware of any serial 1s' complement or 2's complement machines
questions by the assumptions that you are making.
I made no assumptions.
On the other hand, your assertions are nonsense.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Robin Vowels [robi...@dodo.com.au]
Sent: Frida
.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Paul Gilmartin
[0014e0e4a59b-dmarc-requ...@listserv.uga.edu]
Sent: Thursday, June 16, 2022 5:20 PM
On Jun 16, 2022, at 10:43:36, Robin Vowels wrote:
Computers have had instructions for signed and unsigned binary
From: "Farley, Peter x23353" <0dc9d8785c29-dmarc-requ...@listserv.uga.edu>
To:
Sent: Friday, June 17, 2022 12:55 AM
There were already logical instructions as early as the 360 machine series.
They were around even earlier: at least by 1951 such instructions existed.
However, early
From: "Tom Marchant" <00a69b48f3bb-dmarc-requ...@listserv.uga.edu>
To:
Sent: Friday, June 17, 2022 12:58 AM
ADD LOGICAL and SUBTRACT LOGICAL were part of the original System/360,
and are documented in the A22-6821-0 edition of the System/360 Principles of
Operation,
as well as in
From: "Seymour J Metz"
To:
Sent: Friday, June 17, 2022 1:07 AM
Unsigned binary arithmetic goes back at least to the 704 in 1955.
I already said that it goes back to 1951, at least.
I suspect that it goes back farther. There was no concept of halfword at the
time;
it was all 36-bit words.
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Friday, June 17, 2022 7:20 AM
Subject: Re: When did logical instructions appear?
On Jun 16, 2022, at 10:43:36, Robin Vowels wrote:
Computers have had instruc
On 2022-06-17 00:36, Schmitt, Michael wrote:
My company's COBOL coding standards are* to define binary fields as
signed (e.g. PIC S9(4) BINARY). I'm wondering why that's the standard.
The original standards were developed at least 40-60 years ago. They
were revised in 1994 but the signed binary
How would the instrction be interruptable?
How would the lengths of the source and destinations be specified?
- Original Message -
From: "Schmitt, Michael"
To:
Sent: Wednesday, June 08, 2022 8:28 AM
Subject: MVCRL
Why isn't there a Move Relative Long instruction, i.e. move with no
- Original Message -
From: "Schmitt, Michael"
To:
Sent: Friday, May 27, 2022 7:23 AM
I want to replace all '*' with a space in a field. That's a TR instruction,
right?
But when I search through our 40 years of assembler code, I see no uses of TR
for such a purpose.
What? That's
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Sunday, May 01, 2022 1:11 AM
On Apr 30, 2022, at 08:50:04, Bob Raicer wrote:
- begin snippet (from Paul Gilmartin)
I believe what it intends to say is that the two's complement of
the maximum negative
From: "Martin Ward"
Sent: Saturday, April 30, 2022 7:27 PM
On Apr 29, 2022, at 12:08:22, Bob Raicer wrote:
The two's complement of the maximum negative number cannot be
represented in the same number of bits. ...
I think you mean "the absolute value (or the positive value)
of the maximum
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Saturday, April 30, 2022 6:34 AM
Subject: Re: Unsigned 64-bit numbers
On Apr 29, 2022, at 14:07:58, Robin Vowels wrote:
On 2022-04-30 05:10, Paul Gilmartin wrote
From: "Bob Raicer"
To:
Sent: Saturday, April 30, 2022 4:08 AM
There has been a lot of discussion about the representation of
signed binary integers and the common operations of signed addition
and subtraction on these items.
Since the introduction of the S/360 and continuing on through
On 2022-04-30 05:10, Paul Gilmartin wrote:
On Apr 29, 2022, at 12:08:22, Bob Raicer wrote:
For the sake of clarity I am going to paraphrase some of the text
found in the original S/360 Principles of Operation and the
z/Architecture Principles of Operation.
... The two's complement of
a
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Wednesday, April 27, 2022 10:53 AM
Subject: Re: Unexpected C code
On Apr 26, 2022, at 17:30:26, Peter Relson wrote:
Apologies if this was mentioned, since I am only now getting
From: "Peter Relson"
Sent: Wednesday, April 27, 2022 9:30 AM
Apologies if this was mentioned, since I am only now getting around to reading some of this
thread:
Bernd wrote (and others had similar)
LPR: if the register contains 0x8000, IMO the result will be zero
(and overflow),
On 2022-04-24 23:46, Jonathan Scott wrote:
I personally think the condition codes from Add Logical are
perfectly clear, making total sense for multi-length arithmetic,
but those from Subtract Logical are horribly confusing.
What? The condition codes are exactly the same as AL,
with the
On 2022-04-23 03:53, Paul Gilmartin wrote:
On Apr 22, 2022, at 09:52:10, Seymour J Metz wrote:
Right, that should be "if you want only zero with no carry, use JZ."
Zero with carry would be JH (BH on S/370).
Utterly counterintuitive.
Just read the manual.
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Friday, April 22, 2022 8:06 AM
Subject: Re: Unexpected C code
On Apr 21, 2022, at 15:34:21, Seymour J Metz wrote:
All of the logical arithmetic instructions report overflow, but they differ from signed
From: "Seymour J Metz"
To:
Sent: Friday, April 22, 2022 7:19 AM
Subject: Re: Test for zero after Add Logical
That depends on whether you want wrap-around. The BC 10 will branch on either zero with no carry
or zero with carry;
if you want only zero with carry, use JZ.
JZ will jump on zero
On 2022-04-22 03:38, Paul Gilmartin wrote:
I believe the Reference Summary Page 35 tells me that the
instruction to test for a zero result after Add Logial is
AL
BC 10,addr
There's no extended mnemonic for this.
For clarity, its it preferable too code:
AL
LTR
BZ add
???
On 2022-04-22 02:29, Paul Gilmartin wrote:
On Apr 21, 2022, at 10:21:46, Robin Vowels wrote:
AL and SL report overflow via the CC, as carry out.
rather, AL and SL report a carry from
the MSB.
That is overflow.
It it is not overflow.
It is overflow from an unsigned arithmetic operation
On 2022-04-22 02:08, Paul Gilmartin wrote:
On Apr 21, 2022, at 10:00:19, Gord Tomlin
wrote:
On 2022-04-21 10:46 AM, Seymour J Metz wrote:
Well, in the case of S/370 the compiler could emit JO or JNO after
the add.
Well, if only JO and JNO had existed in the days of S/370...
Wasn't there
On 2022-04-22 02:04, Paul Gilmartin wrote:
On Apr 21, 2022, at 08:43:55, Seymour J Metz wrote:
The question is not whether it is possible to detect overflow, but
rather how easy it is. Instructions for signed arithmetic set the
condition code appropriately for signed operands, but not for
On 2022-04-21 22:43, Seymour J Metz wrote:
The problem is detecting overflow.
Even Intel has overflow.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Robin Vowels [robi...@dodo.com.au]
Sent: Wednesday, April 20, 2022
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Wednesday, April 20, 2022 10:32 AM
C programmers don't give a damn about overflows. An unfortunate consequence,
probably, of hardware architectures which, unlike 360, lack unsigned
instructions, forcing compilers to
On 2022-04-20 20:05, Thomas David Rivers wrote:
That's a great explanation Thomas.
I'm curious though:Â how come both compilers produce this
same sequence of instructions? I'd have thought it was a
rather obscure combination. Is it perhaps more common
than I'd suspected, or do GCC and
On 2022-04-21 00:19, Seymour J Metz wrote:
That has at least two bugs: the first test will incorrectly treat 1*-1
The task is to form the product of two POSITIVE integers.
as having an overflow and the second test is testing all of R0,
The second test must test R1, as shown, not R0.
not
On 2022-04-20 23:46, Ian Worthington wrote:
Whilst looking at reliable techniques to detect signed and unsigned
overflow in integer multiplication I was checking out the late John
Erhman's "Assembler Language Programming for IBM System z™ Servers" in
which I discovered he presented this problem
On 2022-04-19 02:03, Don Higgins wrote:
What instructions take fixed quadword operas? I imagine some variant
of
Divide.
Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1.
But
since the dividend is in registers, there is no requirement for quad
word
alignment.
He is
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Saturday, April 16, 2022 1:57 PM
Subject: Re: Next instruction not needed
On Apr 15, 2022, at 21:30:35, Robin Vowels wrote:
R0 doesn't count because
read what I wrote, you will see that I explicitly quoted
3 registers for filling a block.
.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Robin Vowels [robi...@dodo.com.au]
Sent: Friday, April 15, 2022 11:28 PM
- Original Message -
From: "Tom Harper"
Sent: Saturday, April 16, 2022 4:19 AM
I think that is unnecessary because the proposal is only for one to 256 bytes
so no need to make it interruptible. If you want to use for longer areas, use a
move long.
For shorter areas, use MVCL.
From: "Tom Harper"
Sent: Saturday, April 16, 2022 3:10 AM
For a fixed length move, none.
You can use MVC for that. And XC.
For a variable length move, one.
For which MVCL is eminently suitable.
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- Original Message -
From: "Steve Smith"
To:
Sent: Saturday, April 16, 2022 2:49 AM
Subject: Re: Next instruction needed
Tom Harper made a perfectly clear proposal, that evidently only you cannot
comprehend.
The proposal is clearly irrational, and for a need that almost doesn't
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Saturday, April 16, 2022 2:48 AM
On Apr 15, 2022, at 10:27:47, Robin Vowels wrote:
On 2022-04-16 02:23, Tom Harper wrote:
As mentioned, R0.
Make up your mind! You just said that no registe
On Apr 15, 2022, at 5:08 AM, Robin Vowels wrote:
- Original Message - From: "Tom Harper"
To:
Sent: Friday, April 15, 2022 3:06 AM
IMHO, the next instruction to add to z/Architecture would be an instruction to clear storage to
zeros.
Who needs it? I cannot recall e
On 2022-04-16 02:23, Tom Harper wrote:
On Apr 15, 2022, at 12:20 PM, Robin Vowels
wrote:
On 2022-04-16 00:25, Tom Harper wrote:
Well known. But the instruction I’m proposing has no registers
involved
Oh? How do you propose that such an instruction move
N bytes (where N is variable
is that
the instruction be resumeable and for the hardware/microcode/millicode
to periodically check for pending interrupts and update the registers
as needed
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Robin
- Original Message -
From: "Tom Harper"
To:
Sent: Friday, April 15, 2022 3:06 AM
IMHO, the next instruction to add to z/Architecture would be an instruction to clear storage to
zeros.
Right now a number of methods are in widespread use, none of which are clean and simple. I mean,
On 2022-04-15 00:31, Seymour J Metz wrote:
The S/360 architecture uses two's complement arithmetic, and that
remains the case through z. Accordingly, signed and unsigned
arithmetic are the same except for the condition code, except when
sign extension is an issue, e.g., adding a word to a grande
From: "Bob Raicer"
Sent: Wednesday, March 09, 2022 5:04 AM
You might want to consider using this (or a similar) code sequence.
It eliminates the use of EXECUTE instructions and verifies that the
length of the source data is acceptable, i.e., the length is
positive and does not exceed the
On 2022-03-08 09:16, Dave Clark wrote:
I'm confused... I don't understand why the TEST DECIMAL
instruction is rejecting the following situation. Instead of dropping
down to the second execute instruction, it is falling into the error
reporting logic. Why is that?
R1 => x'0108010C'
R2 == 4
The TRT instruction is useful in locating
one or more specific characters, such as a decimal point.
On 2022-02-17 01:42, Dave Clark wrote:
Thanks for all the help so far. Things are looking good. I've
reached the point, now, where I need to transform a zoned-decimal
number
with up to 31
On 2022-02-13 12:21, Seymour J Metz wrote:
Why not CVB/LTR/BC?
Nice suggestion, but it's a huge sledgehammer!
Shmuel (Seymour J.) Metz
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU]
on behalf of Paul Gilmartin
From: "Dave Clark"
Sent: Saturday, February 12, 2022 9:44 AM
"IBM Mainframe Assembler List" wrote on
02/11/2022 05:27:48 PM:
Thanks, we'll see how this works. ;-)
ZAP_IT ZAP PWORK16(0),0(0,R1) (SEE EXECUTE INSTRUCTION BELOW)
...snip...
LHI R2,15*16
- Original Message -
From: "Charles Mills"
Sent: Saturday, February 12, 2022 9:27 AM
EX is independent of the format of the target instruction. You can EX
anything (except EX). It just plugs that second byte of the target
instruction. You can EX an LR and vary which registers get
- Original Message -
From: "Dave Clark"
To:
Sent: Saturday, February 12, 2022 9:03 AM
How do (can?) you EXecute a ZAP instruction? I have a packed
number in plain character format that can vary in length from 1 to 16
bytes. I need to move that into a 16-byte formal packed
- Original Message -
From: "Dave Clark"
To:
Sent: Saturday, February 12, 2022 5:00 AM
Subject: Rules for Zoned Overpunch
I know that x'F1' and x'C1' are positive and that x'D1' is
negative. But what if I find x'A1', x'B1', or x'E1' for overpunch values?
What is the shortest
It will help if you define the operands, e.g.,
divisor DS CL5
quotient DS CL5
remainder DS CL5
dividend EQU quotient
In storage, the remainder follows the quotient.
The first operand (dividend) is quotient+remainder.
The remainder is the same size as the second operand (divisor).
Thus,
DP
May I suggest not obfuscating the program?
ZAP is a trivial instruction for the job,
and does not need a constant area.
On 2022-01-28 00:04, Frank M. Ramaekers wrote:
I simply moved null bytes to overlay the result (I could have XC them
as well).
DPWKPACK,KDAYSQC
…
MVC
On 2022-01-27 04:45, Frank M. Ramaekers wrote:
Will this instruction work?
ZAP WKPACK,WKPACK+(L'WKPACK-L'KDAYSQC) Expand remainder
In other words, can one expand the remainder from a DP instruction to
the entire field?
The field can be expanded.
Ensure that the right-most byte of
On 2022-01-08 07:25, Steve Smith wrote:
Well, I'm not familiar with the VPKZ, and if not available, or
traditionally, you must code two PACKs for pieces of zoned fields
longer
than 16 bytes.
If you use two PACK instructions, it helps to PACK the upper
bytes first.
Same applies conversely
On 2021-11-30 00:06, Peter Relson wrote:
I wrote
For z/OS, this question relates to each work unit and the question is
"does the work unit use FPRs 8-15 or VRs?".
If the answer is no, then that work unit does not save/restore those
regs
upon undispatch/redispatch and thus saves some cycles.
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Phil Smith III
[li...@akphs.com]
Sent: Saturday, November 13, 2021 11:10 AM
Subject: Re: Curious compiler optimization
Unoptimised code typically has redundant instructions.
For example, a store instruction to
- Original Message -
From: "Phil Smith III"
To:
Sent: Friday, November 12, 2021 10:58 AM
Subject: Curious compiler optimization
IBM XLC on z/OS 2.4, under USS.
With NOOPT:
* int var = 0;
LA r4,0
LR r0,r4
ST r0,var(,r13,160)
That's an interesting way to
From: "Schmitt, Michael"
Sent: Thursday, March 11, 2021 10:26 AM
I was taught long ago to add 1 to a register using LA r#,1(,r#) and to subtract
1 using BCTR r#,0.
Is the fastest way now to use AHI r#,1 and AHI r#,-1?
LA and BCTR are good when you don't want to change the CC.
BCTR R,0
- Original Message -
From: "Tony Thigpen"
To:
Sent: Saturday, October 24, 2020 1:55 AM
Subject: Re: Reversed string macro
Robin,
The discussion (which I started)
The "discussion" was started by Steve Smith (also confirmed from the below
letter).
is about using a macro to
- Original Message -
From: "Willy Jensen"
Sent: Wednesday, October 21, 2020 12:04 AM
Extract from a larger macro. And no, I was not overly concerned with
performance.
.* r15 : length
.* r14 -> source
From: "Steve Smith"
Sent: Tuesday, August 11, 2020 11:07 AM
The worst way to zero a register is more interesting. JCTG Rx,* is my
favorite. If Rx is already 0, guess how long that will take.
How about:
BCT1,*
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From: "Steve Smith"
Sent: Tuesday, August 11, 2020 11:07 AM
The worst way to zero a register is more interesting. JCTG Rx,* is my
favorite. If Rx is already 0, guess how long that will take.
Sorry, wouldn't
M r,=F'0'
take even longer?
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From: "Steve Smith"
Sent: Tuesday, August 11, 2020 11:07 AM
For the whole register, LGHI, LLILL (or HL, LH, or HH) are best. LLILF,
LLIHF take up more space. XGR, SGR, SLGR set the CC.
For only the low half, XR, SR, SLR have the shortness advantage, and LHI
the non-CC advantage.
From: "Rupert Reynolds"
Sent: Tuesday, August 11, 2020 11:03 AM
I've not seen SLR, but my comment based on 1990s knowledge is that it's
best to keep it simple. Don't access storage unnecessarily (such as L
Rn,=F'0') and any of the more obvious methods (such as "LA Rn,0" "SR Rn,Rn"
or "XR
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Tuesday, August 11, 2020 8:51 AM
On 2020-08-10, at 16:28:28, Steve Smith wrote:
The only difference between SR & SLR is how they set the condition code.
If that could produce a
From: "Gary Weinhold"
Sent: Tuesday, August 11, 2020 7:49 AM
it may go back to the idea that SR might require an extra step to
set/propagate the sign while SLR wouldn't.
Subtraction requires that the second operand is complemented,
unity is added, and the operands are summed.
The sign is
- Original Message -
From: "Steve Smith"
To:
Sent: Sunday, August 09, 2020 12:23 PM
Sheesh... I missed it somehow, but it is in there. ED & EDMK did support
ASCII mode, and used x'3x' zones in that case.
This old, possibly original
The "-0" version of IBM manuals is always the
- Original Message -
From: "Charles Mills"
To:
Sent: Sunday, August 09, 2020 11:29 AM
ED was not part of the original S/360 instruction set? Did you look under
Decimal Instructions?
It isn';t under "Decimal Instructions".
Try the chapter, Logical Instructions.
---
This email has
- Original Message -
From: "Steve Smith"
To:
Sent: Sunday, August 09, 2020 10:57 AM
Subject: Re: Case Study: IBM SYSTEM/360-370 ARCHITECTURE (1987)
The ASCII feature of S/360 probably wasn't used because it's nearly
useless.
What? See my earlier report that no IBM operating
- Original Message -
From: "Dave Wade"
Sent: Friday, June 05, 2020 7:29 PM
Subject: Re: Convert *signed* EBCDIC to packed decimal
As a demonstrator of the "baby computer" replica at Manchester I would say
that it seems there was not much to choose between the two, if not in tube
From: "Seymour J Metz"
To:
Sent: Friday, June 05, 2020 9:09 PM
I quoted the time for the model 50.
Then why didn't you write "The 360/50 cycle time was 2 microseconds."?
accidental omission. The info I obtained from a friend (for confirmation)
where the context was the model 50.
---
- Original Message -
From: "Dave Wade"
To:
Sent: Friday, June 05, 2020 7:39 PM
-Original Message-
From: IBM Mainframe Assembler List On Behalf Of robi...@dodo.com.au
Sent: 05 June 2020 00:39
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
On 2020-06-05 08:24, Seymour J Metz wrote:
>
Yes, that's what START did.
I wrote a single-pass S/360 assembler for teaching purposes.
One of the purposes was to assemble to location 0,
using absolute addressing. (Yes, I know that the low assresses on the real
machine were not available fot that purpose, but with START 0
& base register 0,
From: "Seymour J Metz"
To:
Sent: Wednesday, June 03, 2020 7:00 AM
Paging? The conventional wisdom has always been to stay within one base
register,
The XPL compiler used multiple base registers.
so for systems with 4K pages that isn't an issue. I tend to use LOCTR so that constants
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Wednesday, June 03, 2020 3:26 AM
Subject: Re: z/OS HLASM: EQU for statement labels
On 2020-06-02, at 10:58:00, David Woolbright wrote:
I’’m just a humble academic so I hesitate to
- Original Message -
From: "Charles Mills"
To:
Sent: Tuesday, June 02, 2020 7:07 AM
I use 0H if it is the beginning of a section of code and there might be an
odd-length DC
in front of it. But I use * when I am jumping around one instruction.
Revealing my age, I got in the
- Original Message -
From: "Schmitt, Michael"
Sent: Tuesday, June 02, 2020 6:43 AM
In John R. Ehrman's SHARE presentations on tips for modernizing
IBM z/Architecture assembler programs (such as
https://share.confex.com/share/120/webprogram/Handout/Session12522/modrnasm.pdf),
he says
From: "Charles Mills"
Sent: Tuesday, December 11, 2018 8:33 AM
It is a way of forcing a condition code of "high." (Too lazy to look up the bit
value.)
Crummy coding.
Similarly *,255 would force "low" and CR 0,0 would force "equal/zero."
ditto.
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From: "Alan Atkinson"
Sent: Saturday, December 08, 2018 1:34 PM
So smelly or not we have a lot of stuff that branches conditionally based on
return codes
Nothing unusual about that.
Has nothing to do with condition codes.
from whatever was just called. CLI *,0 and *,255 along with CR
From: "esst...@juno.com"
Sent: Saturday, December 08, 2018 12:49 AM
Binyamin Thank YouThose are the two instructions I could not remember
There's a good programming manual available.
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From: "Brent Longborough"
Sent: Friday, December 07, 2018 11:24 PM
IMHO this is a Code Smell.
If you need the CC in order to print it out for debugging, it's probably
more useful to print the data that led to that CC.
If you want to save the CC, go off somewhere and do something else, and
BALR
On 7/12/2018 9:14 AM, esst...@juno.com wrote:
Hi,I seeem to recall am instruction that returned the last/current condition
code. Does any one Know the name of this instruction or its OP code ?
.
.
Paul D'Angelo
.
.
From: "Dan Greiner"
Sent: Tuesday, August 07, 2018 8:12 AM
I was once asked why the execute exception existed. That is, why not just let
the hardware —
or, in this odd case, the firmware — cascade down a chain of multiple EX
instructions,
ORing the bits of the R1 field with the subsequent
mes as you want;
1F refers to the next label of 1 and 1B refers to the immediately previous label of 1, so there's
no ambiguity.
From: IBM Mainframe Assembler List on behalf of Robin Vowels
Sent: Sunday, August 5, 2018 9:21 PM
To: ASSEMBLER-LIST@listse
From: "Martin Ward"
Sent: Monday, August 06, 2018 6:40 PM
On 06/08/2018 02:30, Robin Vowels wrote:
And anyway, why would you want to EX an EX?
To cause an ABEND after an error, of course!
I have seen "EX 0,*" in production code to do this
(along with &quo
- Original Message -
From: "Steve Thompson"
To:
Sent: Monday, August 06, 2018 4:21 AM
Subject: Re: EX
On 08/05/2018 08:13 AM, Robin Vowels wrote:
From: "Paul Gilmartin"
<0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Friday, August 03, 2018 3:09
From: "Seymour J Metz"
Sent: Monday, August 06, 2018 6:05 AM
We were all very conscious of "economy in all things programming" in those
days.
We? I've been programming since 1960, and I was never concerned with how much space the source code
took.
Right, that was unimportant. And at 200
From: "Seymour J Metz"
Sent: Monday, August 06, 2018 5:52 AM
Technical Assembly Systemm (TASS) on the 650 had something called a program
point.
A program point was a one digit label, and the references to program points
were suffixed
with B for backwards and F for forward. It is perhaps the
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Friday, August 03, 2018 3:09 AM
A principal use of EX is to be able to use a register mask to modify the
target. CDC 3800 had a clever alternative to this, a modify-next-instruction
instruction (I forget what it was
From: "Tom Marchant" <00a69b48f3bb-dmarc-requ...@listserv.uga.edu>
Sent: Saturday, August 04, 2018 3:44 AM
On Fri, 3 Aug 2018 12:03:02 -0400, Tony Thigpen wrote:
I was taught that to make it easy to read, do the following:
BL *+4+2
LR R1,R2
How about
THIS BL
From: "Mark Hammack"
Sent: Saturday, August 04, 2018 2:16 AM
In 1985 (first MF assembler gig, I had been doing PC programming before
that), we were using Assembler H on MVS/XA (as I recall). Our shop
standard was to use EQU * for labels
Poor pprogramming practice.
and ALWAYS code a a
From: "Tony Thigpen"
Sent: Saturday, August 04, 2018 2:03 AM
I was taught that to make it easy to read, do the following:
BL *+4+2
LR R1,R2
or
BL *+4+2+4
LR R1,R2
LA R3,0(,r1)
It may not look right in your email, but the branched around
instructions
From: "Charles Mills"
Sent: Saturday, August 04, 2018 1:12 AM
We were all very conscious of "economy in all things programming" in those
days. A label occupied a physical punched card or 80 bytes of precious DASD
space.
DASD space was not precious. Nor were cards (cheap as chips).
And the
From: "Hobart Spitz"
Sent: Friday, August 03, 2018 8:59 AM
I think we are missing some points here. If you put a label on an
instruction, the symbol is defined with the correct length (2, 4, or 6),
and a type of C'I'.
Why? It's an instruction,. It is the subject of a branch,
or a
From: "Christopher Y. Blaicher"
Sent: Thursday, August 02, 2018 11:17 AM
Inline data is no more expensive than data in another page. In either case, the reference to the
data requires a cache line load to the D-cache, but does not invalidate/disturb the I-cache.
A comment on the original
From: "Steve Smith"
Sent: Friday, July 20, 2018 2:26 AM
An issue I raised on IBM-MAIN led to discussing how to round an address to
a 16-byte (quad-word) boundary. The C example included the expression
p &= -16;.
Won't this truncate, not round?
You'd need to add 15 and then "and".
I
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Thursday, July 19, 2018 8:00 AM
Generally. Of course HLASM is all but untyped. A might mean an integer
constant, especially since A supports expressions while F somewhat
inexplicably does not. You can code
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