Re: Does the z architecture have something like the SIMD instructions
My bad! The current edition is SA22-7832-12. I had the latest z15 model on my mind, hence the -15 typo.
Re: Does the z architecture have something like the SIMD instructions
SA22-7832-15??? The latest version I have is SA22-7832-12, and I've been looking for SA22-7832-13 since the z15 T02 was GA'd last month with 30 new instructions. Has anyone seen the POPS for the z15 T02? Robert Ngan HCL Technologies (USA) -Original Message- From: IBM Mainframe Assembler List On Behalf Of Dan Greiner Sent: Friday, June 5, 2020 13:57 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Although it does actually access multiple data items, PERFORM LOCK OPERATION (PLO) really doesn't qualify as a SIMD instruction (see my PLO screed below). Seymour's reference to the Wikipedia page (https://clicktime.symantec.com/3NjuMxE6MEZBEJLxW7KRK1C7Vc?u=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FSIMD) is about as adequate a definition as any I've seen. As I recall, IBM's original implementation of vector instructions appeared as an optional extension to ESA/390, but these were never part of the standard architecture defined in the PoO. With the advent of the z13 (2015), IBM added vector instructions to the general architecture, and added Chapters 21-24 to the PoO. There are 32 vector registers, each having 128 bits ... but the 64 bits of VRs 0-15 are the same as floating-point register 0-15. This is not to say that VRs are necessarily floating-point entities; they can be binary integers, strings, or floating point. With the introduction of the z14 (2017), IBM added (a) new instructions that enhanced the existing VR facility, and (b) a vector packed-decimal facility (the latter being a benefit to COBOL and other packed players). With the introduction of the z15 (2019), IBM added a second enhancement to the VR facility. There are now around 190 separate vector instructions — with a mind-boggling array of extended mnemonics. If you haven't bothered to download a PoO in the last few years, it's worth it (but if you choose to print it, have two reams of paper handy). Check out SA22-7832-15 for the latest version. Regarding PLO, this provides the means by which multiple, discontiguous storage locations can appear to be updated atomically without having to bother acquiring a lock. However, in order for PLO to operate properly, EVERY program that inspects or modifies those storage locations also has to do it with PLO. This is because the firmware for PLO gets its own lock in HSA, and serializes other CPUs attempts to use PLO with that lock. If other programs on other CPUs examine the data, the updates do not necessarily appear to be atomic. And, if some programs use PLO and others try to perform updates with classic compare-and-swap logic, really BAD things happen (as certain z/OS developers have discovered more than once). If nobody was actually using PLO, I would have quietly proposed removing it from the architecture, but (alas) there are some OS components that have actually managed to use it properly. For a far more flexible (and higher performance) means of atomic updates of multiple storage locations, check out the transactional-execution facility introduced in the z12 (2012). DXC Technology Company - Headquarters: 1775 Tysons Boulevard, Tysons, Virginia 22102, USA. DXC Technology Company -- This message is transmitted to you by or on behalf of DXC Technology Company or one of its affiliates. It is intended exclusively for the addressee. The substance of this message, along with any attachments, may contain proprietary, confidential or privileged information or information that is otherwise legally exempt from disclosure. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate any part of this message. If you have received this message in error, please destroy and delete all copies and notify the sender by return e-mail. Regardless of content, this e-mail shall not operate to bind DXC Technology Company or any of its affiliates to any order or other contract unless pursuant to explicit written agreement or government initiative expressly permitting the use of e-mail for such purpose.
Re: Does the z architecture have something like the SIMD instructions
Only if the symbols that you are using are the conventional 0123456789ABCDEf; what if you're using, e.g., U+2080 through U=2089 and U+1D400 through U+1D405. (superscript digits, Mathematical letters)? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Martin Ward [mar...@gkc.org.uk] Sent: Monday, June 8, 2020 3:52 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 07/06/2020 21:57, Seymour J Metz wrote: > I will admit that the UNPK/TR technique won;t work so well with > Unicode, but then neither will TROT. For the sixteen hex characters, Unicode UTF-8 encoding is the same as ASCII :-) -- Martin Dr Martin Ward | Email: mar...@gkc.org.uk | http://secure-web.cisco.com/1xXjNV7QcCHEFHAXuPn93_e1NnXhxzFNO_O8VoTYqrt8PO-y5e0JmcByEtLPDDpGUWli1PxcZ4GiXX9qXhMWnNQGXtdP8KgzA5lVyzxE1QZIO5sHPrlnTQcgwRkLH0TXbVwSzkG7nqckhcvj_AXpP5sgcZ_qR_0UL9NP-O1tG3RmCKsRa9ddyn8xymxq37z--T9o4IkaxGK5gKR_r3g9ILPffW7B99MVVHi6xfszyonMqprl66qZkfhsoll9Cd98k6GnMHkFf3czejiL2BpBIoBO7ma4I_s0q5eJHemXMtnq7L2CJaQADcm5sfWeGvWclAezzWC70RgN8eDdD7mFKS8FyGCywDcCYM7-UUbdFvVnzEWUF6RBPyxRAZHKOSsYQElRcFPfwzit6ltKiv5acdJWo3Gx9hoW0RvbqlHH3xTQFZg-XP_QGW0ITu32ZORkUw9IIXp-iuSDYzPeLOhasUg/http%3A%2F%2Fwww.gkc.org.uk G.K.Chesterton site: http://secure-web.cisco.com/1wn17M34rxn966VY6N2Q7gSDgRAnzTpRfZ7nKFpEHh3rgQputgYF0ODlPgMQZ7eCZbPviWtGtjUax73gARavS9butgNDHeAygNolt9lrUirzp7E3GgkFG_9lmi7faPviNzBDk8etFLHpYj3maJwh0T9aPmlhRaK-Jh8efq-bXEdBr_IJUSLx38a3PfRiRgyJTPgtoeEfTTK2JTYEIDZbgf4Ehtf81brJD0i-diFPYwpmYIz8n0CVbTKzwOwUTSNKtKgSXCt9plGmW_oYQpf0Krl0ExYPgEzXR3QTB2LaUeT_LnqXGBLmB4tT4-NEHcnu2H14L8q1FY3TJyCBPb47wbOnjc7BfgvNcPMU1Yqvi64PNouHYrZkZ9HSFBvdxMIeF17dXoxq_Ywj9eBpp7RY2m1cL6bQ02xJ9yFOlWmwaG7xyiYoKP5kPTqm8520fxobnJNcwxMIlM9aYQ15IQcfcUw/http%3A%2F%2Fwww.gkc.org.uk%2Fgkc | Erdos number: 4
Re: Does the z architecture have something like the SIMD instructions
On 07/06/2020 21:57, Seymour J Metz wrote: I will admit that the UNPK/TR technique won;t work so well with Unicode, but then neither will TROT. For the sixteen hex characters, Unicode UTF-8 encoding is the same as ASCII :-) -- Martin Dr Martin Ward | Email: mar...@gkc.org.uk | http://www.gkc.org.uk G.K.Chesterton site: http://www.gkc.org.uk/gkc | Erdos number: 4
Re: Does the z architecture have something like the SIMD instructions
Yes, of course. They say that the mind is the second thing to go - I can't remember the first. Thanks. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Martin Truebner [mar...@pi-sysprog.de] Sent: Monday, June 8, 2020 8:22 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions >> F1F2F3F3 to 0001 0010 0011 0100 you ment F1F2F3F3 to 00010010 00110100 or? -- Martin Trübner; everything around "PoOps of z/arch" Teichstraße 39E D-63225 Langen F: +49 6103 71254 M: +49 171 850 7132 E: mar...@pi-sysprog.de
Re: Does the z architecture have something like the SIMD instructions
>> F1F2F3F3 to 0001 0010 0011 0100 you ment F1F2F3F3 to 00010010 00110100 or? -- Martin Trübner; everything around "PoOps of z/arch" Teichstraße 39E D-63225 Langen F: +49 6103 71254 M: +49 171 850 7132 E: mar...@pi-sysprog.de
Re: Does the z architecture have something like the SIMD instructions
> Nope -- display to hex, i.e. c'1234' to x'1234' That's a representation in assembler notation of a 4 byte field and a two byte field, with the value on the left being hexadecimal and the value on the right being the equivalent binary value: F1F2F3F3 to 0001 0010 0011 0100 -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Monday, June 8, 2020 7:44 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Nope -- display to hex, i.e. c'1234' to x'1234' -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 08 June 2020 12:41 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I might believe hex to binary, with the 16 symbols in an 8 bit encoding. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Monday, June 8, 2020 2:33 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I did create a macro to build the table -- and one for TRTO, to convert display to hex. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 23:05 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Well, any set of 16 symbols encoded in 8 bits; it doesn't work so well with, e.g., Unicode. My intent for PoOps was to illustrate that UNPK is not just a decimal instruction. As for TROT, it would depend on whether the degree of use justified the larger translate table. If I went that way I would be tempted to write a macro to generate a table, although it isn't that hard with a decent editor, e.g., ISPF, SECIT. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Sunday, June 7, 2020 1:39 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Do you mean conversion to printable hex, e.g. convert x'1234' to x'f1f2f3f4'? These days, I use the TROT instruction. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 19:21 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an
Re: Does the z architecture have something like the SIMD instructions
Nope -- display to hex, i.e. c'1234' to x'1234' -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 08 June 2020 12:41 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I might believe hex to binary, with the 16 symbols in an 8 bit encoding. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Monday, June 8, 2020 2:33 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I did create a macro to build the table -- and one for TRTO, to convert display to hex. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 23:05 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Well, any set of 16 symbols encoded in 8 bits; it doesn't work so well with, e.g., Unicode. My intent for PoOps was to illustrate that UNPK is not just a decimal instruction. As for TROT, it would depend on whether the degree of use justified the larger translate table. If I went that way I would be tempted to write a macro to generate a table, although it isn't that hard with a decent editor, e.g., ISPF, SECIT. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Sunday, June 7, 2020 1:39 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Do you mean conversion to printable hex, e.g. convert x'1234' to x'f1f2f3f4'? These days, I use the TROT instruction. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 19:21 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system. -- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Re: Does the z architecture have something like the SIMD instructions
I might believe hex to binary, with the 16 symbols in an 8 bit encoding. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Monday, June 8, 2020 2:33 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I did create a macro to build the table -- and one for TRTO, to convert display to hex. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 23:05 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Well, any set of 16 symbols encoded in 8 bits; it doesn't work so well with, e.g., Unicode. My intent for PoOps was to illustrate that UNPK is not just a decimal instruction. As for TROT, it would depend on whether the degree of use justified the larger translate table. If I went that way I would be tempted to write a macro to generate a table, although it isn't that hard with a decent editor, e.g., ISPF, SECIT. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Sunday, June 7, 2020 1:39 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Do you mean conversion to printable hex, e.g. convert x'1234' to x'f1f2f3f4'? These days, I use the TROT instruction. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 19:21 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system. -- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Re: Does the z architecture have something like the SIMD instructions
I did create a macro to build the table -- and one for TRTO, to convert display to hex. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 23:05 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Well, any set of 16 symbols encoded in 8 bits; it doesn't work so well with, e.g., Unicode. My intent for PoOps was to illustrate that UNPK is not just a decimal instruction. As for TROT, it would depend on whether the degree of use justified the larger translate table. If I went that way I would be tempted to write a macro to generate a table, although it isn't that hard with a decent editor, e.g., ISPF, SECIT. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Sunday, June 7, 2020 1:39 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Do you mean conversion to printable hex, e.g. convert x'1234' to x'f1f2f3f4'? These days, I use the TROT instruction. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 19:21 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system. -- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Re: Does the z architecture have something like the SIMD instructions
Thanks Ed. Already received. It sure would be helpful to have someone with the tutorial and writing skills of John Ehrman to put together an extended explanation that covered all the varieties of vector facilities we now have. The less we know the farther behind we get from the HLL compiler writers using their intimate knowledge of the new facilities and how to use them *effectively*. I'm not afraid of HLL's (I make my living using them) but as assembler coders we ought to know how to do the same work with the same effectiveness. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 6:24 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote: > Is there any chance you could provide (maybe eventually in a SHARE session > presentation?) a set of good examples of using the vector instructions as you > say you do? Peter, There was a thread called "Count Words" into which at one time I posted some pseudo code and/or an example of our generalized string find code that went into the field with (E)JES in Sep 2016. I endured wise cracks, imagined 16-byte limitations, and erroneous claims to the effect: we were using the wrong instructions, performance no longer matters, such coding is best left to compilers, etc. Rather than deal with any more of that "static," I've decided to directly email you a copy of Slide 21 from my March 2017 SHARE San Jose session entitled, "z13s User Experiences" (which won a best session award BTW) in which I touted the new Vector Facility as being a "game changer" for our platform and provided sample code anyone can use to replaces SRST with a loop of vector instructions. Thanks... -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
Re: Does the z architecture have something like the SIMD instructions
I thought that I was cynical, but I would not have predicted it. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Kerry Liles [kerry.li...@gmail.com] Sent: Sunday, June 7, 2020 9:57 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, I too would be interested in your presentation from March 2017 SHARE ... I can only imagine the barrage of knee-jerk responses you likely encountered. Sad but unfortunately predictable. regards, Kerry Liles On Sun, 7 Jun 2020 at 18:23, Ed Jaffe wrote: > On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote: > > Is there any chance you could provide (maybe eventually in a SHARE > session presentation?) a set of good examples of using the vector > instructions as you say you do? > > Peter, > > There was a thread called "Count Words" into which at one time I posted > some pseudo code and/or an example of our generalized string find code > that went into the field with (E)JES in Sep 2016. > > I endured wise cracks, imagined 16-byte limitations, and erroneous > claims to the effect: we were using the wrong instructions, performance > no longer matters, such coding is best left to compilers, etc. > > Rather than deal with any more of that "static," I've decided to > directly email you a copy of Slide 21 from my March 2017 SHARE San Jose > session entitled, "z13s User Experiences" (which won a best session > award BTW) in which I touted the new Vector Facility as being a "game > changer" for our platform and provided sample code anyone can use to > replaces SRST with a loop of vector instructions. > > Thanks... > > -- > Phoenix Software International > Edward E. Jaffe > 831 Parkview Drive North > El Segundo, CA 90245 > https://secure-web.cisco.com/1NHljwdIbMHXIaBdyDWCAwFHvBswn2N8TE-tMXDX6qMM_iRCQgrx7LjjckSfsxacJhM_JxM4evtTAjUeOFYzQPe7Xcn4b0vuwI6EgTZbJa3HGxL4kzY_jyvqcEvfbUZRRwl8qPAhQ7xVjgFDCQf4nx3n8RyvC8JEOY-2BazrQH6akCTVXbhzyQ_J8evtapPyGPp3P4nEyPK_IbhJN_v4KB437fpx-ToLHBnWxxNZ8xIeKjrzn3aIprRcGbESiBM5lV03_poFfo1KZnhecmUyCxgRM3e4Of-STVCecm_WUKdvSFRxGu8Su7XXwqG2jZaTvsuzNF1p4PvadRi-DKw63Sp0XgE68mvj8nuzbUw2SP2T7p-bOQfGQbp2d9FpGO5jRCkSqYgUNs-ubfVflc34ULOz81kGSCgpiNovI9tFAMlZoTIvrns17SCcWmj-xJA83/https%3A%2F%2Fwww.phoenixsoftware.com%2F > > > > > This e-mail message, including any attachments, appended messages and the > information contained therein, is for the sole use of the intended > recipient(s). If you are not an intended recipient or have otherwise > received this email message in error, any use, dissemination, distribution, > review, storage or copying of this e-mail message and the information > contained therein is strictly prohibited. If you are not an intended > recipient, please contact the sender by reply e-mail and destroy all copies > of this email message and do not otherwise utilize or retain this email > message or any or all of the information contained therein. Although this > email message and any attachments or appended messages are believed to be > free of any virus or other defect that might affect any computer system > into > which it is received and opened, it is the responsibility of the recipient > to ensure that it is virus free and no responsibility is accepted by the > sender for any loss or damage arising in any way from its opening or use. >
Re: Does the z architecture have something like the SIMD instructions
Ed, I too would be interested in your presentation from March 2017 SHARE ... I can only imagine the barrage of knee-jerk responses you likely encountered. Sad but unfortunately predictable. regards, Kerry Liles On Sun, 7 Jun 2020 at 18:23, Ed Jaffe wrote: > On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote: > > Is there any chance you could provide (maybe eventually in a SHARE > session presentation?) a set of good examples of using the vector > instructions as you say you do? > > Peter, > > There was a thread called "Count Words" into which at one time I posted > some pseudo code and/or an example of our generalized string find code > that went into the field with (E)JES in Sep 2016. > > I endured wise cracks, imagined 16-byte limitations, and erroneous > claims to the effect: we were using the wrong instructions, performance > no longer matters, such coding is best left to compilers, etc. > > Rather than deal with any more of that "static," I've decided to > directly email you a copy of Slide 21 from my March 2017 SHARE San Jose > session entitled, "z13s User Experiences" (which won a best session > award BTW) in which I touted the new Vector Facility as being a "game > changer" for our platform and provided sample code anyone can use to > replaces SRST with a loop of vector instructions. > > Thanks... > > -- > Phoenix Software International > Edward E. Jaffe > 831 Parkview Drive North > El Segundo, CA 90245 > https://www.phoenixsoftware.com/ > > > > > This e-mail message, including any attachments, appended messages and the > information contained therein, is for the sole use of the intended > recipient(s). If you are not an intended recipient or have otherwise > received this email message in error, any use, dissemination, distribution, > review, storage or copying of this e-mail message and the information > contained therein is strictly prohibited. If you are not an intended > recipient, please contact the sender by reply e-mail and destroy all copies > of this email message and do not otherwise utilize or retain this email > message or any or all of the information contained therein. Although this > email message and any attachments or appended messages are believed to be > free of any virus or other defect that might affect any computer system > into > which it is received and opened, it is the responsibility of the recipient > to ensure that it is virus free and no responsibility is accepted by the > sender for any loss or damage arising in any way from its opening or use. >
Re: Does the z architecture have something like the SIMD instructions
On 6/7/2020 9:23 AM, Farley, Peter x23353 wrote: Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Peter, There was a thread called "Count Words" into which at one time I posted some pseudo code and/or an example of our generalized string find code that went into the field with (E)JES in Sep 2016. I endured wise cracks, imagined 16-byte limitations, and erroneous claims to the effect: we were using the wrong instructions, performance no longer matters, such coding is best left to compilers, etc. Rather than deal with any more of that "static," I've decided to directly email you a copy of Slide 21 from my March 2017 SHARE San Jose session entitled, "z13s User Experiences" (which won a best session award BTW) in which I touted the new Vector Facility as being a "game changer" for our platform and provided sample code anyone can use to replaces SRST with a loop of vector instructions. Thanks... -- Phoenix Software International Edward E. Jaffe 831 Parkview Drive North El Segundo, CA 90245 https://www.phoenixsoftware.com/ This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: Does the z architecture have something like the SIMD instructions
Well, any set of 16 symbols encoded in 8 bits; it doesn't work so well with, e.g., Unicode. My intent for PoOps was to illustrate that UNPK is not just a decimal instruction. As for TROT, it would depend on whether the degree of use justified the larger translate table. If I went that way I would be tempted to write a macro to generate a table, although it isn't that hard with a decent editor, e.g., ISPF, SECIT. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Pieter Wiid [pw...@mweb.co.za] Sent: Sunday, June 7, 2020 1:39 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Do you mean conversion to printable hex, e.g. convert x'1234' to x'f1f2f3f4'? These days, I use the TROT instruction. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 19:21 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system. -- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Re: Does the z architecture have something like the SIMD instructions
Of course you can. There are no bit patterns in hexadecimal, only sixteen symbols. Nor do the symbols need to be EBCDIC; they could as well be ASCII. I will admit that the UNPK/TR technique won;t work so well with Unicode, but then neither will TROT. UNPK/TR is convenient when you only need to translate a few numbers, since it uses a much smaller translate table. The table sizes are probably not large enough for cache hits to be an issue. IAK, I want the UNPK/TRT example in order to emphasize that UNPK is not limited to decimal data. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Steve Smith [sasd...@gmail.com] Sent: Sunday, June 7, 2020 1:40 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. You can't "convert" binary to hexadecimal, their bit patterns are the same. If you're referring to displaying bytes' hexadecimal representation in EBCDIC, then I'd say it's a bit late for that. Thanks to a tip from Rob Scott on this list several years ago, I like using TROT, especially when writing out a considerable amount of storage, like a dump. The TROT table starts thus: DC C'000102030405060708090A0B0C0D0E0F' ... and continues for the obvious 15 more lines. sas
Re: Does the z architecture have something like the SIMD instructions
Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. You can't "convert" binary to hexadecimal, their bit patterns are the same. If you're referring to displaying bytes' hexadecimal representation in EBCDIC, then I'd say it's a bit late for that. Thanks to a tip from Rob Scott on this list several years ago, I like using TROT, especially when writing out a considerable amount of storage, like a dump. The TROT table starts thus: DC C'000102030405060708090A0B0C0D0E0F' ... and continues for the obvious 15 more lines. sas
Re: Does the z architecture have something like the SIMD instructions
Do you mean conversion to printable hex, e.g. convert x'1234' to x'f1f2f3f4'? These days, I use the TROT instruction. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: 07 June 2020 19:21 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system. -- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Re: Does the z architecture have something like the SIMD instructions
I thought that the descriptions of the vector instructions were a much easier read than the, e.g., sort, transaction, instructions. Something that I'd like to see inPoOps is an example of using UNPK and TR to convert binary to hexadecimal. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Farley, Peter x23353 [peter.far...@broadridge.com] Sent: Sunday, June 7, 2020 12:23 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
Re: Does the z architecture have something like the SIMD instructions
Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do? Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
Re: Does the z architecture have something like the SIMD instructions
On 6/7/2020 7:11 AM, Peter Relson wrote: That limitation is not the case for z/Architecture vector operations. I erred in writing that. Shmuel was of course correct. The "vector register" is 128 bits (one quadword). The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- Phoenix Software International Edward E. Jaffe 831 Parkview Drive North El Segundo, CA 90245 https://www.phoenixsoftware.com/ This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: Does the z architecture have something like the SIMD instructions
>>IBM has "Vector" instructions, but the size of a vector is limited to one >>quadword. >That limitation is not the case for z/Architecture vector operations. I erred in writing that. Shmuel was of course correct. The "vector register" is 128 bits (one quadword). The extent of the "vectorization" depends on the size of the operands. Peter Relson z/OS Core Technology Design
Re: Does the z architecture have something like the SIMD instructions
Excellent Ze'ev! Thank you for sharing. From: IBM Mainframe Assembler List on behalf of Ze'ev Atlas <01774d97d104-dmarc-requ...@listserv.uga.edu> Sent: Saturday, June 6, 2020 10:30 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Caution! This message was sent from outside your organization. Hi allI followed some advice her and yes, IBM has a pretty advanced SIMD architecture from z13 onward. I am not sure about previous attempts, but the current architecture seems to be pretty advanced. BTW IBM claims that with 'arch(12)' COBOL. PL/I, C, Java will use that facility at least partially see https://ibmsystemsmag.com/IBM-Z/01/2018/vector-facility-z14 [http://ibmsystemsmag.com//getattachment/c171a91d-6082-4cf8-89a1-e7a73f367569/arrows_nodes.jpg]<https://ibmsystemsmag.com/IBM-Z/01/2018/vector-facility-z14> How to Exploit the Vector Packed Decimal Facility in IBM z14 | IBM Systems Media<https://ibmsystemsmag.com/IBM-Z/01/2018/vector-facility-z14> ibmsystemsmag.com With the IBM announcement of the IBM z14 platform, new features became available, including a new instruction set for the decimal numbers using the Vector Facility. Ze'ev Atlas
Re: Does the z architecture have something like the SIMD instructions
Specifically, the vector instructions allow you to do various operations in parallel on data contained in a pair of quadword vector registers. There are also VECTOR LOAD MULTIPLE and VECTOR STORE MULTIPLE instuctions -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Ze'ev Atlas [01774d97d104-dmarc-requ...@listserv.uga.edu] Sent: Saturday, June 6, 2020 10:30 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Hi allI followed some advice her and yes, IBM has a pretty advanced SIMD architecture from z13 onward. I am not sure about previous attempts, but the current architecture seems to be pretty advanced. BTW IBM claims that with 'arch(12)' COBOL. PL/I, C, Java will use that facility at least partially see https://secure-web.cisco.com/18_tFg2_bubJGOnaMW7qnEwx4DBh_oCaBAsuhgiTGeA7fYHgo7YbyKOze-qOysUyaLLxZs6Bl8mhHkNSggpmJtS4VY9wa_dkIJr_0F_BE4CAUYKlq1pPTz2LsSXQq0rrs9kH8KSrLADzzQv-RP_WrZ8I6WAjAyVuV3NqiB5YMgWy0yVIi3Aptyg3bnYEafKecYhqYBOkHr5VTIcniQAsX6sow6t6JOiY2eIsNzvmkQvE9mIN3bk1NOZptY9mCW4bQFD2rGWdgioNvc6mrKn-g-7Cfr7D0_rT3lT8vLhfk3bthbXDvOxn1_RlNHWo9UBK82m1lReoaX3zsEjqpDsgcXlLWU1VjnQ3dsCVyx388VHrLLkcaC_NEiEPSOk2uT5M_BJNoXg0X8igqsqOPvVrr6UAP2z2g1mEWORWWGIP1qez-birIt9GLcPUGrfV_E5so/https%3A%2F%2Fibmsystemsmag.com%2FIBM-Z%2F01%2F2018%2Fvector-facility-z14 Ze'ev Atlas
Re: Does the z architecture have something like the SIMD instructions
Hi allI followed some advice her and yes, IBM has a pretty advanced SIMD architecture from z13 onward. I am not sure about previous attempts, but the current architecture seems to be pretty advanced. BTW IBM claims that with 'arch(12)' COBOL. PL/I, C, Java will use that facility at least partially see https://ibmsystemsmag.com/IBM-Z/01/2018/vector-facility-z14 Ze'ev Atlas
Re: Does the z architecture have something like the SIMD instructions
Are you referring to VECTOR LOAD MULTIPLE and VECTOR STORE MULTIPLE? I don't know of any other vector instructions that have more than two source quadwords and one destination quadword. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Peter Relson [rel...@us.ibm.com] Sent: Saturday, June 6, 2020 9:06 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions IBM has "Vector" instructions, but the size of a vector is limited to one quadword. That limitation is not the case for z/Architecture vector operations. To the question of the subject, simply, yes. There are SIMD instructions. Whether they are "the" SIMD instructions I don't know. Peter Relson z/OS Core Technology Design
Re: Does the z architecture have something like the SIMD instructions
IBM has "Vector" instructions, but the size of a vector is limited to one quadword. That limitation is not the case for z/Architecture vector operations. To the question of the subject, simply, yes. There are SIMD instructions. Whether they are "the" SIMD instructions I don't know. Peter Relson z/OS Core Technology Design
Re: Does the z architecture have something like the SIMD instructions
Yes, I know. Please review the history of this thread. Dan brought up the old
vector facility ("As I recall, IBM's original implementation of vector
instructions appeared as an optional extension to ESA/390, but these were never
part of the standard architecture defined in the PoO.") and I was commenting on
where it was documented.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Ed Jaffe [edja...@phoenixsoftware.com]
Sent: Friday, June 5, 2020 4:15 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Does the z architecture have something like the SIMD instructions
On 6/5/2020 12:15 PM, Seymour J Metz wrote:
> The S/370 PoOps mentions the vector facility and says "Vector operations are
> described in the publication IBM System/370 Vector Operations, SA22-7125."
>
> You can download it from
> http://secure-web.cisco.com/1TbjqUyY6y-gmFk5gWObf2XvhcQ9sqyf-J_rrlmoVuMPwoeX2PYGvk-JLNQJOvyqNeg51lhdVMQJhkvPIh2-aa2LLT3lTti7v6ewvxvXa6c9X_9rHXnMcbU6I7pEcHrj_lOB3yNb_y6dVE8JyUppk9wqWZEjiXqx1-o5dEG6XHHA0sAu3MKfYUwUdMPRZ3BQqNb7gqTuV_psWYZ08XbZQM7U4HNrhd25gJx26DnOiUWgKJG0nAP3fz3lSB85Tdbb5dijLOYZ_uE9TrvKGXDuJEDt5wVn30KusdUk7DZ76EZtRpIJi42Ed9WhSZOqW53RS2cj-gCf-yCZJfGeWn5pSfGoeVma7omeKHLdqPbpyo_C6FYI8lvOd4pjTo-BR_w6Io_1KX9cBRY585foNRZSj2_H1MJcCwjtyvD2VUKNRXRJb_BjtepowLqlVjG1YAM0C/http%3A%2F%2Fbitsavers.org%2Fpdf%2Fibm%2F370%2FvectorFacility%2FSA22-7125-3_Vector_Operations_Aug88.pdf
That old vector facility no longer exists on any modern mainframe.
There is a new one that is part of z/Architecture (starting with z13)
and doesn't require extra hardware features.
It is FAST!
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
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Re: Does the z architecture have something like the SIMD instructions
On 6/5/2020 12:15 PM, Seymour J Metz wrote: The S/370 PoOps mentions the vector facility and says "Vector operations are described in the publication IBM System/370 Vector Operations, SA22-7125." You can download it from http://bitsavers.org/pdf/ibm/370/vectorFacility/SA22-7125-3_Vector_Operations_Aug88.pdf That old vector facility no longer exists on any modern mainframe. There is a new one that is part of z/Architecture (starting with z13) and doesn't require extra hardware features. It is FAST! -- Phoenix Software International Edward E. Jaffe 831 Parkview Drive North El Segundo, CA 90245 https://www.phoenixsoftware.com/ This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: Does the z architecture have something like the SIMD instructions
The S/370 PoOps mentions the vector facility and says "Vector operations are described in the publication IBM System/370 Vector Operations, SA22-7125." You can download it from http://bitsavers.org/pdf/ibm/370/vectorFacility/SA22-7125-3_Vector_Operations_Aug88.pdf -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Dan Greiner [dan_grei...@att.net] Sent: Friday, June 5, 2020 2:56 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Although it does actually access multiple data items, PERFORM LOCK OPERATION (PLO) really doesn't qualify as a SIMD instruction (see my PLO screed below). Seymour's reference to the Wikipedia page (https://secure-web.cisco.com/1g9JjH5spQKTKip_YcVCSGxFPyS93bsF0rty3cayA3B2sZ2D4Q_El-WD75GMFVbcIZJHbWIdhnz469e8c96r3NQvd7MnrTdsIQegSzR5roKxSGwI3UJUFgG2cmwu22PBp8FShQeXm8O8D8JfdpCMC5LZvgP2ONFYFDRlByNSKUu-v2XTrrLoMUS10BP1xSiGJb729bBpfKoSFFuWCMkiDCKa1j1urk56bSobXkpIgGPXGpwibHEteCcsvsmN0OnEFlv7bpRAl7PWToJp0CJ88K6BhT-vIQPZp4oiUQqBIiCCRV4S-ztbTed7wno5eXxGUEQ2SO7DQMf6itV_ZR_UMptAT0vQigtdqmIzTpk6cQ0hoJZv4y1bPTmiNvuA7kAXnlMuWJxU0xkyApGW0Qgrz92gzowCKCkNd6HIam5wuiRAFEquej9eyAeTJl87GKprc/https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FSIMD%29 is about as adequate a definition as any I've seen. As I recall, IBM's original implementation of vector instructions appeared as an optional extension to ESA/390, but these were never part of the standard architecture defined in the PoO. With the advent of the z13 (2015), IBM added vector instructions to the general architecture, and added Chapters 21-24 to the PoO. There are 32 vector registers, each having 128 bits ... but the 64 bits of VRs 0-15 are the same as floating-point register 0-15. This is not to say that VRs are necessarily floating-point entities; they can be binary integers, strings, or floating point. With the introduction of the z14 (2017), IBM added (a) new instructions that enhanced the existing VR facility, and (b) a vector packed-decimal facility (the latter being a benefit to COBOL and other packed players). With the introduction of the z15 (2019), IBM added a second enhancement to the VR facility. There are now around 190 separate vector instructions — with a mind-boggling array of extended mnemonics. If you haven't bothered to download a PoO in the last few years, it's worth it (but if you choose to print it, have two reams of paper handy). Check out SA22-7832-15 for the latest version. Regarding PLO, this provides the means by which multiple, discontiguous storage locations can appear to be updated atomically without having to bother acquiring a lock. However, in order for PLO to operate properly, EVERY program that inspects or modifies those storage locations also has to do it with PLO. This is because the firmware for PLO gets its own lock in HSA, and serializes other CPUs attempts to use PLO with that lock. If other programs on other CPUs examine the data, the updates do not necessarily appear to be atomic. And, if some programs use PLO and others try to perform updates with classic compare-and-swap logic, really BAD things happen (as certain z/OS developers have discovered more than once). If nobody was actually using PLO, I would have quietly proposed removing it from the architecture, but (alas) there are some OS components that have actually managed to use it properly. For a far more flexible (and higher performance) means of atomic updates of multiple storage locations, check out the transactional-execution facility introduced in the z12 (2012).
Re: Does the z architecture have something like the SIMD instructions
Although it does actually access multiple data items, PERFORM LOCK OPERATION (PLO) really doesn't qualify as a SIMD instruction (see my PLO screed below). Seymour's reference to the Wikipedia page (https://en.wikipedia.org/wiki/SIMD) is about as adequate a definition as any I've seen. As I recall, IBM's original implementation of vector instructions appeared as an optional extension to ESA/390, but these were never part of the standard architecture defined in the PoO. With the advent of the z13 (2015), IBM added vector instructions to the general architecture, and added Chapters 21-24 to the PoO. There are 32 vector registers, each having 128 bits ... but the 64 bits of VRs 0-15 are the same as floating-point register 0-15. This is not to say that VRs are necessarily floating-point entities; they can be binary integers, strings, or floating point. With the introduction of the z14 (2017), IBM added (a) new instructions that enhanced the existing VR facility, and (b) a vector packed-decimal facility (the latter being a benefit to COBOL and other packed players). With the introduction of the z15 (2019), IBM added a second enhancement to the VR facility. There are now around 190 separate vector instructions — with a mind-boggling array of extended mnemonics. If you haven't bothered to download a PoO in the last few years, it's worth it (but if you choose to print it, have two reams of paper handy). Check out SA22-7832-15 for the latest version. Regarding PLO, this provides the means by which multiple, discontiguous storage locations can appear to be updated atomically without having to bother acquiring a lock. However, in order for PLO to operate properly, EVERY program that inspects or modifies those storage locations also has to do it with PLO. This is because the firmware for PLO gets its own lock in HSA, and serializes other CPUs attempts to use PLO with that lock. If other programs on other CPUs examine the data, the updates do not necessarily appear to be atomic. And, if some programs use PLO and others try to perform updates with classic compare-and-swap logic, really BAD things happen (as certain z/OS developers have discovered more than once). If nobody was actually using PLO, I would have quietly proposed removing it from the architecture, but (alas) there are some OS components that have actually managed to use it properly. For a far more flexible (and higher performance) means of atomic updates of multiple storage locations, check out the transactional-execution facility introduced in the z12 (2012).
Re: Does the z architecture have something like the SIMD instructions
Well, Wikipedia says "It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously.", which is how I recall the term being used, and those don't match. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Binyamin Dissen [bdis...@dissensoftware.com] Sent: Friday, June 5, 2020 11:20 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Well, PLO is certainly an example. But the relatively recent Transaction instructions greatly expand this. On Fri, 5 Jun 2020 04:56:53 + Ze'ev Atlas <01774d97d104-dmarc-requ...@listserv.uga.edu> wrote: :>I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. :>Ze'ev Atlas -- Binyamin Dissen http://secure-web.cisco.com/1w-cc8W0sRFs2o5i9Kfpz35p5OQTai31KwEm5O_mFKsjfWh63Gw-QWndxOp91IVUDeVaBW8s4oC0exxBXT9ZvSlqP-cn6jBqyqnfP7PkTz5qjb_Whjrwwc8j7Dj7nDb0iH1vFUcO8-UCNncgss_HwYR5phOO7_YTGLatFfRlxLjD3MVgAv1TbjpdSsRT0KHRIuFzVUyT9RHlIWJebcgIochrKi1tWfhnjZKjP91e8FhlQIhXQiwGgGHNyTUILMBnA_adw4VQqL8PyPXrrG514LqAs-HUPswWWcsxU6g1qg58NtsnUWc4ArzPrAPQUMeY27XvayeZrZs7ECTNPl35mv9O1twob0vkw0CEKAZgkgHV3WG53FO0K1EkEt9YsL_1EgNLpP-T7uJ4ol_jvcC2hC0p_XOw5tg0BGflzKMwJCbonEMpV8CuVH7lQrqNIpJ3S/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies.
Re: Does the z architecture have something like the SIMD instructions
Well, PLO is certainly an example. But the relatively recent Transaction instructions greatly expand this. On Fri, 5 Jun 2020 04:56:53 + Ze'ev Atlas <01774d97d104-dmarc-requ...@listserv.uga.edu> wrote: :>I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. :>Ze'ev Atlas -- Binyamin Dissen http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies.
Re: Does the z architecture have something like the SIMD instructions
You may find some of the SHARE presentations useful. I used SIMD z os share as keywords. On 2020-06-05 7:11 a.m., Seymour J Metz wrote: IBM has "Vector" instructions, but the size of a vector is limited to one quadword. Usefull, but not what you normally think of as SIMD. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at www.DKL.com E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Ze'ev Atlas [01774d97d104-dmarc-requ...@listserv.uga.edu] Sent: Friday, June 5, 2020 12:56 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Does the z architecture have something like the SIMD instructions I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. Ze'ev Atlas
Re: Does the z architecture have something like the SIMD instructions
IBM has "Vector" instructions, but the size of a vector is limited to one quadword. Usefull, but not what you normally think of as SIMD. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Ze'ev Atlas [01774d97d104-dmarc-requ...@listserv.uga.edu] Sent: Friday, June 5, 2020 12:56 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Does the z architecture have something like the SIMD instructions I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. Ze'ev Atlas
Re: Does the z architecture have something like the SIMD instructions
Sorta, kinda. IBM calls them Vector instructions, but they're limited to a quadword. The term SIMD normally implies a greater degree of parallelism or streaming. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Keven [k...@k3n.us] Sent: Friday, June 5, 2020 1:42 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the z architecture have something like the SIMD instructions Yes, z/Architecture has a number of SIMD instructions that operate on distinct data types. They are called vector instructions in mainframeze and accordingly have mnemonics that all begin with V. On Thu, Jun 4, 2020 at 11:57 PM -0500, "Ze'ev Atlas" <01774d97d104-dmarc-requ...@listserv.uga.edu> wrote: I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. Ze'ev Atlas
Re: Does the z architecture have something like the SIMD instructions
Yes, z/Architecture has a number of SIMD instructions that operate on distinct data types. They are called vector instructions in mainframeze and accordingly have mnemonics that all begin with V. On Thu, Jun 4, 2020 at 11:57 PM -0500, "Ze'ev Atlas" <01774d97d104-dmarc-requ...@listserv.uga.edu> wrote: I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. Ze'ev Atlas
Does the z architecture have something like the SIMD instructions
I admit being away from the mainframe for long time. Most of my work is on Solaris and Linux servers and therefore I do not code in Assembler. However, I was active in porting a C library into classic z/OS.I was looking to do another port and stumbled upon the fact that that library has several SIMD architecture specific extensions (Altivec, Neon are two examples). While I can ignore that stuff, I became somewhat interested in the subject. Ze'ev Atlas
