Signed-off-by: Rouven Czerwinski
---
arch/arm/boards/raspberry-pi/rpi-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c
b/arch/arm/boards/raspberry-pi/rpi-common.c
index 650b26ce7..840f525bb 100644
---
We don't know if the firmware running on the raspberry pi is the same firmware
which is running on all bcm283x devices.
Therefore move the console clock initialization into the rpi-common.c board
file.
A future commit will use this function to retrieve the miniuart clock from the
raspberry pi
Since we now support the miniuart, enable it as the default stdout port.
With this change the device tree overlay to switch the miniuart to bluetooth is
no longer necessary.
Signed-off-by: Rouven Czerwinski
---
arch/arm/dts/bcm2837-rpi-3.dts | 7 +--
1 file changed, 1 insertion(+), 6
Since we now use the miniuart on the raspberry pi 3, the miniuart overlay is no
longer needed.
Signed-off-by: Rouven Czerwinski
---
Documentation/boards/bcm2835.rst | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/boards/bcm2835.rst b/Documentation/boards/bcm2835.rst
index
The miniuart uses the core clock as the clock source. This clock is fixed by the
firmware to 250Mhz if enable_uart=1 is set in the config.txt file.
However a user could still choose to overclock the core frequency,
which would result in wrong baudrates computed by barebox.
Retrieve the core clock
Since the 16550 driver now supports the RPI3 miniuart, enable it in the default
config.
Signed-off-by: Rouven Czerwinski
---
arch/arm/configs/rpi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index
Add the compatible for the Raspberry Pi AUX UART and an init function which
enables it via the aux register and configures the correct shift value.
Signed-off-by: Rouven Czerwinski
---
drivers/serial/serial_ns16550.c | 25 +
1 file changed, 25 insertions(+)
diff --git
According to the device tree bindings for 8250, width is an optional property.
Default to 1 which is the same default value as used by the kernel.
Before this change the driver would not work for device trees which do not
include the optional binding.
Signed-off-by: Rouven Czerwinski
---
This patch series adds support for the raspberry pi miniuart (also called
aux-uart) to barebox.
With this series the miniuart overlay is no longer necessary to start barebox on
Raspberry Pi 3.
v2:
- Move console clock initialization into board core
- Retrieve the core clock frequency for the
Port of a Linux commit 314fc854f50317931fb4dfaab431695ab886e8de
No functional change. Fix all checkpatch warnings and check errors in
pcie-designware.c
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Bjorn Helgaas
Acked-By: Joao Pinto
Signed-off-by: Andrey Smirnov
---
Port of a Linux commit 51c84709b8c4065fe83b84a487fe7822c2271e77
PCI: imx6: Removed unused struct imx6_pcie.mem_base
Removed the unused struct imx6_pcie.mem_base member. No functional change
intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
Port of a Linux commit b4a8a51caf7de47c2fb03dfb1bbbe442661b5732
Replace of all initial lowercase character in comments and debug messages
to uppercase to maintain coherence.
Fix messages coherence within the DesignWare driver.
Fix code style on dw_pcie_irq_domain_free() function.
Port of a Linux commit a5fcec480f25eb5444c0b71ecdf9b18b09236b95
Freescale has stated [1] that the LVDS clock source of the IMX6 does not
pass the PCI Gen2 clock jitter test, therefore unless an external Gen2
compliant external clock source is present and supplied back to the IMX6
PCIe
Port of a Linux commit 96291d565550c1fd363e488cc17cb3189d2e4cc2
Fix various typos and whitespace errors:
s/Synopsis/Synopsys/
s/Designware/DesignWare/
s/Keystine/Keystone/
s/gpio/GPIO/
s/pcie/PCIe/
s/phy/PHY/
s/confgiruation/configuration/
No functional change
Port of a Linux commit 8cfab3cf63cfe5a53e2e566b3b86b30c187edf3a
Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.
Remove the boilerplate GPL version 2 language, relying on the assertion in
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
On Thu, Dec 13, 2018 at 07:33:56AM +0100, Thorsten K. Scherer wrote:
> fixes 97e81f2
>
> Signed-off-by: Thorsten K. Scherer
> ---
> include/asm-generic/barebox.lds.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/asm-generic/barebox.lds.h
>
Port of a Linux commit 4d1821e729b5d2060ef8c9825af1dacc2182da38
Factor out ref clock enable to make it cleaner to add imx6sx support. No
functional change intended.
Signed-off-by: Bjorn Helgaas
Tested-by: Christoph Fritz
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 43
Port of a Linux commit d91dfe5054d4f2c424bd70ca34fc3328ee179f20
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
Pin registers, but the fixes don't actually work because these registers
are read-only.
Enable write permission before updating the Class Code and
Port of a Linux commit 2a6a85d5368e55e506abd7ca79f08131028bb0bc
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the imx6
driver. No functional change intended.
Signed-off-by: Bjorn Helgaas
Port of a Linux commit 4ab2e7c0df6b8bbc6c8ea1617b737d33c2510012
The dw_pcie_host_ops structures are never modified. Constify these
structures such that these can be write-protected.
Signed-off-by: Jisheng Zhang
Signed-off-by: Bjorn Helgaas
Acked-by: Jingoo Han
Acked-by: Kishon
Port of a Linux commit e44abfed6fcb750d24f4438dc9d5a02eebb5fcac
The read-only DBI registers can be written only when the "Write to RO
Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.
Add accessors to enable and disable write permission, and use them instead
of
On Wed, Dec 12, 2018 at 03:10:51PM +0100, Rouven Czerwinski wrote:
> Add the compatible for the Raspberry Pi AUX UART and an init function which
> enables it via the aux register and configures the correct shift value.
>
> Signed-off-by: Rouven Czerwinski
> ---
> drivers/serial/serial_ns16550.c
Port of a Linux commit e9be4d78618af2e0d5592d9556cf0bba210cfd1a
The ATU CTRL2 register is 32 bits, and bits other than the enable bit may
be set. To check whether the ATU is enabled or not, we should test the
enable bit specifically.
Signed-off-by: Jisheng Zhang
Signed-off-by: Bjorn
Port of a Linux commit 9ab021b6cf8b5bfc40ea9333c9b64b554fe01cd4
Remove unused return values. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff
Port of a Linux commit 4a301766f5263dd94c1b95d1b1bbdf338afb1a37
In several dwc-based drivers, ->host_init() can fail, so make sure to
propagate and handle this to avoid continuing operation of a driver or
hardware in an invalid state.
Signed-off-by: Bjorn Andersson
Signed-off-by:
Port of a Linux commit 6995de2168edc6e58a350e7eb76e02dd191b64f4
Replace a division by 2 operation for a right shift rotation of 1 bit.
Probably any recent and decent compiler does this kind of substitution
in order to improve code performance. Nevertheless it's a coding good
practice
Port of a Linux commit c2deae44616dab0112d965a0dc72d053b5727b4b
The subordinate value indicates the highest bus number which can be
reached downstream though a certain device.
Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
parent")
ensures that downstream
Port of a Linux commit a509d7d9af5ebf86ffbefa98e49761d813fb1d40
Previously dbi accessors can be used to access data of size 4 bytes. But
there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
set/get the number of required MSI interrupts in EP mode) where dbi
accessors
Port of a Linux commit a71280722eeba8f1afa51ad6656028dcb96e110b
This causes CPU hangs when the system is reset by the watchdog, as the GPRs
aren't cleared, but the clocks are back to disabled state.
If the bootloader uses PCIe, it must take care to bring it down into a safe
state, before
Port of a Linux commit 5f334db665173facf2213854408bb5fa2445d0b3
The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
num-lanes is applicable to both root complex mode and endpoint mode. As a
first step, move the parsing of this property outside dw_pcie_host_init().
This
Port of a Linux commit feb85d9b1c47ea8dbcae559ff127b433fdb245b7
Split pcie-designware.c into pcie-designware-host.c that contains the host
specific parts of the driver and pcie-designware.c that contains the parts
used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay
Port of a Linux commit e7d7705ace9494949863848ec77536d5a3287b0a
Only interfaces used from outside the driver, e.g., those called by
the DesignWare core, need to accept pointers to the generic struct
pcie_port. Internal interfaces can accept pointers to the
device-specific struct,
Port of a Linux commit b50b2db266d8a8c303e8d88590c6416dfe576c6c
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
to access dbi address space can access only dbics. However dbics2 has to
be accessed for programming the BAR registers in the case of EP mode. This
is
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index baa07447e..8e7bae258 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -289,20
Port of a Linux commit 916bf1cc6528618197cdaf05ad42a9a82e9dea04
Reorder struct imx6_pcie to put generic fields first. No functional change
intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 2 +-
1 file changed, 1 insertion(+), 1
Port of a Linux commit 8bad7f2fc3006d1752c426343ca77f1fbe61cf00
Pass the struct imx6_pcie pointer, not dbi_base address, to PHY accessors.
This enables future simplifications. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
Port of a Linux commit caf3f562e1161a86bd48a4c4c33af89d3693c658
When a PCI card is not connected, the following messages are seen on mx6:
imx6q-pcie 1ffc000.pcie: phy link never came up
imx6q-pcie 1ffc000.pcie: Link never came up
The first one comes from the pcie-designware.c core
Port of a Linux commit ad8802189426cf7b3a2ad0444f71981fb81312a8
Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
anything specific to access configuration space. It can be just renamed to
dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Bjorn Helgaas
Port of a Linux commit 13957652f7242a8cb02ffb8c96f412f62c486ee1
Use a local "struct device *dev" for brevity and consistency with other
drivers. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 17 ++---
Port of a Linux commit 68a0bfec72cb4f117198ae31df114dad4c5e405d
When we have only two view ports in a DesignWare PCIe platform, iatu0
is used for both CFG and IO accesses. When CFGs are sent to peripherals
(e.g., lspci), iatu0 frequently switches between CFG and IO.
For such scenarios,
Port of a Linux commit 40f67fb2c384fe12741aa35010d62bfe8c98286c
No functional change. Get device pointer at the beginning of
dw_pcie_host_init() instead of getting it all over dw_pcie_host_init().
This is in preparation for splitting struct pcie_port into host and core
structures (once
Port of a Linux commit fe48cb8538421fbd16ecf8bf95829faf8d8c001e
Most of the platforms have 3 or more viewports. For such platforms, We do
not need to share viewports between IO and CFG. Assign viewport 2 to IO
transactions in such cases.
Tested-by: Dong Bo
Signed-off-by: Pratyush
Port of a Linux commit 1034023606d0e971f4dee6f725e441b785a846b5
Rename dw_pcie_valid_config() to dw_pcie_valid_device() and use the result
directly as a boolean value instead of testing against 0. No functional
change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey
Port of a Linux commit c388de1c4f0e5da3e96b49efb0388e2a0d34e079
Move the link wait sleep definitions to the .c file as suggested by
Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaas
CC: Jisheng Zhang
Signed-off-by: Andrey Smirnov
---
Port of a Linux commit d8bbeb39fbf3ff06b6adae9d336f44bee4e3f3ec
Add a loop with timeout to make sure the iATU is really enabled before
subsequent config and I/O accesses.
[bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()]
Signed-off-by: Joao Pinto
Signed-off-by:
Port of Linux commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is
Port of a Linux commit 446fc23fb6f0cab15011d7daae856091856a65cc
dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in
space supplied by the caller. Return the u32 value directly instead.
This makes the calling code read better and makes it obvious that the
caller
Port of a Linux commit 01c076732e8288485c22ef50f20949455a783ca9
The link may be up but still in link training. In this case, we can't
think the link is up and operating correctly. Teach dw_pcie_link_up() to
be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
Also rewrite
Port of a Linux commit 67de2dc34cc30d334cb66ab4f466e80f04d5b618
Drivers based on the DesignWare core can override the config read accessors
by supplying rd_own_conf() and rd_other_conf() function pointers.
dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root
bus) or
Port of a Linux commit a5cb903aef8c642e6f0f6810d46dacedf666b54a
Currently dw_pcie_setup_rc() configures memory base and memory limit in the
type1 configuration header for the root complex. In doing so it uses the
CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
Port of a Linux commit dac29e6c5460d05774e3e8c4fdf4d6e7bd481fab
Add a default DesignWare "link_up" test for use when a sub-driver doesn't
supply its own pcie_host_ops.link_up() method.
[bhelgaas: changelog, split into its own patch]
Signed-off-by: Joao Pinto
Signed-off-by: Bjorn
Port of a Linux commit 116a489d78b30862a2dd04961d3ba98fe4704220
Return values immediately when possible to simplify the control flow.
No functional change intended. Folded in unused variable removal as
pointed out by Fabio Estevam , Arnd Bergmann
, and Thierry Reding .
Signed-off-by:
Port of a Linux commit 17209dfb35a228e597a387bfc83b68093b247f78
Read back the ATU CR2 register to ensure ATU programming is effective
before any subsequent I/O or config space accesses.
Without this, PCI device enumeration is unreliable.
[bhelgaas: changelog, comment]
Signed-off-by:
Port of a Linux commit dd193929d91e1b44b90f81509feeff10c94ddc4d
Some platforms don't support ATU, e.g., pci-keystone.c. These platforms
use their own address translation component rather than ATU, and they
provide the rd_other_conf and wr_other_conf methods to program the
translation
Port of a Linux commit 2d91b491d5be13602a73be789bb8a3c28d06b7f2
Most transactions' type are cfg0 and MEM, so the current iATU usage is not
balanced: iATU0 is hot while iATU1 is rarely used.
Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM.
This allocation idea
Port of a Linux commit c003ca99632e1783466f459033874a0e1e31457b
dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size
requested, but dw_pcie_cfg_read() previously performed a 32-bit read and
masked out the bits requested.
Use the exact access size in dw_pcie_cfg_read(). For
Port of a Linux commit ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e
The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. In IP
v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is
Port of a Linux commit b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058
Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and
dw_pcie_cfg_write(). These checks make sure that accesses are aligned on
their size, e.g., a 4-byte config access is aligned on a 4-byte boundary.
Port of a Linux commit 907fce0902539ecde609e485eb2ecd7119a7a623
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used
if we call dw_pcie_setup_rc() while bringing up the link. If the link has
already been brought up by firmware, we need not call dw_pcie_setup_rc(),
Port of a Linux commit 63503c87f06e0f2c8c951cada81221c5500188d8
Currently, the outbound iATU programming functions are similar: the only
difference is index, type, addr and size. Consolidate these functions into
one. This saves about 1700 bytes in text:
textdata bss dec
Port of a Linux commit 4d107d3b5a686b5834e533a00b73bf7b1cf59df7
imx6_pcie_link_up() previously used usleep_range() to wait for the link to
come up. Since it may be called while holding the config spinlock, the
sleep causes a "BUG: scheduling while atomic" error.
Instead of waiting for
Port of a Linux commit 7e57fd1444bf8f4ba9179f826ed6817c56b801d4
dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc()
programs the Root Complex registers. The Root Complex may lose power
during
Signed-off-by: Andrey Smirnov
---
drivers/pci/pcie-designware.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h
index 8d0330a5a..ba5752ec1 100644
--- a/drivers/pci/pcie-designware.h
+++ b/drivers/pci/pcie-designware.h
@@ -62,8
Port of a Linux commit 4c45852f494dab827291c656ee9e12f3f4ee64d6
Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where". The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two
Everyone:
As a part of working on adding support for PCI on i.MX7D/8MQ, I spent
some time looking through Linux commit history of pci-imx6.c and
pcie-designware*.c and porting various patches to minimize the
differences between the two codebases. This series is the result of
that effort. All of
NULL is used to designate a dummy regulator, so it it should be safe
to use against regulator_enable(). Any value that would retrun true
for IS_ERR(), OTOH, is not. Such value would also pass "if (r)" check
without any problems.
Fix the code to use !IS_ERR() instead.
Signed-off-by: Andrey
Since NULL, is a dummy regulator, we can drop a bit of error checking
logic and simplify the code if we assing host->supply to NULL in case
we can't find an appropriate regulator during probing.
Signed-off-by: Andrey Smirnov
---
drivers/mci/mci-core.c | 19 +--
1 file changed, 9
Since regulator_get() can return an errno via regulator pointer, we
need to make sure we handle that case without passing bogus pointers
around.
Add code to convert mtl017->regulator to a dummy regulator if
regulator_get() fails.
Signed-off-by: Andrey Smirnov
---
drivers/video/mtl017.c | 3 +++
On Tue, Dec 11, 2018 at 02:31:30PM +0300, Antony Pavlov wrote:
> On Fri, 7 Dec 2018 08:09:50 +0100
> Oleksij Rempel wrote:
>
> > Hi Anthony,
> >
> > i would be happy if you can say:
> > - this set is no go, because...
> > or:
> > - right now, I can't test it and if it caused some regression
On Wed, Dec 12, 2018 at 03:01:03PM +0300, Antony Pavlov wrote:
> At the moment globalvar code tries to use nv_device
> even if nv_device is not registered.
>
> How to reproduce the problem:
>
> barebox$ make sandbox_defconfig
> ...
> barebox$ sed -i "s/\(CONFIG_NVVAR\)=y/# \1 is not
E1000_ich8lan, e1000_82573, e1000_82574 and e1000_igb
devices (hw->mac_type) do not use data read from
EEPROM_INIT_CONTROL2_REG in e1000_setup_link(), so there's no reason
for it to bail out when EEPROM read fails. An examlpe use-case would
be a i210 adapter initialized from iNVM with no valid
E1000_read_eeprom() returns a number of different error codes, so
propagate them up the caller chain instead of reducing it to
E1000_READ_EEPROM.
Signed-off-by: Andrey Smirnov
---
drivers/net/e1000/main.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
A number of custom error codes used by e1000 driver will be propagated
all the way up to generic networking code and will end up being fed to
strerror(). As a result of that, some of the current error codes will
result in not very helpful failure messages. For example, trying to
ping a host on a
Hi Roland,
This one doesn't apply. Could you rebase?
Sascha
On Mon, Dec 10, 2018 at 04:55:09PM +0100, Roland Hieber wrote:
> Signed-off-by: Roland Hieber
> ---
> Documentation/boards/imx.rst | 102 +++
> 1 file changed, 57 insertions(+), 45 deletions(-)
>
>
On Mon, Dec 10, 2018 at 03:48:23PM +0100, Lucas Stach wrote:
> From: Andrey Smirnov
>
> Unlike LCD type information, IP address as well as netmaks are not
> stored in an easily usable format in RAVE SP EEPROM. In order to obtain
> them we need to issue a special command to RAVE SP. For that
On Mon, Dec 10, 2018 at 02:38:14PM +0100, Lucas Stach wrote:
> This command allows to reset the network switch on the DEB,
> clearing any DSA configuration, which may still be present from
> a prior boot.
>
> Signed-off-by: Lucas Stach
> ---
Applied, thanks
Sascha
>
On Mon, Dec 10, 2018 at 03:32:39PM +0100, Lucas Stach wrote:
> This was missing, so the default external DI clock source on i.MX51 was
> missing. Also set the divider to a division ratio of 1 initially, to avoid
> complicating the logic in the IPU driver further.
>
> Signed-off-by: Lucas Stach
>
The runtime offset has to be added to the memcpy source address and
substracted from the return address. This should have been changed in
a43e2bbc46 which changed from returning the negative runtime offset
into changing the positive runtime offset. Instead a43e2bbc46 only
changed a zero
fixes 97e81f2
Signed-off-by: Thorsten K. Scherer
---
include/asm-generic/barebox.lds.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/asm-generic/barebox.lds.h
b/include/asm-generic/barebox.lds.h
index 74d3ca4a9..decaab79a 100644
---
On Wed, 2018-12-12 at 15:22 +0100, Lucas Stach wrote:
> Am Mittwoch, den 12.12.2018, 15:10 +0100 schrieb Rouven Czerwinski:
> > Add a clkdev for uart1 which will be used on the Raspberry Pi 3.
> > Double the clockrate since the ns16550 driver used for the uart
> > will divide by
> > 16, while the
Am Mittwoch, den 12.12.2018, 15:10 +0100 schrieb Rouven Czerwinski:
> Add a clkdev for uart1 which will be used on the Raspberry Pi 3.
> Double the clockrate since the ns16550 driver used for the uart will divide by
> 16, while the bcm2835 peripheral manual describes that the bcm2835 miniuart
>
Add a clkdev for uart1 which will be used on the Raspberry Pi 3.
Double the clockrate since the ns16550 driver used for the uart will divide by
16, while the bcm2835 peripheral manual describes that the bcm2835 miniuart will
only divide by 8.
Signed-off-by: Rouven Czerwinski
---
Since the 16550 driver now supports the RPI3 miniuart, enable it in the default
config.
Signed-off-by: Rouven Czerwinski
---
arch/arm/configs/rpi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index
According to the device tree bindings for 8250, width is an optional property.
Default to 1 which is the same default value as used by the kernel.
Before this change the driver would not work for device trees which do not
include the optional binding.
Signed-off-by: Rouven Czerwinski
---
Add the compatible for the Raspberry Pi AUX UART and an init function which
enables it via the aux register and configures the correct shift value.
Signed-off-by: Rouven Czerwinski
---
drivers/serial/serial_ns16550.c | 20
1 file changed, 20 insertions(+)
diff --git
This patch series adds support for the raspberry pi miniuart (also called
aux-uart) to barebox.
With this series the miniuart overlay is no longer necessary to start barebox on
Raspberry Pi 3.
Rouven Czerwinski (6):
mach-bcm2835/core: add clkdev for uart1
serial_ns16550: handle default
Since we now support the miniuart, enable it as the default stdout port.
With this change the device tree overlay to switch the miniuart to bluetooth is
no longer necessary.
Signed-off-by: Rouven Czerwinski
---
arch/arm/dts/bcm2837-rpi-3.dts | 7 +--
1 file changed, 1 insertion(+), 6
At the moment globalvar code tries to use nv_device
even if nv_device is not registered.
How to reproduce the problem:
barebox$ make sandbox_defconfig
...
barebox$ sed -i "s/\(CONFIG_NVVAR\)=y/# \1 is not set/" .config
barebox$ sed -i
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