[PATCH 1/1] added support for zynq7000-fpga-manager

rmwareload tool, because I intended to use it on both, ZynqMP and Zynq7000. I would be happy to get read your feedback. Best Regards Michael Signed-off-by: Michael Graichen --- arch/arm/configs/zynq_defconfig | 2 + arch/arm/mach-zynq/Makefile | 2 +- arc

AW: [PATCH 1/1] added support for zynq7000-fpga-manager

't know how much of CSUs functionality is acctually needed to programm the FPGA. Is the CSU within ZynqMP used for something other than programming the firmware in barebox? Best regard, Michael Von: Michael Tretter Gesendet: Donnerstag, 25. März

AW: [PATCH 1/1] added support for zynq7000-fpga-manager

Mar 2021 12:05:31 +0000, Michael Graichen wrote: > > I think, it would be fine to use only "zynq" instead of zynqmp for the > > firmware loader/fpga manager. (I didn't compare the Zynq7000 and ZynqMP low > > level interfaces for programming the FPGA, yet, but I guess

[PATCH 1/1] Zynq: add support to chainload another barebox

Since OCRAM is only 192K this introduces CONFIG_ZYNQ_BUILD_FSBL so we can can chainload a more feature rich barebox via bootm. >From 1f1a95eca42198d73c38cc12b9b44f061980cef8 Mon Sep 17 00:00:00 2001 From: Michael Graichen Date: Mon, 3 May 2021 12:03:05 +0200 Subject: [PATCH] zynq: add supp

[PATCH 1/1] zedboard: add support for usb

This adds minimalistic support for USB on the Zedboard/Zynq-7000 >From e1e1cdc8e2f82a5c9ecb4acc8eb67181687791d0 Mon Sep 17 00:00:00 2001 From: Michael Graichen Date: Mon, 3 May 2021 16:08:23 +0200 Subject: [PATCH] zedboard: add support for usb Signed-off-by: Michael Graichen --- arch/

AW: [PATCH 1/1] Zynq: add support to chainload another barebox

Hey Lucas, > Seems you imported this patch from somewhere and it left some traces in > the commit message? yes, sorry, my local mirror. I will fix that. > Also I don't understand what this change is supposed to be doing. You > are building just another Barebox binary, with no real differences in

AW: [PATCH 1/1] zedboard: add support for usb

Hey Lucas, [...] > This change does 3 distinct things and should be split in 3 patches to > do one thing at a time: > - add Zynq EHCI support > - add ULPI PHY ID > - add Zedboard USB pinmux no problem, I can split this is separate patches. [...] > Maybe update the defconfig too, if it doesn't b

AW: [PATCH 1/1] Zynq: add support to chainload another barebox

Hey Michael, > This looks familiar. I have a similar patch that sets SDHCI_INT_DATA_AVAIL > only if the command is a READ, but I didn't yet have time to verify, that this > is the correct fix. Can you please send it to me? Thanks, Michael ___ barebox

Re: [PATCH 00/25] EFI improvements

Hey, Am 15.12.21 um 12:07 schrieb Ahmad Fatoum: On 13.12.21 22:08, Sascha Hauer wrote: This series contains several improvements for barebox running on EFI. Most patches are around the efi-stdio driver in which handling of ansi escape sequences is greatly improved. With this series efi-std

Read Barebox Infos from Linux

Hey, I was just wondering if it is possibe to read the Barebox log messages or the Barebox version from within Linux? Best regards Michael ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

AW: Read Barebox Infos from Linux

Hey Ahmed and Sascha, Thanks for your reply. This is all meant to work with devicetree support. Not x86/efi systems? Best regards Michael Von: Ahmad Fatoum Gesendet: Montag, 21. Februar 2022 14:59 An: Michael Graichen; barebox@lists.infradead.org

Barebox for Zedboard

Hey, i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC. I have seen that Barebox has an defconfig for the zynq so i tried export ARCH=arm export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf- export PATH=/opt/OSELAS.Toolchain/arm-cortex

AW: Barebox for Zedboard

Von: Lucas Stach Gesendet: Donnerstag, 19. März 2020 11:53 An: Michael Graichen; barebox@lists.infradead.org Betreff: Re: Barebox for Zedboard Hi Michael, Am Donnerstag, den 19.03.2020, 10:38 + schrieb Michael Graichen: > Hey, > > i

AW: Barebox for Zedboard

Von: Lucas Stach Gesendet: Donnerstag, 19. März 2020 11:53 An: Michael Graichen; barebox@lists.infradead.org Betreff: Re: Barebox for Zedboard Hi Michael, Am Donnerstag, den 19.03.2020, 10:38 + schrieb Michael Graichen: > Hey, > > i

[PATCH] some fixes for the zedboard build

Hey, i've attached some fixes for the zedboard build that worked, at least, for me. The MIO config in lowlevel.c seem to be very "hardware specific" but one can compare this to what Xilinx Vivado says. When including the drivers for Networking, QSPI and SD one will run out of OCRAM very quickl

[PATCH 1/7] Zedboard Arasan MMC driver checks wrong bit

when accessing the SD card arasan_sdhci_send_cmd checks for the wrong bit diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c index b43a4f8dd..0dd9382ae 100644 --- a/drivers/mci/arasan-sdhci.c +++ b/drivers/mci/arasan-sdhci.c @@ -278,7 +278,7 @@ static int arasan_sdhci_send_cmd(s

[PATCH 4/7] Zedboard fix GEM0 MIO Settings

fixed GEM0 MIO Settings according to what Vivado says diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index 912eb11fd..6f05d934c 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -258,7 +258

[PATCH 5/7] Zedboard added FPGA and PCAP clock control

Added the configuration for FPGA an PCAP clock control diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index 6f05d934c..b8001fcf6 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -276,6 +27

[PATCH 6/7] Zedboard turn on LED on startup

Turns on the LED on MIO7 on the Zedboard to have a signal diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index b8001fcf6..eb85df507 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -306,6

[PATCH 7/7] Zedboard added Zynq FPGA manager

This adds support to programm the PL part of the Zynq SoC, but only the non-secure way and no partial reconfiguration. It adds the 'zynq_fpga_manager' so we can use firmwareload -l firmwareload -t zynq-fpga-manager /mnt/mmc0.0/design_1_wrapper.bit to programm the PL. diff --git a/arch/arm/mach-

[PATCH 1/7] Zedboard: Arasan MMC driver

The Arasan driver depends on the SDHCI driver, without it we will see undefined references while linking arasan-sdhci.c:283: undefined reference to `sdhci_set_cmd_xfer_mode' arasan-sdhci.c:299: undefined reference to `sdhci_read_response' arasan-sdhci.c:303: undefined reference to `sdhci_transfer_

[PATCH 3/7] Zedboard fix compiler warning

Fixes a warning while compiling zynq_mkimage.c scripts/zynq_mkimage.c:312:2: warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result] fread returns the number bytes read, if it is not equal to st_size some error has happend diff --git a/scripts/zynq

[PATCH v2 1/7] add-MCI_SDHCI-dependency-to-Arasan-driver

ference to `sdhci_transfer_data' Signed-off-by: Michael Graichen --- drivers/mci/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig index 80b3a2600..9f56bed3a 100644 --- a/drivers/mci/Kconfig +++ b/drivers/mci/Kconfig @@ -141,6 +141,7 @@ config MCI

[PATCH v2 2/7] fixed-false-bit-in-arasan-driver

when accessing the SD card arasan_sdhci_send_cmd checks for the wrong bit Signed-off-by: Michael Graichen --- drivers/mci/arasan-sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c index b43a4f8dd..520bf30ff 100644

[PATCH v2] remove-compiler-warning-in-mkimage

Fixes a warning while compiling zynq_mkimage.c scripts/zynq_mkimage.c:312:2: warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result] fread returns the number bytes read, if it is not equal to st_size some error has happend Signed-off-by: Michael

[PATCH v2 4/7] fixed-gem0-mio-settings

fixed GEM0 MIO Settings according to what Vivado says Signed-off-by: Michael Graichen --- arch/arm/boards/avnet-zedboard/lowlevel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c

[PATCH v2 5/7] added-fpga-clock-control-and-pcap-clock-control

Added the configuration for FPGA an PCAP clock control Signed-off-by: Michael Graichen --- arch/arm/boards/avnet-zedboard/lowlevel.c | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index

[PATCH v2 6/7] turns-on-mio7-led-an-startup

Turns on the LED on MIO7 on the Zedboard to have a signal Signed-off-by: Michael Graichen --- arch/arm/boards/avnet-zedboard/lowlevel.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index

[PATCH v2 7/7] added-zynq-fpga-manager

This adds support to programm the PL part of the Zynq SoC, but only the non-secure way and no partial reconfiguration. It adds the 'zynq_fpga_manager' so we can use firmwareload -l firmwareload -t zynq-fpga-manager /mnt/mmc0.0/design_1_wrapper.bit to programm the PL. Signed-off-b

Re: [PATCH v2 7/7] added-zynq-fpga-manager

Hi Michael, Am 14.04.20 um 12:53 schrieb Michael Tretter: Hi Michael, On Thu, Apr 09, 2020 at 02:44:00PM +, Michael Graichen wrote: This adds support to programm the PL part of the Zynq SoC, but only the non-secure way and no partial reconfiguration. It adds the 'zynq_fpga_manager&#

AW: Barebox for Zedboard

> Von: barebox im Auftrag von Johannes > Roith > Gesendet: Sonntag, 18. Mai 2025 19:06 > An: Ahmad Fatoum > Cc: barebox@lists.infradead.org > Betreff: Re: Barebox for Zedboard > > Hello Ahmad, > > Am Fri, May 16, 2025 at 09:28:03PM +0200 schrieb Ahmad Fatoum: > > Hello Johannes, > > > > On 16.05

[PATCH v2025] added-zynq-fpga-manager

This adds support to programm the PL part of the Zynq-7000 SoC, It adds the 'zynq_fpga_manager' so we can use firmwareload -l firmwareload -t zynq-fpga-manager /mnt/mmc0.0/design_1_wrapper.bit to programm the PL. Signed-off-by: Michael Graichen --- arch/arm/mach-zyn

[PATCH] add zynq-7000 i2c support

This adds support to use the i2c bus on zynq-7000 Signed-off-by: Michael Graichen --- drivers/i2c/busses/Kconfig | 4 ++-- drivers/i2c/busses/i2c-cadence.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index

[PATCH] added zynq 7000 usb support

This adds support to use the USB interface on Zynq-7000 SoC. Signed-off-by: Michael Graichen --- drivers/usb/host/Kconfig | 8 drivers/usb/host/Makefile| 1 + drivers/usb/host/ehci-zynq.c | 36 3 files changed, 45 insertions(+) create

AW: Porting Cora Z7 Board to barebox

> > > > In lowlevel.c I am setting the clock divider for the sdio0 interface to 10 > > and the Source for generated clock is IO PLL. Therefore, the sdio IP > > should get a 100 MHz input clock. IS this correct? Do you know which > > clockrate the driver expects? > > > > Or do you have any other

Re: MMC prepare for zynq

Am 5. Juli 2025 09:01:38 MESZ schrieb Gwenhael Goavec-Merou : >Hi, >Thanks for informations: after deleting everything but the last two lines, >barebox starts has expected. >Now I have and error with SDCard but maybe related to lines removes or >something similar. > Hey, please show me the er