hi jesus,
to follow up on rick and jack's comments:
to use the dual <=1Gsps ADC at 1200 Msps,
then as you point out, you need to use the
ADC in interleave mode:
you need to supply a 600 MHz clock to the ADC board;
and the ADC will then supply a 150 MHz clock
to the FPGA (the ADC clock is divide
Hi Jesús,
If you're using the dac_4x block, which is designed for a DAC running at 4x
the "simulink clock", you're going to have problems if you want to run both
the FPGA and the DAC at 150MHz.
If you really want to do this, I guess you can make a new yellow block (
https://casper.berkeley.edu/wik
Oh, I thought you had said you were using the MKID board. Or at least
the yellow block for the MKID board. Make sure you're not using a
yellow block that does not match the actual hardware you have. The MKID
board is also known as either ADC2X400-14 or ADC2X550-12, depending on
which chips a
Jésus-
I'm guessing that you are using the wrong yellow blocks (the MKID
ADC/DAC design) for a different set of hardware.
Tom
2011/6/28 Jesús García :
>
> Hi Rick,
> I think you are wrong, because with that block I ran a design using a
> sampling rate of 600MHz.
> Moreover my ADC board is:
>
>
Hi Rick,
I think you are wrong, because with that block I ran a design using a
sampling rate of 600MHz.
Moreover my ADC board is:
ADC2x1000-8 (2005 - present | dual 1GSa/sec)
Dual 8-bit, 1000Msps (or single 8-bit 2000Msps), Atmel/e2v AT84AD001B ADC
So 1200 MHz in interleave mode is also possible
That MKID ADC board has a maximum clock rate of 550MHz, so 1200 is not
going to work.
Rick
On 6/28/2011 6:39 AM, Jesús García wrote:
Hi,
I am trying to make a design with an ADC board and a DAC board working
with
different sampling rates, and up to date I have no success.
I am trying to do a
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