On 5/23/2020 6:47 PM, Chris Hanson wrote:
> On May 23, 2020, at 7:54 AM, Jay Jaeger wrote:
>>
>
> I think it depends on whether you want to expose *Ethernet* to the device
> you’re implementing, or just to provide access to it *over* Ethernet.
> Exposing serial and other channels via SPI or
On May 23, 2020, at 7:54 AM, Jay Jaeger wrote:
>
> I don't think a 100K character IBM SMS machine needs DDR. 8D For my
> old student ECE ZAP machine, I just used very simple
> on-development-board RAM, with a layer in between. Probably do the same
> here.
These days, the RAM on a lot of
Thanks to all of those who suggested looking at GHDL. Essentially
instant "analyze" runs. That alone is going to save me hours => days =>
even weeks of time compared to Vivado or even ISE.
I tried one file I had already generated and it worked as is, except for
the need to yank out the
On 5/22/2020 4:45 PM, Chris Hanson wrote:
> On May 21, 2020, at 8:46 AM, Jay Jaeger via cctalk
> wrote:
>>
>> Helpful tips - I agree with avoiding vendor extensions. Thanks.
>
> I’d strongly suggest that the situation with FPGAs & HDLs requires a bit more
> nuance than that. You *should*
On May 21, 2020, at 8:46 AM, Jay Jaeger via cctalk
wrote:
>
> Helpful tips - I agree with avoiding vendor extensions. Thanks.
I’d strongly suggest that the situation with FPGAs & HDLs requires a bit more
nuance than that. You *should* probably avoid or carefully isolate vendor
*language
On 2020-05-21 22:44, Jim Brain via cctalk wrote:
> I must have miscommunicated. I have Xilinx ISE WebPack installed and
> running. I was asking about getting the Lattice toolchain up and
> running, which programming cable to get,
Are you talking Lattice/Diamond on Win10 or linux?
I don't
On 5/21/2020 5:37 PM, Jon Elson wrote:
Windows should be trivial, just read the release notes on what systems
it is compatible with.
I must have miscommunicated. I have Xilinx ISE WebPack installed and
running. I was asking about getting the Lattice toolchain up and
running, which
On 05/21/2020 12:42 PM, Jim Brain via cctalk wrote:
On 5/21/2020 12:24 PM, Eric Smith via cctalk wrote:
On Thu, May 21, 2020 at 10:07 AM Jon Elson via cctalk
wrote:
(I also use Coolrunner II and XC9500XL devices in some
of my
products.)
I used to use XC9500XL series (mostly XC9572XL)
> On May 21, 2020, at 3:56 PM, Jay Jaeger wrote:
>
> On 5/21/2020 11:55 AM, Paul Koning wrote:
>>
>> ...
>> This sort of question is why I found starting with the simulator is helpful.
>> In a simulation you can specify delays directly. So for my 6600, I have
>> the gate delay (5 ns) and
On 5/21/2020 11:55 AM, Paul Koning wrote:
>
>
>> On May 21, 2020, at 12:21 PM, Jay Jaeger wrote:
>>
>> On 5/21/2020 9:51 AM, Paul Koning wrote:
>>>
>> ...
>>> If the timing in your machine is reasonably sane and has enough margin, the
>>> simulation should be painless and synthesis should
I call complete BS on Bunnie Huang's notion that both the way the HDL
module is written and the lack of area optimization is due to some
nefarious intent to sell bigger silicon by Xilinx. I'm really not a fan
of that guy so maybe my glasses are tinted anti-rose. But the design of
large
On 2020-05-21 07:34, Sytse van Slooten via cctalk wrote:
> One of the things I’ve done with my pdp11 vhdl from the start is that I’ve
> not used any vendor specific constructs or language extensions. That’s
> probably the only design decision that I’m still really happy about - it
> allows me
On 5/21/2020 12:24 PM, Eric Smith via cctalk wrote:
On Thu, May 21, 2020 at 10:07 AM Jon Elson via cctalk
wrote:
(I also use Coolrunner II and XC9500XL devices in some of my
products.)
I used to use XC9500XL series (mostly XC9572XL) quite a bit, but I have
switched to Lattice LC4000ZE
On 5/20/2020 8:22 PM, Jay Jaeger via cctech wrote:
As I wrote in my last post, but write here for use as a separate thread:
I'd be interesting in hearing from folks what toolsets they have used
for HDL (VHDL in particular). I started with Xilinx ISE and then
graduated to Vivado for later
On 5/21/20 11:27 AM, Jay Jaeger via cctalk wrote:
> On 5/21/2020 11:22 AM, Jay Jaeger via cctalk wrote:
>> On 5/21/2020 10:00 AM, Tom Uban wrote:
>>> Paul, your project is super interesting. Is there a website where I can
>>> track it?
>>>
>>> --tom
>>>
>> Mainly the github.com/cube1us/IBM1410SMS
I've taken to using parts supported by the open source toolchains & IP,
that mostly limits me to using Lattice parts, but the efficiencies obtained
from not instancing all the extra garbage from a vendor's IP library is
worth it. When you use the vendor tools, they want to waste as many gates
as
On 5/21/20 9:51 AM, Paul Koning via cctalk wrote:
>
>> On May 20, 2020, at 10:22 PM, Jay Jaeger via cctalk
>> wrote:
>>
>> As I wrote in my last post, but write here for use as a separate thread:
>>
>> I'd be interesting in hearing from folks what toolsets they have used
>> for HDL (VHDL in
On 5/20/20 10:22 PM, Jay Jaeger via cctech wrote:
> I'd be interesting in hearing from folks what toolsets they have used
> for HDL (VHDL in particular).
I've been using Verilog rather than VHDL but I started with Quartus for
a little while then moved over to Vivado which I like a little better.
On Thu, May 21, 2020 at 10:07 AM Jon Elson via cctalk
wrote:
> (I also use Coolrunner II and XC9500XL devices in some of my
> products.)
>
I used to use XC9500XL series (mostly XC9572XL) quite a bit, but I have
switched to Lattice LC4000ZE series because they are less expensive and
lower power,
> On May 21, 2020, at 12:21 PM, Jay Jaeger wrote:
>
> On 5/21/2020 9:51 AM, Paul Koning wrote:
>>
> ...
>> If the timing in your machine is reasonably sane and has enough margin, the
>> simulation should be painless and synthesis should produce few issues. If
>> you have bits that are
> On May 21, 2020, at 11:00 AM, Tom Uban wrote:
>
> On 5/21/20 9:51 AM, Paul Koning via cctalk wrote:
>>
>>> ...
>> I have been working, very slowly, on a project analogous to yours: a gate
>> level model of the CDC 6600 supercomputer.
>> ...
> Paul, your project is super interesting. Is
On 5/21/2020 11:22 AM, Jay Jaeger via cctalk wrote:
> On 5/21/2020 10:00 AM, Tom Uban wrote:
>>>
>> Paul, your project is super interesting. Is there a website where I can
>> track it?
>>
>> --tom
>>
>
> Mainly the github.com/cube1us/IBM1410SMS .
>
> I do have a website:
On 5/21/2020 11:07 AM, Jon Elson wrote:
> On 05/20/2020 09:22 PM, Jay Jaeger via cctalk wrote:
>> As I wrote in my last post, but write here for use as a separate thread:
>>
>> I'd be interesting in hearing from folks what toolsets they have used
>> for HDL (VHDL in particular). I started with
On 5/21/2020 10:00 AM, Tom Uban wrote:
>>
> Paul, your project is super interesting. Is there a website where I can track
> it?
>
> --tom
>
Mainly the github.com/cube1us/IBM1410SMS .
I do have a website: www.computercollection.net . I do post there, but
not often.
JRJ
On 5/21/2020 9:51 AM, Paul Koning wrote:
>
>
>> On May 20, 2020, at 10:22 PM, Jay Jaeger via cctalk
>> wrote:
>>
>> As I wrote in my last post, but write here for use as a separate thread:
>>
>> I'd be interesting in hearing from folks what toolsets they have used
>> for HDL (VHDL in
On 05/20/2020 09:22 PM, Jay Jaeger via cctalk wrote:
As I wrote in my last post, but write here for use as a separate thread:
I'd be interesting in hearing from folks what toolsets they have used
for HDL (VHDL in particular). I started with Xilinx ISE and then
graduated to Vivado for later
On 5/21/2020 7:41 AM, Peter Corlett via cctalk wrote:
> On Thu, May 21, 2020 at 01:34:09PM +0200, Sytse van Slooten via cctalk wrote:
> [...]
>> So basically what it comes down to is Quartus or Vivado. I’ve kind of
>> implicitly chosen Quartus, because the Altera based development boards tend
>>
On 5/21/2020 6:45 AM, emanuel stiebler wrote:
> On 2020-05-20 22:22, Jay Jaeger via cctalk wrote:
>> As I wrote in my last post, but write here for use as a separate thread:
>>
>> I'd be interesting in hearing from folks what toolsets they have used
>> for HDL (VHDL in particular). I started with
Helpful tips - I agree with avoiding vendor extensions. Thanks.
I seem to recall some issues regarding edits inside vs. outside Vivado
as well, but it has been more than a year, so the recollection is fuzzy.
JRJ
On 5/21/2020 6:34 AM, Sytse van Slooten wrote:
> If you’re targeting FPGA hardware
> On May 20, 2020, at 10:22 PM, Jay Jaeger via cctalk
> wrote:
>
> As I wrote in my last post, but write here for use as a separate thread:
>
> I'd be interesting in hearing from folks what toolsets they have used
> for HDL (VHDL in particular). I started with Xilinx ISE and then
>
On Thu, May 21, 2020 at 01:34:09PM +0200, Sytse van Slooten via cctalk wrote:
[...]
> So basically what it comes down to is Quartus or Vivado. I’ve kind of
> implicitly chosen Quartus, because the Altera based development boards tend
> to be a lot nicer and cheaper than the Xilinx based stuff. I
On 2020-05-20 22:22, Jay Jaeger via cctalk wrote:
> As I wrote in my last post, but write here for use as a separate thread:
>
> I'd be interesting in hearing from folks what toolsets they have used
> for HDL (VHDL in particular). I started with Xilinx ISE and then
> graduated to Vivado for
If you’re targeting FPGA hardware (opposed to a design for a foundry, or a
design you want to run exclusively in a simulator), it is kind of inevitable
that you work with the toolchains that the hardware vendor supplies. Would be
nice if you could choose freely from competing toolchains, but
As I wrote in my last post, but write here for use as a separate thread:
I'd be interesting in hearing from folks what toolsets they have used
for HDL (VHDL in particular). I started with Xilinx ISE and then
graduated to Vivado for later chipsets - unfortunately, Vivado seems to
be something of
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