Carl-Daniel Hailfinger wrote:
Group each probe function together with the associated IDs in the flash
chip description.
Please add a ticket for this in trac to avoid that the patch is
forgotten.
Carl-Daniel Hailfinger wrote:
All unknown xy SPI chip entries claim to have status UNTESTED for
#127: Add support for hp dl145g3 to coreboot v2
---+
Reporter: samuel.verstra...@… | Owner: somebody
Type: enhancement | Status: new
Priority: major
#128: Improve email user interface for trac
+---
Reporter: stuge | Owner: somebody
Type: enhancement | Status: new
Priority: major |
Author: stepan
Date: 2009-04-22 09:23:00 +0200 (Wed, 22 Apr 2009)
New Revision: 4163
Added:
trunk/util/ectool/
trunk/util/ectool/Makefile
trunk/util/ectool/ec.c
trunk/util/ectool/ec.h
trunk/util/ectool/ectool.c
Log:
A small utility to dump the RAM of a laptop's
On 22.04.2009 1:59 Uhr, Uwe Hermann wrote:
On Wed, Apr 22, 2009 at 12:52:54AM +0200, Stefan Reinauer wrote:
I wrote a small utility to dump the RAM of a laptop's
Embedded/Environmental Controller. Nothing fancy, does not know any
laptops, EC types, or what the values mean. It just dumps
See patch
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* move
See patch
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Factor
Hi,
the attached patch removes the requirement for payload.sh files to be
executable. That help if the file is generated from patches, esp. if
that happens often (eg. with quilt)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Allow non-executable payload.sh scripts. This helps with
On 22.04.2009 10:01, Patrick Georgi wrote:
Hi,
the attached patch removes the requirement for payload.sh files to be
executable. That help if the file is generated from patches, esp. if
that happens often (eg. with quilt)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
On 22.04.2009 09:54, Stefan Reinauer wrote:
Factor out acpi_create_madt_lapics. It can be used on all ACPI boards.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Regards,
Carl-Daniel
--
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Am Mittwoch, den 22.04.2009, 09:53 +0200 schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Author: oxygene
Date: 2009-04-22 10:07:31 +0200 (Wed, 22 Apr 2009)
New Revision: 4164
Modified:
trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c
Log:
Trivial removal of a freudian slip.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi
Am Mittwoch, den 22.04.2009, 09:54 +0200 schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
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Author: oxygene
Date: 2009-04-22 10:10:48 +0200 (Wed, 22 Apr 2009)
New Revision: 4165
Modified:
trunk/coreboot-v2/util/abuild/abuild
Log:
Remove the requirement for payload.sh files to be executable. This
helps if the file is generated from patches, esp. if that happens
often (eg. with quilt)
Author: stepan
Date: 2009-04-22 10:12:05 +0200 (Wed, 22 Apr 2009)
New Revision: 4166
Modified:
trunk/coreboot-v2/util/
Log:
add svn:externals for ectool (trivial)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Property changes on:
Author: stepan
Date: 2009-04-22 10:17:38 +0200 (Wed, 22 Apr 2009)
New Revision: 4167
Modified:
trunk/coreboot-v2/src/arch/i386/boot/acpi.c
trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h
trunk/coreboot-v2/src/boot/hardwaremain.c
Log:
* move i386 / ACPI dependent code out of
Author: stepan
Date: 2009-04-22 10:18:37 +0200 (Wed, 22 Apr 2009)
New Revision: 4168
Modified:
trunk/coreboot-v2/src/arch/i386/boot/acpi.c
trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c
trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c
Log:
Factor out
On 22.04.2009 10:06 Uhr, Patrick Georgi wrote:
Am Mittwoch, den 22.04.2009, 09:53 +0200 schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
r4167
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On 22.04.2009 10:06 Uhr, Carl-Daniel Hailfinger wrote:
On 22.04.2009 09:54, Stefan Reinauer wrote:
Factor out acpi_create_madt_lapics. It can be used on all ACPI boards.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Carl-Daniel Hailfinger
Hello. I want/need to make linuxbios to work with my asus a8js. I'll
explain the why's.
My gforce 7700 fried and needed replacement. So I bought a gforce 9500
from an asus f8sn. The card fits perfectly to the socket and thermal
module. However when bios loads it starts beeping like there is no
See patch.
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Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
This
See patch.
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Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
* Allow
On 22.04.2009 10:38, Stefan Reinauer wrote:
This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a
combined socket_mPGA604. No other sockets come with clock rates, and there is
no difference in code, except for the number of microcode patches included in
a
build.
On 22.04.2009 10:39, Stefan Reinauer wrote:
* Allow coreboot to use the full 256 bytes of CMOS memory
* Make functions out of the accessor macros in mc146818rtc.c
* don't hide reserved cmos entries from coreboot, only from the user.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
This
Author: stepan
Date: 2009-04-22 10:56:50 +0200 (Wed, 22 Apr 2009)
New Revision: 4169
Added:
trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/
trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Config.lb
trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/chip.h
Author: stepan
Date: 2009-04-22 11:03:08 +0200 (Wed, 22 Apr 2009)
New Revision: 4170
Modified:
trunk/coreboot-v2/src/include/boot/coreboot_tables.h
trunk/coreboot-v2/src/pc80/mc146818rtc.c
trunk/coreboot-v2/src/pc80/mc146818rtc_early.c
trunk/coreboot-v2/util/options/build_opt_tbl.c
Author: stepan
Date: 2009-04-22 11:06:38 +0200 (Wed, 22 Apr 2009)
New Revision: 4171
Modified:
trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/chip.h
trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/socket_mPGA604.c
Log:
argh... never redo parts of the original patch on the fly. This fixes the
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4170 to
the coreboot repository. This caused the following
changes:
Change Log:
* Allow coreboot to use the full 256 bytes of CMOS memory
* Make functions out of the accessor macros
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4169 to
the coreboot repository. This caused the following
changes:
Change Log:
This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a
combined socket_mPGA604.
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4171 to
the coreboot repository. This caused the following
changes:
Change Log:
argh... never redo parts of the original patch on the fly. This fixes the tree
again.
Signed-off-by:
Author: stepan
Date: 2009-04-22 14:00:17 +0200 (Wed, 22 Apr 2009)
New Revision: 4172
Modified:
trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c
Log:
remove some style guide breaks and warnings from raminit_f_dqs.c
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by:
Hi,
Status of dl145g3:
* 2 Opteron 2218HE's working in the machine. No problem
* both cpu's got 4GB of ram, NUMA is working :)
* booting with filo works
* converted the patches of Mondrian to the last revision of coreboot.
(original patches are on trac, issue 127)
*
Author: stepan
Date: 2009-04-22 14:14:39 +0200 (Wed, 22 Apr 2009)
New Revision: 4173
Modified:
trunk/coreboot-v2/util/nrv2b/nrv2b.c
Log:
don't ignore return values (trivial)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4172 to
the coreboot repository. This caused the following
changes:
Change Log:
remove some style guide breaks and warnings from raminit_f_dqs.c
Signed-off-by: Stefan Reinauer
Author: uwe
Date: 2009-04-22 14:28:14 +0200 (Wed, 22 Apr 2009)
New Revision: 4174
Modified:
trunk/util/ectool/Makefile
trunk/util/ectool/ec.c
trunk/util/ectool/ec.h
trunk/util/ectool/ectool.c
Log:
Quick 'indent' run on ectool with some additional manual cosmetic fixes.
Signed-off-by:
Hello,
From time to time, flashrom build produces some errors. CC1 or GCC complain
about some missing file.
It comes from the pciutils rules :
steph-laptop:~/Work/Flashrom/flashrom make pciutils
Checking for pciutils and zlib... found.
steph-laptop:~/Work/Flashrom/flashrom make pciutils
Author: stepan
Date: 2009-04-22 14:35:57 +0200 (Wed, 22 Apr 2009)
New Revision: 4175
Modified:
trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout
trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout
trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout
Author: stepan
Date: 2009-04-22 14:38:23 +0200 (Wed, 22 Apr 2009)
New Revision: 4176
Modified:
trunk/coreboot-v2/src/arch/i386/boot/boot.c
Log:
drop unused variable.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
On Wed, Apr 22, 2009 at 01:43:14AM +0200, Carl-Daniel Hailfinger wrote:
All unknown xy SPI chip entries claim to have status UNTESTED for
probe/read/erase/write. That is incorrect.
A bit of confusion comes from how the #defines are named. We call them
TEST_BAD_*, but the message printed by
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
On Behalf Of samuel
Sent: Wednesday, April 22, 2009 6:00 AM
To: coreboot@coreboot.org
Cc: Anton Borisov; Mondrian Nuessle
Subject: Re: [coreboot] [PATCH] First support for HP DL145 G3
On Wed, Apr 22, 2009 at 06:58:02AM -, coreboot wrote:
To avoid that issues are forgotten after a few weeks it makes a lot of
sense to file tickets for them in the tracker.
ACK.
Or, alternatively, send a *ping* email for your patches, which often
helps.
I would _not_, however, store the
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4173 to
the coreboot repository. This caused the following
changes:
Change Log:
don't ignore return values (trivial)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by:
Have you tried SeaBIOS for your payload? It runs the option ROMS directly
instead of emulating them. As an added bonus it will use your original grub
installation.
I have considered this but didn't test it yet as filo also had a patch
to support the dl145g3, and i'm unsure if i need to port
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer uwe checked in revision 4174 to
the coreboot repository. This caused the following
changes:
Change Log:
Quick 'indent' run on ectool with some additional manual cosmetic fixes.
Signed-off-by: Uwe Hermann
Author: hailfinger
Date: 2009-04-22 15:33:43 +0200 (Wed, 22 Apr 2009)
New Revision: 4177
Modified:
trunk/util/flashrom/flashchips.c
Log:
All unknown xy SPI chip entries claim to have status UNTESTED for
probe/read/erase/write. That is incorrect.
A bit of confusion comes from how the #defines
On 22.04.2009 14:41, Uwe Hermann wrote:
On Wed, Apr 22, 2009 at 01:43:14AM +0200, Carl-Daniel Hailfinger wrote:
All unknown xy SPI chip entries claim to have status UNTESTED for
probe/read/erase/write. That is incorrect.
A bit of confusion comes from how the #defines are named. We call
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4175 to
the coreboot repository. This caused the following
changes:
Change Log:
no duplicate names in cmos.layout allowed. (fixes a bunch of boards)
Signed-off-by: Stefan Reinauer
On Wed, Apr 22, 2009 at 6:00 AM, samuel samuel.verstra...@gmail.com wrote:
Hi,
Status of dl145g3:
* 2 Opteron 2218HE's working in the machine. No problem
* both cpu's got 4GB of ram, NUMA is working :)
* booting with filo works
* converted the patches of Mondrian to the last revision of
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer hailfinger checked in revision 4177 to
the coreboot repository. This caused the following
changes:
Change Log:
All unknown xy SPI chip entries claim to have status UNTESTED for
probe/read/erase/write. That is
devfn: 00 (20), offs: 00
device pci 2.2 on end # USB
# when HT_CHAIN_END_UNITID_BASE (0,1)
HT_CHAIN_UNITID_BASE (6),
device pci 4.0 on end # VGA /* REMOVE
THIS ONE */
On Wed, Apr 22, 2009 at 8:00 AM, samuel samuel.verstra...@gmail.com wrote:
2. VGA output is still not working. I have tried both YABEL and
X86BIOS to load the vga rom but i get errors...
X86BIOS: http://merlin.ugent.be/~samuel/dl145g3/vgarom/corebootx86bios.log
relevant part:
On mainboard,
2009/4/21 Cristi Magherusan cristi.magheru...@net.utcluj.ro:
Hello,
I tried to port Ron's fix to v3, and now it seems ifconfig eth0 up
works, the IP address can be manually set, but DHCP fails and ping to
qemu's default gateway fails causing kernel's watchdog timer to expire.
I would not
Author: stepan
Date: 2009-04-22 17:49:28 +0200 (Wed, 22 Apr 2009)
New Revision: 4178
Modified:
trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb
Log:
increase rom sizes for abuild
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Stefan Reinauer wrote:
+++ src/arch/i386/boot/acpi.c (.../trunk/coreboot-v2)
..
+#if 0
+#if MEM_TRAIN_SEQ != 0
+ #error So far it works on AMD and MEM_TRAIN_SEQ == 0
+#endif
+
+#if _RAMBASE 0x1F0
+ #error For ACPI RESUME you need to have _RAMBASE at least 31MB
+ #error
attached
ron
bb.diff
Description: Binary data
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Stefan Reinauer wrote:
+ outb(addr, RTC_BASE_PORT + offs + 0);
Please skip +0, otherwise
Acked-by: Peter Stuge pe...@stuge.se
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Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 4178 to
the coreboot repository. This caused the following
changes:
Change Log:
increase rom sizes for abuild
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan
Stefan Reinauer wrote:
- printed CBFS rom address was always 0
- drop dead code.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Peter Stuge pe...@stuge.se
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Author: stepan
Date: 2009-04-22 18:23:47 +0200 (Wed, 22 Apr 2009)
New Revision: 4179
Modified:
trunk/coreboot-v2/src/arch/i386/boot/acpigen.c
trunk/coreboot-v2/src/arch/i386/boot/tables.c
trunk/coreboot-v2/src/console/console.c
trunk/coreboot-v2/src/pc80/mc146818rtc_early.c
On 22.04.2009 18:00 Uhr, Peter Stuge wrote:
Stefan Reinauer wrote:
+++ src/arch/i386/boot/acpi.c(.../trunk/coreboot-v2)
..
+#if 0
+#if MEM_TRAIN_SEQ != 0
+#error So far it works on AMD and MEM_TRAIN_SEQ == 0
+#endif
+
+#if _RAMBASE 0x1F0
+#error For
Author: stepan
Date: 2009-04-22 18:32:18 +0200 (Wed, 22 Apr 2009)
New Revision: 4180
Modified:
trunk/coreboot-v2/src/devices/pci_rom.c
Log:
- printed CBFS rom address was always 0
- drop dead code.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Peter Stuge pe...@stuge.se
On 22.04.2009 18:30 Uhr, Stefan Reinauer wrote:
On 22.04.2009 18:00 Uhr, Peter Stuge wrote:
+#if MEM_TRAIN_SEQ != 0
+ #error So far it works on AMD and MEM_TRAIN_SEQ == 0
+#endif
+
+#if _RAMBASE 0x1F0
+ #error For ACPI RESUME you need to have _RAMBASE at least 31MB
+ #error
On Wed, Apr 22, 2009 at 9:29 AM, Tom Sylla tsy...@gmail.com wrote:
On Wed, Apr 22, 2009 at 8:00 AM, samuel samuel.verstra...@gmail.com wrote:
2. VGA output is still not working. I have tried both YABEL and
X86BIOS to load the vga rom but i get errors...
X86BIOS:
On Wed, Apr 22, 2009 at 10:59 AM, Myles Watson myle...@gmail.com wrote:
On Wed, Apr 22, 2009 at 9:29 AM, Tom Sylla tsy...@gmail.com wrote:
On Wed, Apr 22, 2009 at 8:00 AM, samuel samuel.verstra...@gmail.com wrote:
2. VGA output is still not working. I have tried both YABEL and
X86BIOS to load
On Wed, Apr 22, 2009 at 10:02 AM, ron minnich rminn...@gmail.com wrote:
attached
ron
Looks good.
Acked-by: Marc Jones marcj...@gmail.com
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On Wed, 2009-04-22 at 08:42 -0700, ron minnich wrote:
2009/4/21 Cristi Magherusan cristi.magheru...@net.utcluj.ro:
Hello,
I tried to port Ron's fix to v3, and now it seems ifconfig eth0 up
works, the IP address can be manually set, but DHCP fails and ping to
qemu's default gateway fails
On Mon, 20 Apr 2009 11:27:38 -0400, Joseph Smith j...@settoplinux.org
wrote:
Hello,
I keep getting unexpected exception errors on my IP1000 with builds over
the past 6 months or so. The unexpected exception errors are random
errors
and are different every time, but seem to happen right
On Wed, Apr 22, 2009 at 2:32 PM, Joseph Smith j...@settoplinux.org wrote:
On Mon, 20 Apr 2009 11:27:38 -0400, Joseph Smith j...@settoplinux.org
wrote:
Hello,
I keep getting unexpected exception errors on my IP1000 with builds over
the past 6 months or so. The unexpected exception
2009/3/31 Mondrian Nuessle nues...@uni-hd.de:
Hi everybody,
I prepared an initial set of patches to support the HP DL145 G3 server, which
is a Broadcom HT-1000/HT-2100 based Socket
F machine.
Thanks for the patches! Could you add a Signed-off-by: line so I can
ack and commit it?
Thanks,
Acked-by: Samuel Verstraete samuel.verstraete at gmail.com
2009/3/31 Mondrian Nuessle nues...@uni-hd.de:
Hi everybody,
I prepared an initial set of patches to support the HP DL145 G3 server, which
is a Broadcom HT-1000/HT-2100 based Socket
F machine.
The current status of the port is:
*
Author: myles
Date: 2009-04-22 22:27:53 +0200 (Wed, 22 Apr 2009)
New Revision: 4182
Added:
trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/
trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Config.lb
trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
Modified:
On Wed, 22 Apr 2009 16:15:38 -0400, Corey Osgood corey.osg...@gmail.com
wrote:
On Wed, Apr 22, 2009 at 2:32 PM, Joseph Smith j...@settoplinux.org
wrote:
On Mon, 20 Apr 2009 11:27:38 -0400, Joseph Smith j...@settoplinux.org
wrote:
Hello,
I keep getting unexpected exception errors on
Author: myles
Date: 2009-04-22 22:30:42 +0200 (Wed, 22 Apr 2009)
New Revision: 4183
Added:
trunk/coreboot-v2/src/superio/serverengines/
trunk/coreboot-v2/src/superio/serverengines/pilot/
trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h
Carl-Daniel Hailfinger wrote:
Convert 12 more boards to use include statements.
abuild tested.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by: Peter Stuge pe...@stuge.se
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Author: myles
Date: 2009-04-22 22:34:05 +0200 (Wed, 22 Apr 2009)
New Revision: 4184
Added:
trunk/coreboot-v2/src/mainboard/hp/
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
On Wed, Apr 22, 2009 at 2:22 PM, samuel samuel.verstra...@gmail.com wrote:
Acked-by: Samuel Verstraete samuel.verstraete at gmail.com
Rev 4182, 4183, 4184.
I didn't commit the patch that disables IDE since it would affect
other boards. It will need to be reworked so that it is
board-specific.
Author: myles
Date: 2009-04-22 22:41:42 +0200 (Wed, 22 Apr 2009)
New Revision: 4185
Modified:
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
Log:
Trivial patch. I forgot to update K8_SET_FIDVID.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson
On Tue, Apr 21, 2009 at 4:41 AM, Joseph Smith j...@settoplinux.org wrote:
This really sounds like an unitialized variable or a bad pointer.
Wouldn't gcc catch these and error when building?
not always. that's what sparse can be useful for.
ron
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On 22.04.2009 22:50 Uhr, ron minnich wrote:
On Tue, Apr 21, 2009 at 4:41 AM, Joseph Smith j...@settoplinux.org wrote:
This really sounds like an unitialized variable or a bad pointer.
Wouldn't gcc catch these and error when building?
not always. that's what sparse
Uwe Hermann wrote:
Sounds reasonable.
Does it really sound reasonable for flashrom to claim that a chip
which can only be matched by a wildcard has a known test status?
//Peter
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ron minnich wrote:
+This new section uses some constructs not yet discussed in detail.
XIP\_ROM\_SIZE just refers to the
+fact that the failover code is eXecute In Place, i.e. not copied to ROM.
not copied to RAM
Of course, the ROM part of normal/fallback is as well, so the usage of XIP
On Wed, 22 Apr 2009 22:54:08 +0200, Stefan Reinauer ste...@coresystems.de
wrote:
On 22.04.2009 22:50 Uhr, ron minnich wrote:
On Tue, Apr 21, 2009 at 4:41 AM, Joseph Smith j...@settoplinux.org
wrote:
This really sounds like an unitialized variable or a bad pointer.
Wouldn't gcc catch
Cristi Magherusan wrote:
in v3 /proc/interrupts shows nothing about eth0
Then you have to look to dmesg output from when the driver is
initialized.
Also, comparing dmesg between v2 and v3 boot would be interesting.
//Peter
pgp6uLed68Xvf.pgp
Description: PGP signature
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On Wed, Apr 22, 2009 at 1:54 PM, Stefan Reinauer ste...@coresystems.de wrote:
If anyone succeeds to get sparse running with coreboot, i'll give it a try,
too. It didn't work all too well when i tried.
I have not been paying attention. this looks better than what I have
seen of sparse.
ron
--
Thanks, I will fix these typos.
ron
On Wed, Apr 22, 2009 at 2:06 PM, Peter Stuge pe...@stuge.se wrote:
ron minnich wrote:
+This new section uses some constructs not yet discussed in detail.
XIP\_ROM\_SIZE just refers to the
+fact that the failover code is eXecute In Place, i.e. not copied
Joseph Smith wrote:
Wow looks like there are alot of bugs in romcc.c !
I only looked at the very first ones:
API Argument with 'nonnull' attribute passed null romcc.c:10780
The thing to note here is that there are conditions to the error.
Code can very well be making sure that those
Joseph Smith wrote:
Here is my GDB dumps they all seem to be related to x86emu but
different every time? Do you see anything useful??
There is debugging support in x86emu. Look for X86EMU_trace_on().
You may also have to enable some debug flag in the x86emu source.
It'll show full trace
ron minnich wrote:
Thanks, I will fix these typos.
Awesome!
Acked-by: Peter Stuge pe...@stuge.se
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Dear coreboot readers!
This is the automatic build system of coreboot.
The developer myles checked in revision 4184 to
the coreboot repository. This caused the following
changes:
Change Log:
This patch adds the target hp/dl145_g3 together with
the appropriate mainboard sources.
Signed-off-by:
Author: hailfinger
Date: 2009-04-23 00:08:00 +0200 (Thu, 23 Apr 2009)
New Revision: 4186
Added:
trunk/coreboot-v2/src/config/nofailovercalculation128.lb
Modified:
trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
On 22.04.2009 22:32, Peter Stuge wrote:
Carl-Daniel Hailfinger wrote:
Convert 12 more boards to use include statements.
abuild tested.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by: Peter Stuge pe...@stuge.se
Thanks, r4186.
Regards,
On Wed, Apr 22, 2009 at 4:08 PM, s...@coreboot.org wrote:
Author: hailfinger
Date: 2009-04-23 00:08:00 +0200 (Thu, 23 Apr 2009)
New Revision: 4186
Added:
trunk/coreboot-v2/src/config/nofailovercalculation128.lb
Modified:
trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
On 21.04.2009 05:37, Myles Watson wrote:
-Original Message-
From: ron minnich [mailto:rminn...@gmail.com]
On Mon, Apr 20, 2009 at 7:50 PM, ron minnich rminn...@gmail.com wrote:
the issue is that include files need an end statement. Long story. My
fault.
that's not
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer myles checked in revision 4185 to
the coreboot repository. This caused the following
changes:
Change Log:
Trivial patch. I forgot to update K8_SET_FIDVID.
Signed-off-by: Myles Watson myle...@gmail.com
Author: myles
Date: 2009-04-23 00:25:45 +0200 (Thu, 23 Apr 2009)
New Revision: 4187
Modified:
trunk/coreboot-v2/src/config/nofailovercalculation.lb
trunk/coreboot-v2/src/config/nofailovercalculation128.lb
trunk/coreboot-v2/util/newconfig/config.g
Log:
This patch fixes the parser. '|'
On Wed, Apr 22, 2009 at 4:13 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
On 21.04.2009 05:37, Myles Watson wrote:
-Original Message-
From: ron minnich [mailto:rminn...@gmail.com]
On Mon, Apr 20, 2009 at 7:50 PM, ron minnich rminn...@gmail.com wrote:
the issue
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer hailfinger checked in revision 4186 to
the coreboot repository. This caused the following
changes:
Change Log:
Convert 12 more boards to use include statements in Config.lb.
Signed-off-by: Carl-Daniel
Author: stepan
Date: 2009-04-23 00:43:02 +0200 (Thu, 23 Apr 2009)
New Revision: 4188
Added:
trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb
Log:
fix compilation of hp dl145
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Added:
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
On Behalf Of s...@coreboot.org
Sent: Wednesday, April 22, 2009 4:43 PM
To: coreboot@coreboot.org
Subject: [coreboot] [v2] r4188 - trunk/coreboot-v2/targets/hp/dl145_g3
Author: stepan
(No need to cc me. Thanks!)
Cristi Magherusan wrote:
dmesg output
Hello,
Thanks, here you have the outputs you requested, and these are the
more interesting parts, IMHO. I'll try to change the v3 IRQ to 5
instead of 11, to see what happens next.
All right! Keep us posted.
dmesg in
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