[coreboot] ASUS KFSN4-DRE Automated Test Failure [master]

The ASUS KFSN4-DRE fails verification for branch master as of commit 31be2c969eed74510c3546bad0dbb9a7334f5843 The following tests failed: VIDEO_FAILURE Commits since last successful test: 31be2c9 soc/intel/common: remove mrc cache assumptions See attached log for details This message was

Re: [coreboot] post_code to text file

cbmem, in util/cbmem/, should be what you are looking for. 2016-12-15 2:35 GMT+01:00 Haleigh Novak : > Hello All, > > I was wondering if it would be possible to add a few lines in the post_code > method so it also writes all the codes to a text file and then keep that > text file

[coreboot] post_code to text file

Hello All, I was wondering if it would be possible to add a few lines in the post_code method so it also writes all the codes to a text file and then keep that text file around so it could be read once the system is running - for debugging purposes because a post_code reader is currently

Re: [coreboot] TALOS project short of funding goals - where to now?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 12/14/2016 02:07 PM, Zoran Stojsavljevic wrote: >> The coreboot project is pretty much dead in the water without it, */ > the only real choices for further development are either /* > */ > super low power crappy ARM devices /* or always going to

Re: [coreboot] TALOS project short of funding goals - where to now?

> The coreboot project is pretty much dead in the water without it, *the only real choices for further development are either* *> super low power crappy ARM devices* or always going to be expensive IBM/TYAN POWER servers, so what do we do? What is wrong with "super low power crappy ARM devices"?

Re: [coreboot] Disassembly of coreboot binaries

Thanks Igor. The RIP isn't mapped in any elf. So probably my load address is problematic. Regards Himanshu On Wed, Dec 14, 2016 at 8:25 PM, Igor Skochinsky via coreboot < coreboot@coreboot.org> wrote: > Hello Himanshu, > > > Wednesday, December 14, 2016, 10:11:57 AM, you wrote: > > > Hi, > > I

Re: [coreboot] Disassembly of coreboot binaries

Hi Aaron, Yes, I am mapping the memory where coreboot.rom is loaded to upper 4GiB. I create a fixed shadow page table entry for reset vector. Coreboot doesn't have a linked address of RIP that I shared. I think with the increase in size of coreboot (from the previous tag I was using) the load

Re: [coreboot] Disassembly of coreboot binaries

Title: Re: [coreboot] Disassembly of coreboot binaries Hello Himanshu, Wednesday, December 14, 2016, 10:11:57 AM, you wrote: Hi, I am working on a hypvervisor and am using coreboot + FILO as guest BIOS. While things were fine a while back, it has stopped working. I see that my hypervisor

Re: [coreboot] Disassembly of coreboot binaries

On Wed, Dec 14, 2016 at 3:11 AM, Chauhan, Himanshu wrote: > Hi, > > I am working on a hypvervisor and am using coreboot + FILO as guest BIOS. > While things were fine a while back, it has stopped working. I see that my > hypervisor can't handle address 0xFC while

Re: [coreboot] coreboot solidpc

Piotr Król wrote: > > > 3/ ./flashrom -p dediprog:voltage=1.8V -w solidrun.rom > > > > Why 1.8V? Is there a schematic available for this board? > > Please take a look at this: > http://www.solid-run.com/wiki/doku.php?id=products:ibx:software:development:bios Cool - thanks! The reason is simply

Re: [coreboot] coreboot solidpc

On Wed, Dec 14, 2016 at 02:05:12PM +, Peter Stuge wrote: > sebastien basset wrote: Hi Peter, > > For flashing board solidpc, > > 1/ plug power supply (without pressing the power button) > > 2/ connect dediprog on j8 connector( with good cable) > > 3/ ./flashrom -p dediprog:voltage=1.8V -w

Re: [coreboot] coreboot solidpc

in http://wiki.solid-run.com/doku.php?id=products:ibx:documents , there is SolidPC Schematics : page 1 : you can read: *""Notice that the programmer must drive 1.8v signals; otherwise* *the main processor might get damaged.""* 2016-12-14 15:05 GMT+01:00 Peter Stuge : >

Re: [coreboot] coreboot solidpc

i have a post-code when call FspMemoryInit of FSP, do you know post-code FSP, how to retrieve post-code generated by FSP intel ? 2016-12-14 14:15 GMT+01:00 sebastien basset : > Hi, > > For flashing board solidpc, > 1/ plug power supply (without pressing the power button) > 2/

Re: [coreboot] coreboot solidpc

sebastien basset wrote: > For flashing board solidpc, > 1/ plug power supply (without pressing the power button) > 2/ connect dediprog on j8 connector( with good cable) > 3/ ./flashrom -p dediprog:voltage=1.8V -w solidrun.rom Why 1.8V? Is there a schematic available for this board? //Peter --

Re: [coreboot] coreboot solidpc

Hi, For flashing board solidpc, 1/ plug power supply (without pressing the power button) 2/ connect dediprog on j8 connector( with good cable) 3/ ./flashrom -p dediprog:voltage=1.8V -w solidrun.rom i'am working on tag 4.5 coreboot. Sébastien Le 14 déc. 2016 12:39, "Piotr Król"

Re: [coreboot] coreboot solidpc

On Wed, Dec 14, 2016 at 10:24:10AM +0100, sebastien basset wrote: > Hello, Hi Sebastien, > > i ve began porting coreboot to solidpc. Have you coreboot working for solidPC, > today ? I would be glad to help you with that. I have SolidPC 1.2. Unfortunately had problem with setting up with

[coreboot] coreboot solidpc

Hello, i ve began porting coreboot to solidpc. Have you coreboot working for solidPC, today ? For now, i am stuck in the init of the ram, in call FspMemoryInit: coreboot-4.5-4-gca220c0-dirty Wed Nov 30 13:43:19 UTC 2016 romstage starting... FSP TempRamInit successful bist: 0x tsc:

[coreboot] Disassembly of coreboot binaries

Hi, I am working on a hypvervisor and am using coreboot + FILO as guest BIOS. While things were fine a while back, it has stopped working. I see that my hypervisor can't handle address 0xFC while coreboot's RIP is at 0xfff81e41. The exact register dump of guest is as follow: [guest0/uart0]