[coreboot] Re: google/sarien (Dell Chromebook): Recovery options

On Tue, May 25, 2021 at 4:40 AM Paul Menzel wrote: > > Dear coreboot folks, > > > In a few days I am going to get my hands on a Dell Latitude 5400 > Chromebook Enterprise (google/sarien) [1][2], and my goal is to install > upstream coreboot on it. > > According to *Developer Information for

[coreboot] Re: ec/google/wilco: Details on EC firmware

On Tue, May 25, 2021 at 4:57 AM Paul Menzel wrote: > Dear coreboot folks, > > > Some Google Chromebooks come with a Google Wilco EC (EC_GOOGLE_WILCO) > instead of Google Chrome EC. coreboot implements the interface for the > Google Wilco EC. > > Unfortunately, I was unable to find more details

[coreboot] Re: Embedding EC firmware

On Fri, Oct 2, 2020 at 8:40 AM Andy Pont wrote: > Duncan wrote... > > You can enable CONFIG_HAVE_EC_BIN and define CONFIG_EC_BIN_PATH ( > https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/southbridge/intel/common/firmware/Kconfig#115) > to point to the EC binary and

[coreboot] Re: Embedding EC firmware

On Fri, Oct 2, 2020 at 3:51 AM Andy Pont wrote: > Hello, > > I have a binary file that is the firmware for the embedded controller on > the laptop platform that I am working on. In the regular BIOS provided > by the hardware vendor this 128KB binary is located at offset 0x40 > in the BIOS

[coreboot] Re: Fixing Hidden PCI devices on Intel common SoCs

On Fri, Sep 27, 2019 at 3:58 PM Aaron Durbin via coreboot wrote: >> > >> > 5. PCI coalesce can alter PCI dev.fn assignments? >> >> That's a serious problem. I noticed that CFL FSP can reassign them >> without being asked to, unpredictably (e.g. if a device fails to show >> up in whatever

Re: [coreboot] What's the relationship between ACPI and SMM?

On Sun, Apr 2, 2017 at 10:43 PM, Iru Cai wrote: > Hello, > > I'm trying to write some ACPI code to support an EC. I don't know if I > need to write an smihandler.c for the boards. > > I saw some mainboard code. Older boards such as lenovo/x200 have no > smihandler.c, but

Re: [coreboot] Skylake ME power down mitigation timer

On Wed, Oct 12, 2016 at 1:48 PM, Trammell Hudson <hud...@trmm.net> wrote: > On Wed, Oct 12, 2016 at 10:08:38AM -0700, Duncan Laurie wrote: > > I wouldn't read too much into the data in there, it turns out the ME > > release that added this output detail (which we shipped in

Re: [coreboot] Skylake ME power down mitigation timer

I wouldn't read too much into the data in there, it turns out the ME release that added this output detail (which we shipped in this device) also got it wrong so the data is not reliable. -duncan On Wed, Oct 12, 2016 at 10:03 AM, Trammell Hudson wrote: > Does anyone have

Re: [coreboot] i2c_writeb vs i2c_raw_write output

On Fri, Oct 7, 2016 at 5:51 PM, Julius Werner wrote: > Also, I think all of these functions only work on non-x86 devices > right now so they're probably not really helpful to you (I'd be > surprised if they even compile and link for your board). The I2C API > is

Re: [coreboot] Servo debug uart in Linux?

On Thu, Oct 6, 2016 at 10:56 AM, Trammell Hudson wrote: > Is it possible to use the Skylake Servo debug UART in Linux or Xen? > It doesn't show up as a normal 16550 (setserial reports "uart type > unknown"), which is making debugging the payload kernel a little > frustrating. >

Re: [coreboot] FYI: ACPI ASL 2.0

So far I've been asking people in ACPI patches to not introduce ASL 2.0 syntax into existing ASL code as it can be confusing if the two are mixed. So we should either convert everything or at least only use ASL 2.0 syntax in new files. The problem with auto-converting sources with the

Re: [coreboot] Question about Intel's documentation notations

Those typically indicate there is a note at the bottom of the table with additional information, corresponding to the superscript number. So you should find a (2) and (3) entry at the bottom of the table explaining that value in more detail. Hopefully. -duncan On Mon, May 9, 2016 at 8:18 AM,

Re: [coreboot] coreboot specific ACPI table

On Tue, Apr 19, 2016 at 6:49 AM, Aaron Durbin wrote: > On Mon, Apr 18, 2016 at 10:17 PM, Julius Werner > wrote: > > I think we should only export the coreboot table location and size > > through ACPI and then read everything else from there. That way we

[coreboot] SPD binaries in coreboot

On Friday, October 23, 2015, Aaron Durbin > wrote: > On Fri, Oct 23, 2015 at 10:33 AM, Peter Stuge wrote: > > Patrick Georgi wrote: > >> we carry the SPD data in coreboot. > > .. > >> Currently, they're

Re: [coreboot] Flashrom won't work with DediProg SF100 fw 6.5.03

. -- Steve G. On Tue, Jun 2, 2015 at 8:48 AM, Duncan Laurie dlau...@chromium.org wrote: On Tue, Jun 2, 2015 at 7:39 AM, Steve Goodrich steve.goodr...@se-eng.com wrote: I have a DediProg SF100 programmer that I want to use with flashrom under Linux. Unfortunately, the SF100 has

Re: [coreboot] Flashrom won't work with DediProg SF100 fw 6.5.03

On Tue, Jun 2, 2015 at 7:39 AM, Steve Goodrich steve.goodr...@se-eng.com wrote: I have a DediProg SF100 programmer that I want to use with flashrom under Linux. Unfortunately, the SF100 has firmware version 6.5.03 and I can't use flashrom with it. I'm looking for a solution. Does anyone

Re: [coreboot] Google Panther: coreboot has to wait for Intel’s ME (Management Engine)

On Mon, Apr 27, 2015 at 12:29 PM, Matt DeVillier matt.devill...@gmail.com wrote: On 4/26/2015 3:03 AM, Paul Menzel wrote: Dear coreboot folks, looking at the time stamps of the Intel Haswell device Google Panther, which Matt DeVillier thankfully uploaded to the board status repository

Re: [coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)

on the previous system power state. I'd be happy for someone else to take a look and tell me I'm misreading though :) cheers, Matt On 3/26/2015 5:21 PM, Matt DeVillier wrote: On 3/26/2015 9:49 AM, Duncan Laurie wrote: On Wed, Mar 25, 2015 at 11:35 PM, Matt DeVillier matt.devill

Re: [coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)

On Wed, Mar 25, 2015 at 11:35 PM, Matt DeVillier matt.devill...@gmail.com wrote: Greetings all! I was wondering if it's possible to have Panther (Asus ChromeBox - Haswell/Lynxpoint) power on when AC power connected regardless of the previous power state. Currently, the box will power on if

Re: [coreboot] questions about google/samus

On Fri, Mar 20, 2015 at 2:04 PM, Andrzej Szeszo asze...@gmail.com wrote: On 13 March 2015 at 00:59, Stefan Reinauer stefan.reina...@coreboot.org wrote: - Is the SSD soldered to the board? Yes. It would be nice to look at motherboard pictures. Does anyone know if there are any online?

Re: [coreboot] XHCI device disconnect on S3 standby

On Tue, May 27, 2014 at 3:17 PM, Matt DeVillier matt.devill...@gmail.com wrote: Greetings, I'm unable to use any USB devices connected to an XHCI controller to resume from S3 standby, as something causes all connected devices to disconnect just prior to entering standby, as per the output

Re: [coreboot] [proposal] EC-mainboard interaction at ASL level

On Tue, Apr 8, 2014 at 2:08 AM, Peter Stuge pe...@stuge.se wrote: mrnuke wrote: Define a set of common ACPI method names which the mainboard code should define, and the EC code can always use. Thanks for starting this! It is exactly what is needed. * MB_TOGGLE_WLAN() or MB_TOGGLE_WIRELESS()

Re: [coreboot] C720 swapparoo

On Wed, Jan 29, 2014 at 10:55 AM, John Lewis jle...@johnlewis.ie wrote: Dear List, If I dd the contents of the RW_LEGACY slot into the WP_RO slot on the stock c720 firmware, will it a) Still work and b) then boot into SeaBIOS by default? :) Unfortunately it is not that simple since SeaBIOS

Re: [coreboot] C720 swapparoo

On Wed, Jan 29, 2014 at 11:30 AM, John Lewis jle...@johnlewis.ie wrote: Forgot to hit reply to all/list, again ... On 29/01/14 19:14, Duncan Laurie wrote: Of course you could also replace the payload with SeaBIOS directly if you are so inclined. This is just a way to enable default legacy

Re: [coreboot] Chromebook coreboot sources

On Tue, Nov 5, 2013 at 10:56 AM, Aaron Durbin adur...@chromium.org wrote: On Tue, Nov 5, 2013 at 12:52 PM, Stefan Reinauer stefan.reina...@coreboot.org wrote: * Aaron Durbin adur...@chromium.org [131105 18:00]: On Tue, Nov 5, 2013 at 10:55 AM, Kyösti Mälkki kyosti.mal...@gmail.com wrote:

Re: [coreboot] Samsung 550 Chromebook own Coreboot

Lumpy should have 2GB of on-board memory and a DIMM slot that comes with a 2GB DIMM. Coreboot seems to detect the on-board memory and finds the SPD binary for it, any chance the DIMM slot is empty? Memory Straps: - memory capacity 2GB - die revision 1 - vendor Samsung CBFS: Looking for

Re: [coreboot] Samsung 550 Chromebook own Coreboot

Unfortunately the input can depend on the systemagent binary. In this case the sandybridge-only binary has a different SMBUS layer and the 7-bit notation is correct. Now the systemagent code comes with its own driver that uses 8-bit notation. -duncan On Mon, Jul 29, 2013 at 8:22 AM, Kyösti

Re: [coreboot] Samsung 550 Chromebook own Coreboot

a brick with the SODIMM removed. John. Duncan Laurie dlau...@chromium.org wrote: Lumpy should have 2GB of on-board memory and a DIMM slot that comes with a 2GB DIMM. Coreboot seems to detect the on-board memory and finds the SPD binary for it, any chance the DIMM slot is empty? Memory

Re: [coreboot] Merges too fast not giving a chance for proper review (was: New patch to review for coreboot: 0ae65d8 Add support for Butterfly Chromebook)

On Mon, Feb 11, 2013 at 2:08 PM, Paul Menzel paulepan...@users.sourceforge.net wrote: Am Montag, den 11.02.2013, 22:51 +0100 schrieb Peter Stuge: Stefan Reinauer wrote: Date: Mon, 11 Feb 2013 21:09:57 +0100 Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set

Re: [coreboot] help finding a quote

On Thu, Sep 6, 2012 at 9:17 PM, ron minnich rminn...@gmail.com wrote: never found it ... I remember seeing something on the gentoo list, is this it? http://archives.gentoo.org/gentoo-dev/msg_aab711c23ab7a209481bf9e870fb7ac8.xml -duncan -- coreboot mailing list: coreboot@coreboot.org