[coreboot] [coreboot - Bug #524] `CONFIG_X2APIC_ONLY=y`or `CONFIG_X2APIC_RUNTIME=y` cause Linux in emulation/qemu-i440fx to crash

Issue #524 has been updated by Felix Held. This isn't really a coreboot bug, since qemu doesn't support x2apic emulation: https://gitlab.com/qemu-project/qemu/-/issues/330 Also the i440fx chipset is much older than the first CPU supporting x2apic mode

[coreboot] Re: QEMU x86 i440fx/piix4 build fails for >= 32MB ROMs - Assertion IS_HOST_SPACE_ADDRESS(host_space_address) failed

Hi Mike, SPI NOR flash chips with more than 16MByte use 4 byte addresses while ones with up to 16MBytes use 3 byte addresses. The SPI flash controllers on older systems often only support the 3 byte address mode. Also typically only up to 16 MBytes worth of SPI flash contents can be mapped

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi Peter, I want to apologize if it seemed that I asked you to hold back on any effort, especially some not directly related to day-to-day tasks, I did not mean anything like that. [...] That said, of course it would be great if more developers try the new submit strategy and see how they feel

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi Martin and Peter, sure, I can let other developers with submit right try out the new submit strategy and not submit anything that's not directly related to what I'm working on right now. I mainly started looking through the submittable patches and submit them when I don't spot anything

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi Peter, By "keep an overview" I mean to know which commits in a pushed branch that have been reviewed and which not. Ah, ok; I'd assume that Gerrit won't allow pushing a series of patches if one patch in there doesn't have +2 and +1 verified yet. Haven't verified this though. I'm all

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi, I reread the documentation and the thing I missed in there is that Gerrit will only automatically rebase a patch when submitting when none of the files it changed have been changed between the parent commit of the to be submitted patch and the current top of tree. At least this explains

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi Peter, I definitely want to submit a patch train patch by patch and not just the last submittable patches including all patches before to make sure that I looked at each individual patch when submitting. Maybe the patch train is too long if it becomes hard to keep an overview? I'd say

[coreboot] Re: ASUS P8ZZ7-V i7-3770 >16GB RAM: SPD CRC failed

Hi Nico, Most notable is that for the failing memory configurations the '[DEBUG] Stored timings CRC16 mismatch.' message is returned, after which `[DEBUG] SPD probe channel0, slot1` is triggered, which seems to fail: `ERROR: SPD CRC failed!!!` Had a quick look at the code that prints this

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi Patrick, When going through the list of submittable patches i ran into a two problems and also got a question: When a patch before other patches gets abandoned, those patches can no longer be submitted. Example: CB:66324 When submitting the first patch of a patch series, somehow the

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi Peter! Hmm, I'm not sure about that? I understand the effective difference with the new strategy to merely be that a later commit in a pushed changeset/branch can't be submitted before an earlier one. That is my understanding of this too. What I wanted to point out in my last email is

[coreboot] Re: Reconsidering the Gerrit submission strategy

Hi, even though I'm not completely convinced that the advantages of this new submit strategy will outweigh the disadvantages for me, I agree that it would be good to try the always rebase strategy for a month and see how well it'll work in practice. Having a commit queue or even running a

[coreboot] Re: POST codes and PCI Post card

Beware though that usually by default the I/O port 0x80 code aren't routed to the PCI bus on any x86 platform that was released in maybe the last maybe 10 years even if it still has PCI slots. The I/O port 0x80 writes often get decoded/routed to the LPC or eSPI bus on the platform which is

[coreboot] Re: [RFC] #pragma once

Hi Martin, To support #pragma once, the compiler tries to identify duplicate encounters with the same file, but the check gcc actually performs to establish the identity of the file is weak. Here's someone who made two copies of the same header with different names, each with a #pragma once,

[coreboot] Re: [RFC] #pragma once

Hi Arthur, I'm very much in favor of using #pragma once instead of the include guards in the coreboot tree, since that removes the possibility of some sorts of bugs and also removes 2 lines of boilerplate per header file. Not sure if romcc supported #pragma once and if that was one of the

[coreboot] Re: Denverton-NS refactoring

Hi Jeff, those merge conflicts are only there for cherry-picking the specific patch without the ones before it directly on top of the current top of tree. When the patches before that one in the patch train are submitted, the merge conflict will disappear, so while this might look like a

[coreboot] Re: link time optimization testing

Hi Peter, So actually no opto-isolation as the advertising claims? I think there was some galvanic isolation between the USB-serial chip and the microcontroller that connects to the rest of the circuitry. Since I took that device apart maybe 2 years ago, I don't remember the details and I

[coreboot] Re: link time optimization testing

Hi Branden, VultureProg was mentioned - even a DIY emulator would be fairly straightforward; that's a nice microcontroller project. That seems a bit overkill, but then again flash chips seem to be more expensive then microcontrollers these days. I don't think I'm up to working on something

[coreboot] Re: Proper way to obtain GbE.bin for Denverton atom

Hi Balaji, Not sure about Denverton, but on Ivy Bridge the GbE partition is just configuration data and since it contains the MAC address, it's specific to one unit and not to one type of board. Regards, Felix ___ coreboot mailing list --

[coreboot] Re: Debugging Windows 10 BSOD

Forgot to add that to find out what the cause is the easiest way is probably having the installed image configured in a way that it'll write full kernel memory dumps to disk and then use !analyze -v in WinDbg on that generated kernel dump. At least that's what I remember from more than 1.5

[coreboot] Re: Debugging Windows 10 BSOD

Hi Raul, The installer behaves differently than the installed Windows OS, so I'd only try on an already installed OS at first. If you need to do some in-depth debugging, I'd also recommend using a checked build that has debug symbols available. Beware that the installed version is very picky

[coreboot] Re: "Fixing" `1 << 31` (technically undefined behavior with known implementation-specific results)

While I find the BIT() macro to be much better than the BITx defines Why? The BITx defines seem to be a rather redundant way of doing things to me. I don't think it was invented by edk2, so edk2 using it shouldn't be held against the format. :) Sure, but that's where I remember seeing

[coreboot] Re: "Fixing" `1 << 31` (technically undefined behavior with known implementation-specific results)

Hi, While I find the BIT() macro to be much better than the BITx defines in edk2, I still prefer the non-macro form and at least in the subtrees I maintain I try to get rid of BIT() usage in new code that gets merged. Since BIT() can only be used for single bits and not for multiple bits and

[coreboot] Re: Why is AGESA blob necessary when AMD Secure Processor initializes DRAM?

Hi Paul, when the PSP releases the x86 cores from reset, the part of AGESA running on the PSP has initialized DRAM and some other parts of the AMD silicon, but for example the initialization of most high speed serial links like PCIe, USB3 and the display interfaces on APUs are done in the

[coreboot] Re: IRQ routing: how to do the mainboard_picr_data/_intr_data structures?

Hi Mike! The PIRQ_MISC registers in the indirect I/O address space with 0xc00 being the index register aren't IRQ numbers; those configuration bits. To get an idea, have a look at the interrupt routing register chapter of for example AMD publication number 45482 [1]. Not sure if that's the

[coreboot] amd_blobs submodule update issue when using git sup alias and how to fix it

Hi! Quick heads-up: In [1] I updated the submodule pointer of amd_blobs so that it now tracks the new official repository [2]. Since the new repository and the old don't have common ancestors, using the git sup alias to update the submodules, that rebases the changes, will fail causing git

[coreboot] Re: Embedding EC firmware

Hi Andy!   Flash Region 1 (BIOS): 0040 - 00ff   Flash Region 8 (EC): 07fff000 - 0fff (unused) Looking at the contents of flash.bin then the EC firmware is located at offset 0x40 which would appear to put it at the start of the IFD BIOS partition. Yep, the EC firmware is

[coreboot] Re: Embedding EC firmware

Hi Andy! Does the EC firmware of your system reside in the IFD EC partition or in the IFD BIOS partition? The former doesn't seem to be the case, since ifdtool complains about nor IFD EC region being present in the IFD. For the latter have a look at 51nb/x210 and mb/amd/mandolin where an FMAP

[coreboot] Re: ASAN-related build error at coreboot master

Hi Mike! https://review.coreboot.org/c/coreboot/+/44656 fixes the bug and is already submitted, so pulling in the changes that have landed today will fix the temporary issue. Regards Felix ___ coreboot mailing list -- coreboot@coreboot.org To

[coreboot] Re: Supporting blobs with licenses that you agree to on download

Hi! I also consider using branches within the same repository to separate different binaries to be a very bad idea. What if you need some blob from one branch and another form another branch for the same board? Also not having a branch checkout out doesn't imply not having downloaded the

[coreboot] Re: Hands-on AMD Zork(Picasso)

Hi! I want to learn Coreboot and AMD Zork architecture. Do you have any suggestion on which board (and its manufacturer product name) to start with. I can see Trembyle, Dolbaz ... for Google Zork (mainboard) but I cannot figure out witch Google Chrome book is paired with a specific baseboard.

[coreboot] Re: beginner's despair ;) coreboot update via internal fails

Hi! I'd say that flashrom only verifying the section it writes by default would be less surprising behavior than the current behavior. Regards Felix ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to

[coreboot] Re: (no subject)

Hi Luke! Is there any texts anyone could recommend to get me started? Not sure what you're looking for exactly, but for general information on the topic [1] might be a good place to start looking. If you're mostly interested about x86 and PCI stuff, have a look at [2] and [3]. Hope that

[coreboot] Re: teensy_debugdev: Can we make this USB EHCI debug jig work?

Hi Keith! Did I miss something? How can we make this work? It won't work, since the ATMega32u4 only supports 1.5 and 12 MBit/s USB, but an EHCI debug dongle needs to support 480 MBit/s mode or it won't work. That's also why the ft(2)232h works as a slightly out-of-spec EHCI debug device

[coreboot] Re: Howdy!

of the socket, that'll fry the memsim2, so build a small adapter that doesn't connect those two pins, but connects the rest. There's also an open source tool to push the firmware image to the emulator; haven't tried the vendor tool. Regards Felix -- Felix Held c/o cyberkombinat23 Steinstraße 23

[coreboot] Re: Howdy!

-- Felix Held c/o cyberkombinat23 Steinstraße 23 76133 Karlsruhe Germany m...@felixheld.de Ust-ID: DE301814366 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: How to access the PCIE device registers at an early stage of coreboot booting?

Hi! This might be worth a look: https://review.coreboot.org/c/coreboot/+/19820/10/src/mainboard/asus/kgpe-d16/romstage.c Regards Felix -- Felix Held c/o cyberkombinat23 Steinstraße 23 76133 Karlsruhe Germany m...@felixheld.de Ust-ID: DE301814366

[coreboot] Re: Trying to check potential compatibility of intel server board

/IVB. C206 should be the same silicon die as the 6 series PCHs (H61, H67, ...) with the only difference being the fuse settings. Regards Felix -- Felix Held c/o cyberkombinat23 Steinstraße 23 76133 Karlsruhe Germany m...@felixheld.de Ust-ID: DE30181

[coreboot] Re: Proposal: Improved ACPI generation

Hi Patrick! for improved runtime ACPI generation I would like to introduce a new member in struct device_operations. It would return the ACPI HID for the given device similar to the ACPI NAME that's already implemented: Sounds good to me. Regards Felix -- Felix Held c/o cyberkombinat23

[coreboot] Re: Kernel Panics on corebooted systems with linux 4.19 ( >4.9)

Hi! Tested it both with microcode and without microcode. It doesent changes the behaviour. Uh, that's indeed not good then. Have you tried if this also happens with older coreboot versions or when running under the vendor firmware? Regards Felix -- Felix Held c/o cyberkombinat23

[coreboot] Re: Suggestion Computer-On-Module implementations

-- Felix Held c/o cyberkombinat23 Steinstraße 23 76133 Karlsruhe Germany m...@felixheld.de Ust-ID: DE301814366 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Kernel Panics on corebooted systems with linux 4.19 ( >4.9)

ly microcode updates and this doesn't depend on just one configuration switch. Regards Felix -- Felix Held c/o cyberkombinat23 Steinstraße 23 76133 Karlsruhe Germany m...@felixheld.de Ust-ID: DE301814366 ___ coreboot mailing list -- coreboot@coreboot.org To unsub

[coreboot] Re: Using WSL to build coreboot

Hi Gregg! This new one is one of those who supports Linux via that WSL function. I've got SuSe SLES12 installed. Has anyone gotten builds to work using something appropriate from the same setup? If need be I'll snag a different WSL set. Building coreboot on Debian-flavored WSL worked for

[coreboot] Re: AMD IMC open source firmware replacement

Hi Mike! I only know one board where the IMC is used for fan control - gizmo2 Could you please clarify the IMC status for ASUS AM1I-A (AMD 16h mini-ITX board) ? Because at coreboot's "menuconfig" I see this dependency I'm pretty sure that the fan control is done by the superio on that

[coreboot] Re: AMD IMC open source firmware replacement

Hi! " To check if IMC is active check if PCI 0:14.3 0x40 bit7 set. " what command do I need to use to check this? sudo setpci -s 14.3 40.b Despite command name, it will print the value. and got 0x04 value. So bit7 is not set --> means IMC is disabled... Please tell, what could be a

Re: [coreboot] Asus KGPE-D16 with latest coreboot errors with Unsupported Hardware on Qubes 4 install missing IOMMU?

Hi! Things should settle down some after Christmas, so I'll see what I can do to pull the old D16 dev platform back out at that time and start testing / merging patches. Are there any others that I should also help take a look at? Arthur pushed a new version of your patch #19820 and since

Re: [coreboot] Asus KGPE-D16 with latest coreboot errors with Unsupported Hardware on Qubes 4 install missing IOMMU?

Hi! No idea why combined mode is the default, it's only useful for OSes from the '90s. It's not about the type of drives (SATA vs PATA) connected but how the SATA controller identifies itself to the OS. I agree that the combined mode isn't the best default, but I can't say that it's

Re: [coreboot] Supported Motherboards

Hi! Seems that I forgot to send this e-mail, so here's a rather late response: By removing open-source AGESA and all boards that use them, you would remove many boards that can boot blobless (like KGPE-D16 and KCMA-D8, there's also cheap low-end like E350M1, although I'm not sure this uses

Re: [coreboot] Proposing a change to Coding Style

Hi! I hereby propose that going forward, we should always wrap conditional blocks in braces, even one-liners. I'd also like to have this change, since it might prevent bugs and doesn't add too much verbosity. Related question: Should the else line in if else statements look like this: }

Re: [coreboot] Server systems shipped with coreboot

Hi Carl-Daniel! At 34C3 I was told by someone that a major vendor has been shipping servers with coreboot without announcing this, and I unfortunately neither remember the server model nor who told me about this. This might be related:

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

And so far, nobody was able to crack Huffman, thus to have ability to reverse-engineer plain kernel executable. Not true. See http://blog.ptsecurity.com/2017/12/huffman-tables-intel-me.html , https://github.com/ptresearch/unME11 and https://github.com/IllegalArgument/Huffman11 Regards

Re: [coreboot] how to implement variable read/write variable in coreboot

Hi Nico! I'm not sure how to use a per erase-block counter? When would it update? we could only do that on every erase. A per variable counter might be useful, but I still hope it will work without. I was thinking of putting a number in the first word of a block. Every time a new block is

Re: [coreboot] how to implement variable read/write variable in coreboot

Hi Nico! The question I have here is what to do if there is more than one valid entry. Just using the first one introduces a bit of undetermined behavior (block order in the flash might be different after defragmentation). No, always choosing the first would be determined behavior. In case we

Re: [coreboot] how to implement variable read/write variable in coreboot

Hi! Write strategy: Invalidate any entry with matching key, append after last entry if there is enough space in the current erase block. If not, finalize current erase block with an invalid entry spanning the free space of the block, write variable into next erase block. If we run out of erase

Re: [coreboot] Intel NIC security

Hi Taiidan! Is it worth figuring out how to externally re-flash grey market "intel" nics - or is the onboard NVM flash unable to do anything too terrible? In the newer (the 3 digit i/x series like i350, x540 etc) nics intel has added a "security" flash write protect feature so I imagine

Re: [coreboot] Power supply and X220

Hi! You should only power your BBB with an external 5V power supplier, > and connect its usb peripheral port to your controlling computer. > I have never used any ATX power supplier for this, just the > configuration I just described is enough. For a x220 the 3,3V regulator on the BBB likely

Re: [coreboot] coreboot community meeting minutes for February 16, 2017

Hi! * coreboot is evaluating the idea switching from the mailing list to a forum package. A poll on this will be posted shortly. - Switch to reddit? - Switch to google groups? - Look for a forum software package that integrates well with the mailing list. - Skepticism was expressed

Re: [coreboot] PECI temperature in lm-sensors

Hi! 2) I don't have secret PECI docs either, so I don't know what else should I do... Maybe the three peci.c files in 3rdparty/chromeec can help you. At least those contain the meaning of some of the magic values. 3) You're right, I want to configure SuperIO to control fans on motherboard

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

Hi! I don't know if Charlotte has added the ID of the dGPU to src/drivers/lenovo/hybrid_graphics.c. Does the dGPU consume power after hybrid_graphics.c disable the dGPU? OPTIMUS_ENABLE is a PCH GPIO and controls the muxes that select if the internal display is connected to the iGPU or the

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

Hi! BIOS: 11W Coreboot: 19W [...] Can you also measure the power consumption with the GPU enabled under the vendor firmware? and no, the NVidia GPU was not enabled in corebooy. Both results were on integrated GPU only Have you only disabled the nVidia GPU in devicetree.cb (that will only

Re: [coreboot] Good source for SOIC clips

There are a number of chinese websites offering cheap SOIC clips, the most widely known is probably Alibaba/Aliexpress: http://www.aliexpress.com/wholesale?catId=0_id==SOIC+clip These are certainly much cheaper than the expensive ones available in the "west" - though I don't know if the

Re: [coreboot] G505s status (and test report)

Hi Florentin! As for adding support for Bolton and refactoring and unifying the FCH code, I would like to pick up the task, because I want to invest myself in coreboot dev again and I hope that I will have some time to spend in the near future... Great! IIRC someone in the IRC channel was

Re: [coreboot] G505s status (and test report)

Hi Florentin! -3) The USB3 does NOT work : the 3rdparty xhci blob (${COREBOOT}/3rdparty/blobs/southbridge/amd/hudson/xhci.bin) is not correct!.. PLEASE HELP : can someone give me a tip or advice, how to extract this blob (from uefi image or/sys/)? You have to use the Bolton USB3 blob if you

Re: [coreboot] Adding Coreboot support to the F2A85-M PRO mainboard

but apparently missing early serial support The early serial support was factored out into the src/superio/nuvoton/common directory. So there is support for that. Regards Felix -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] Putting HDA verbs in CBFS

would it work to name the verb tables by the vendor,device standard we use for vga bios and then be able to pick the right one? Those HDA verb tables are not only codec dependent, but also board dependent. In the tables is e.g. the configuration for the different analog ports, which very likely

Re: [coreboot] [GSoC-2015] Interested in Participating - Discussing Ideas

Hi Varad! I dumped the BIOS binary for a Radeon GPU and am trying to make sense of it using the atombios kernel header [1] - are there any resources on ATOMBIOS internals I can use? I believe the GPU initialization can be done by tracing the dump contents as suggested in this thread [2], but

Re: [coreboot] programming a 2764

Hi Ron! 1. Get a pin-compatible replacement for a 2764 A AT28C64B might be a replacement, but you still need a special programmer; not a simple SPI one. 2.get a USB to parallel port adapter Probably won't work; those things only work with printers and do not support direct access to the

Re: [coreboot] Naming for identical chips with different model numbers due to different package variants

Hi! some vendor will come up with a way to break a naming scheme. That why I choose NCT6776D and not NCT6776 as name. NCT6776D and NCT6776F have a common datasheet and the only difference I could spot was the package. But the manufacturer might release a chip with a different suffix and

Re: [coreboot] Naming for identical chips with different model numbers due to different package variants

Hi Peter! The code you are writing is communicating with a piece of hardware that is expected to behave a certain way. Which package the hardware comes in is utterly irrelevant for the behavior of the hardware in this case, so please do not garble the name with that noise. Then I should rename

Re: [coreboot] Naming for identical chips with different model numbers due to different package variants

Personally, I'd just use a little 'x' in place of D or F in this case. What if a chip has X as suffix? At least that was my thought not to choose that. And that also might it can confuse people, since there is no NCT6776X. I think I'll just remove the suffix from this bikeshed and add a

Re: [coreboot] AMD A76M chipset?

Hi Rudolf! Is here someone who wants to work on this perhaps together with me? (of course donations welcome ;) I will buy some / work on that only if someone else buys it too. I've started porting coreboot to the ASROCK FM2A88M-HD+ (A88X chipset) and have nearly finished the code for the SIO

Re: [coreboot] AMD A76M chipset?

Hi Rudolf! Is here someone who wants to work on this perhaps together with me? (of course donations welcome ;) I will buy some / work on that only if someone else buys it too. I've started porting coreboot to the ASROCK FM2A88M-HD+ (A88X chipset) and have nearly finished the code for the SIO

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

Hi Scott! The NIC bus number is hard-coded at the moment. This needs fixing if the NIC bus number can change. The bus number of the NIC changed from 03:00.0 to 04:00.0 when I plugged a PCIe card into the board. Tried that maybe two weeks ago. Regards Felix -- coreboot mailing list:

Re: [coreboot] ASRock E350M1 start automatically after a electric cut

Have a look at the power loss control bits inside the superio chip. They specify what to do when the mainboard gets its standby power. Okay, but how please? Haven't read enough of the coreboot source code to be able to say if and where those bits are written by coreboot. They are in the LDN A

Re: [coreboot] ASRock E350M1 start automatically after a electric cut

Hi! My E350M1 start automatically after a electric cut. I tested this in the hope but I get the same result: http://review.coreboot.org/#/c/5397/ That (hopefully) fixes a completely different problem. Does watchdog is used by default? That doesn't sound like the watchdog. Do you have an

[coreboot] coreboot port for the ASRock FM2A88M-HD+

Hi! I am trying to port the ASRock FM2A88M-HD+ board. Should be a good board for my first coreboot port, since the reference code for the chipset and the datasheet for the superio chip are available. And it's quite inexpensive. I gathered some information and created a wiki page for it: