Hi,
You should probably try an older version of coreboot, close to when the
harcuvar board was introduced and check if that version outputs anything
on UART.
I did that on a custom board using denverton recently and already
proposed a few fix, but I don't have an harcuvar board to test.
Hope
On Fri, Nov 08, 2019 at 12:45:39AM +0100, Nico Huber wrote:
> On 07.11.19 12:05, Nico Huber wrote:
> > 1. Few people seem to take the might of Git into account. We have a
> >tool that can significantly increase the efficiency of development
> >and can help to preempt bugs. But many people
On Thu, Mar 28, 2019 at 06:55:50AM +0800, Rafael Send wrote:
> Hi,
> If I theoretically had a flash chip that was larger than 128Mb, it requires
> 3-4 byte addressing.
>
> Does / could coreboot support such large memory, or would the limitation
> live somewhere else in the system?
My guess is it
uconfig. How can that be done?
>
Hello,
You are reading it wrong:
It depends on CONSOLE_OVERRIDE_LOGLEVEL been =n, because of the « ! »
And it is =n (according to the « [=n] » text.
So go to menu « Console » and set « Default console log level » to 8:SPEW
That’s for the coreboot part
since the first denverton commit…
So please test and submit a patch ;)
Best Regads
Julien
>
> Thanks,
> Sumo
>
>
>
>
>
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Julien Viard de Galbert - jviardd
xceed the limit but the script complains…
Just saying that the script should be updated if the policy is changed.
Best Regards
--
Julien Viard de Galbert - jviarddegalb...@online.net
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up, do it in your own time. ;)
>
> Thanks,
> Sumo
>
> 2018-03-27 6:54 GMT-03:00 Julien Viard de Galbert <jviarddegalb...@online.net
> <mailto:jviarddegalb...@online.net>>:
>
>
>> Le 26 mars 2018 à 21:24, Sumo <kingsu...@gmail.com
>> <mailto:kingsu
g the ACPI implementation to
Gerrit sooner.
Best Regards,
Julien
> Thanks,
> Sumo
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Julien Viard de Galbert - jviarddegalb...@online.net
Online / Scaleway
Looking for an
t; provided by you; meaning you have to extract the BIOS from the flash,
> extract the ME-binary using coreboot/utils, clean it with ME-cleaner
> (optional) and then build coreboot with your blob.
>
> The toolchain takes care automatically about the correct placement of
> the ME in the
> Le 8 févr. 2018 à 17:24, Aaron Durbin <adur...@google.com> a écrit :
>
> On Thu, Feb 8, 2018 at 7:20 AM, Julien Viard de Galbert
> <jviarddegalb...@online.net> wrote:
>> Hello all,
>>
>> First sorry for mailing direclty those of you who are o
recommendations?
Best Regards
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Julien Viard de Galbert - jviarddegalb...@online.net
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at FOSDEM for more details ;-)
Best Regards,
Julien
>
> Regards
> Felix
>
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Julien Viard de Galbert - jviarddegalb...@online.net
Online / Scaleway
Looking for a
Hello coreboot developers and Denverton Maintainers,
As the Denverton support has been integrated, I tried to port our changes over
it and see what can be contributed...
The first thing I noticed was that there is a hard dependency from the chip
to the harcuvar board which looked really wrong and
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