Hello, all. My girlfriend Maria (CC'ed) would like to organize some
goodies for coreboot meeting. Already available are black T-shirts:
2 x M, 8 x L, 1 x XL according to my notes, it's no guarantee, I can't
double-check now as I'm travelling.
Expected price is under €20 for any of items.
Capacity
Good news: now it's possible to have them in black as well.
I received up to now only one request to which I replied by personal
mail. If you didn't receive any reply, please resend your request.
Please specify in request the size, color (white, black, few other
colors if someone is interested),
On 31.05.2015 19:27, Matthias Apitz wrote:
El día Sunday, May 31, 2015 a las 06:45:48PM +0200, Vladimir
'φ-coder/phcoder' Serbinenko escribió:
Good news: now it's possible to have them in black as well.
I received up to now only one request to which I replied by personal
mail. If you
On 21.05.2015 16:19, Michael Gerlach wrote:
Okay here we go...
I memtested the modules again and as expected no defect was found. So i
retried latest master today and quite unusually it just boots up.
Quite possibly you were just missing microcode update.
It does not reach payload-state
On 08.12.2014 01:00, Charles Devereaux wrote:
Sorry, but if it is like the X60 it can not be made the work.
Just like in the WWAN slot, but in reverse, the USB lines are not wired
on the WLAN slot.
IIRC this is not the case on the X201 (a very nice machine, but coreboot
support may not be
On 03.12.2014 23:32, Charles Devereaux wrote:
Hello
As explained before, thinkpad-acpi can't control the non-wifi radio like
bluetooth or wwan, because it expects some ACPI entries that aren't
there - so there is no rfkill control for these, even if some
non-working entries are shown with
To emulate rfkill functionality, just write directly to the ec, for ex
to turn on wwan and wifi:
./ec_access -w 0x3a -v 0x60
Usecase?
Example: I have a wwan card, but I mostly use it for GPS. I can save
some power by turning it off without rebooting, while
On 22.11.2014 12:22, John Lewis wrote:
On 21/11/14 21:58, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
On 14.11.2014 12:44, John Lewis wrote:
Hey y'all,
I've modified the board-status script to have as few external
dependencies as possible, be a self-extracting, self-running binary
On 22.11.2014 17:28, John Lewis wrote:
On 22/11/14 15:55, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
On 22.11.2014 12:22, John Lewis wrote:
On 21/11/14 21:58, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
On 14.11.2014 12:44, John Lewis wrote:
Hey y'all,
I've modified the board
Hello, all. I know I've signed up to fix board-status and cmos but I
don't want to go through painful reviews, so I'm not going to do this,
even though maintaining current CMOS stuff is a pain in itself.
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On 14.11.2014 12:44, John Lewis wrote:
Hey y'all,
I've modified the board-status script to have as few external
dependencies as possible, be a self-extracting, self-running binary.
and removed the time-stamp to keep the number initial commits down. Feel
free to tell me how bad it is and how
On 12.10.2014 08:03, Vipin Gahlaut wrote:
Hi,
I have cloned latest coreboot and trying to build with grub2 as payload.
in make menuconfig I select grub2 instead of seabios. when I fire make
command it checkout latest grub and that fails to build. for 2 reasons.
1. Due to some
Hello, all. I've updated
http://www.coreboot.org/PragueMeetingHardware#phcoder . If somebody
wants me to bring sth, please add a paragraph there, otherwise, I won't
take almost anything.
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to increase the ROM size?
-Original Message-
From: Vladimir 'φ-coder/phcoder' Serbinenko [mailto:phco...@gmail.com
mailto:phco...@gmail.com]
Sent: Sunday, October 12, 2014 3:02 PM
To: Vipin Gahlaut; coreboot
Subject: Re: [coreboot] unable to build coreboot with grub
On 12.10.2014 08:03
On 12.10.2014 12:44, Vipin Gahlaut wrote:
I tried changing under main mainboard - rom chip size but does not seem
to be helping. If I look at .config I suspect that the reason is
CONFIG_BOARD_ROMSIZE_KB_256=y which doesn't change even if I change ROM
size in main board.
, Oct 12, 2014 at 4:21 PM, Vladimir 'φ-coder/phcoder' Serbinenko
phco...@gmail.com mailto:phco...@gmail.com wrote:
On 12.10.2014 12:44, Vipin Gahlaut wrote:
I tried changing under main mainboard - rom chip size but does not seem
to be helping. If I look at .config I suspect
is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
CONFIG_COREBOOT_ROMSIZE_KB=512
CONFIG_ROM_SIZE=0x8
On Sun, Oct 12, 2014 at 4:21 PM, Vladimir 'φ-coder/phcoder' Serbinenko
phco...@gmail.com mailto:phco
Success. Addresses are slightly different and new XSDT table but both
are ok and expected.
On 11.10.2014 00:16, Paul Menzel wrote:
Dear Vladimir,
Am Mittwoch, den 08.10.2014, 21:29 +0200 schrieb Vladimir Serbinenko:
Vladimir Serbinenko (phco...@gmail.com) just uploaded a new patch set to
On 11.10.2014 03:03, ron minnich wrote:
Android defaults sometimes surprise me.
When we've had this kind of issue in the past a disassembly diff of
good vs bad has sometimes led to diagnosis. I think you have a rough
idea what's broken so start there. Painful but necessary.
.car.data is
On 11.10.2014 03:20, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
On 11.10.2014 03:03, ron minnich wrote:
Android defaults sometimes surprise me.
When we've had this kind of issue in the past a disassembly diff of
good vs bad has sometimes led to diagnosis. I think you have a rough
idea
On 21.09.2014 04:12, ron minnich wrote:
Here's the problem. There is caching of the DRAM configuration going
on. So, a restart is not stateless.
I would be happier if you could guarantee that the mrc cache is
disabled, or never used, each time you change the dram setup (move
DIMMs,
On 09.09.2014 20:52, Luigi Bai wrote:
Per the wiki, I am offering this information to try to determine the
status of coreboot support, especially for Intel/PM965 or Intel/82801H.
I didn't see either under the lists of supported hardware
Unsupported, chipset unsupported. There is a very
I'm not a fan of Coreboot having invented its own nonstandard hacks, but
I guess it is pretty much unavoidable.
It's completely avoidable. The stub can copy this information to
standard framebuffer info structure. The only missing thing is to apply
patch by cjwatson or mjg59 (I'm not sure now
On 06.09.2014 00:18, ron minnich wrote:
Vladimir can you point me to that patch? This sounds interesting.
https://lkml.org/lkml/2010/8/25/190
ron
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On 06.09.2014 00:19, ron minnich wrote:
I don't think it's random at all. Vladimir can confirm, but if he is
caching the RAM parameters, then this 'solution' will work for you
until the next time you reflash coreboot, or change your dram type, at
which point it will stop working.
Nehalem
On 06.09.2014 00:31, H. Peter Anvin wrote:
On 09/05/2014 02:23 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
On 06.09.2014 00:18, ron minnich wrote:
Vladimir can you point me to that patch? This sounds
interesting.
https://lkml.org/lkml/2010/8/25/190
I believe *most* of this patch has
This code assumes that payload didn't change video mode which is
improper assumption if you're not a payload.
On 04.09.2014 12:25, Gerd Hoffmann wrote:
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
arch/x86/Kconfig | 12 +++
arch/x86/kernel/Makefile | 1 +
Charles
On Mon, Aug 25, 2014 at 5:02 PM, Vladimir 'φ-coder/phcoder'
Serbinenko phco...@gmail.com mailto:phco...@gmail.com wrote:
On 25.08.2014 22 tel:25.08.2014%2022:53, Vladimir
'φ-coder/phcoder' Serbinenko wrote:
Ideally, the DSDT should be fixed
On 01.09.2014 22:19, Charles Devereaux wrote:
Hello
I'm interested in WWAN support, mostly for the GPS features and the cool
things you can do with them (like a stratum ntp server).
Most GPS receivers don't have enough precision for any timing.
I was told a EM770W doesn't even need a
On 26.08.2014 08:50, Paul Menzel wrote:
Dear Charles, dear David,
Am Montag, den 25.08.2014, 11:21 -0600 schrieb David Hubbard:
I'm focusing in on this error message first:
ACPI Warning: For \_SB_.PCI0.LPCB.EC__.LED_: Excess arguments - needs 1,
found 2
Can you take a look at the
On 26.08.2014 17:53, Charles Devereaux wrote:
My understanding is that the OS does the call that correctly, but that
coreboot ASL tables only expect one argument.
Please provide a refrence when doing such bold claims. LED method is not
specified in ACPI, so assuming that it takes any particular
On 25.08.2014 04:39, Charles Devereaux wrote:
Hello
Previously
(http://www.coreboot.org/pipermail/coreboot/2014-July/078320.html) I
mentioned that 3 bugs seemed to be related to the DSDT:
- missing ACPI events when the stylus is inserted/removed
How is the OS supposed to react to them?
-
Ideally, the DSDT should be fixed within coreboot, but this goes beyond
my present abilities.
Not true. Just do the same changes to the corresponding *.asl files in
coreboot repo and send the patch to gerrit. Other than a layer of
preprocessing, it's exactly the same code as you got from
On 25.08.2014 22:53, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
Ideally, the DSDT should be fixed within coreboot, but this goes beyond
my present abilities.
Not true. Just do the same changes to the corresponding *.asl files in
coreboot repo and send the patch to gerrit. Other than a layer
On 25.08.2014 23:28, ron minnich wrote:
A friend asks me how to disable the usb stack in his bios. I have no
clue, anyone?
Doesn't sound like end goal. But I'd go through setup menu to see if
something fits his *end* goal (disabling usb stack sounds like means to
goal, not the goal itself).
On 10.08.2014 21:06, John de la Garza wrote:
I understand that the calling functions in 32 bit C uses the stack and
this is why coreboot needs to use cache as RAM. Doesn't 64 bit C use
registers to pass arguments to functions? If this is the case why not
run in 64 bit mode?
Also, even if
On 06.08.2014 00:08, Peter Stuge wrote:
Simon Andrä wrote:
I want use coreboot but i dont know if my system is supportet:
I have an Acer Predator G3620
It isn't.
I hope someone can help me
As always with open source you have to help yourself.
Or hire someone to do it.
//Peter
On 19.07.2014 07:42, Charles Devereaux wrote:
Hello,
On Wed, Jul 9, 2014 at 2:15 AM, Denis 'GNUtoo' Carikli
gnu...@no-log.org mailto:gnu...@no-log.org wrote:
My pomona clip had issues with its contact pins(the ones in contact
with the flash chip) over time, so I unmounted it and
On 20.06.2014 20:08, Patrick Georgi wrote:
Am 20.06.2014 22:01, schrieb Rafael Vanoni:
Take serial number, for example. I'd like each different system that I
build to have its own serial number, and building coreboot for every
serial number doesn't scale.
We have an .id section just below the
On 20.06.2014 20:43, Patrick Georgi wrote:
Am 20.06.2014 22:40, schrieb Vladimir 'φ-coder/phcoder' Serbinenko:
(think MAC address).
I guess PC technology is finally beyond requiring those at fixed magic
offsets. Some of our chipsets still need it that way.
having fixed indexes doesn't scale
On 11.06.2014 09:46, derpeter wrote:
I tried this last month. I cherrypickt everything execpt the video fix
and got a working coreboot.
Sadly i could not bring the wacom to work but i'm not sure if its a
problem of coreboot or linux.
Submit logs then: Xorg log, dmesg and coreboot log.
On 05.04.2014 19:02, mrnuke wrote:
When an event happens, on the other hand, like a hotkey, or AC is removed, it
does not generate an SCI that would lead to a query call (_Qxx). Instead it
spits out an SMI. I know for a fact that the SCI and SMI GPEs are where we
expect them to be.
What do
On 29.03.2014 07:45, Stefan Reinauer wrote:
* Andrew Wu andrewwu...@gmail.com [140327 14:00]:
Sorry, I checked Vortex86EX CPU datasheet, but it seems there is no
workaround can do it.
So if I want to get rid of romcc, maybe I have to write DRAM init code
in assembly, That is not very easy.
On 29.03.2014 08:41, Patrick Georgi wrote:
Am Samstag, den 29.03.2014, 08:30 +0100 schrieb Vladimir
'φ-coder/phcoder' Serbinenko:
Do I get it correctly that your main problem is the heavy use of
#include romcc requires? If so why don't we just create a file with
#include's from all files from
On 26.03.2014 00:33, The Gluglug wrote:
-- alternatively:
ship coreboot without anything in src/mainboard.
have git repositories for each vendor/mainboard.
user downloads what they need, and a default .config for the board of
their choosing.
Git is developpement tree, not user-fetch tree.
On 25.03.2014 02:33, Stefan Reinauer wrote:
* David Hubbard david.c.hubbard+coreb...@gmail.com [140323 20:33]:
On Sun, Mar 23, 2014 at 12:58 PM, Vladimir ' -coder/phcoder' Serbinenko
phco...@gmail.com wrote:
On 23.03.2014 19:24, ron minnich wrote:
So I believe the problem is not
On 25.03.2014 06:34, ron minnich wrote:
On Mon, Mar 24, 2014 at 10:20 PM, Vladimir 'φ-coder/phcoder' Serbinenko
phco...@gmail.com mailto:phco...@gmail.com wrote:
I don't see how this prevents any of my propositions for the bulk of the
boards. The problem you describe isn't
On 23.03.2014 04:10, Peter Stuge wrote:
That isn't too different from creating a fork?
Fork is better. With fork we don't have to deal with the same people who
pushed the community out in the first place.
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On 23.03.2014 19:24, ron minnich wrote:
So I believe the problem is not the idea of gatekeepers, but the
manner in which they are proposed to work. Can you tell me what about
this upsets you? I want to understand.
The problem is that the proposal is that all commits go through
gatekeepers. It's
On 23.03.2014 19:24, ron minnich wrote:
I have friends who commit to grub2, and there seem to be gatekeepers
there; how do you manage that process?
In case of grub2 I admit we have exactly the problems I described. I'm
open to having more maintainers but right now it doesn't seem to be
feasible.
On 20.03.2014 22:33, Stefan Reinauer wrote:
During this time we collected over 250 different
mainboards. A great achievement,
I suppose that most of boards were contributed by non-commercial
community. Yet now you propose to basically kill this chicken nesting
golden eggs and make coreboot
On 20.03.2014 11:25, Allen Yan wrote:
Hi, David,
When at AsusTek Suzhou, my work is mainly responsible for bios
porting and fixing bug. There were four mainboards P5KPL-S, P5QL-E,
P5QL-SE, P5QL. All based on Intel platform and AMI Legacy BIOS Core
In the second half year of 2008, I
On 20.03.2014 12:12, Shant Kehyeian wrote:
Hello,
I have Samsung ARM chromebook series 3 Snow and I am trying to flesh
it and change the boot process.
So I build a coreboot.rom for that, but before I start to do that I
would like to ask about the payload. When I did the make menuconfig it
even mean that only
Linux-based works on your machine.
On Thu, Mar 20, 2014 at 4:05 PM, Vladimir 'φ-coder/phcoder' Serbinenko
phco...@gmail.com mailto:phco...@gmail.com wrote:
On 20.03.2014 12:12, Shant Kehyeian wrote:
Hello,
I have Samsung ARM chromebook series 3 Snow and I am
, 2014 at 12:23 PM, Vladimir 'φ-coder/phcoder'
Serbinenko
phco...@gmail.com mailto:phco...@gmail.com
mailto:phco...@gmail.com mailto:phco...@gmail.com wrote:
On 20.03.2014 13:10, Shant Kehyeian wrote:
In fact I do need the SeaBios not the GRUB2 to be able
On 20.03.2014 13:45, Peter Stuge wrote:
Vladimir 'φ-coder/phcoder' Serbinenko wrote:
On 20.03.2014 11:25, Allen Yan wrote:
Hi, David,
When at AsusTek Suzhou, my work is mainly responsible for bios
porting and fixing bug.
Do I understand it correctly, that you've had access to proprietary
On 20.03.2014 22:33, Stefan Reinauer wrote:
coreboot for the 21st century
setting up the project for the next decade
Purpose: Purge all boards / chipsets / cpus that require ROMCC in
romstage and known broken chipsets (sc520, i855)
coreboot is now officially 15 years old. One and a half
On 21.03.2014 01:39, Carl-Daniel Hailfinger wrote:
Hi Stefan,
streamlining development and maintenance is definitely absoutely
worthwhile. Getting rid of unmaintained code is also a good thing. The
guidelines presented in your mail look mostly good IMHO, but I'd like to
comment on a few
On 19.03.2014 21:06, Allen Yan wrote:
As Stefan Tauner's suggestion, maybe porting coreboot to new mainboard
Just a quick note: for porting to new chipset to be accepted, you need to:
1) Justify why this chipset is relevant. E.g. old chipsets most probably
aren't.
2) Prove that you're able to do
On 17.03.2014 17:08, Bernie Innocenti wrote:
Hello Vlad!
First of all, thank you very much for porting Coreboot to the X230.
I'm following your instructions [1] to build a coreboot image from head,
but I'm not sure how to configure things in menuconfig. Would you mind
sharing your .config
On 17.03.2014 20:39, Grim Schjetne wrote:
Bernie Innocenti ber...@codewiz.org writes:
First of all, thank you very much for porting Coreboot to the X230.
Indeed, this has made me all the more interested in the Coreboot
project. With an X201 and an X230 port, perhaps there is some hope
for
On 17.03.2014 08:00, Mono wrote:
Who knows, it might(!) fix some 5 year old bug?
Then it should be no problem for you to point one to us.
coreboot is not openhardware. It never was and never will be.
Openhardware is the only way to know what your hardware actually.
Coreboot is only how to kick
@ron: please provide more information about your qemu: version, how
built, options, patches,... Try -M pc-q35-1.7 and -M pc-i440fx-1.7. Try
specifying --no-kvm and --enable-kvm. Speyifying -cpu may help as well.
From my experience with GRUB, qemu has following flaws:
- From version to version they
On 02.03.2014 09:01, Muhammad Ramshad wrote:
When i search through the projects and organizations the coreboot
project grabbed my focus towards it because i am more interested in
Digital System Design and hardware a level development like processor
design and ISA designs.
And absolutely no
On 26.02.2014 04:24, mrnuke wrote:
On Wednesday, February 19, 2014 11:06:40 PM Paul Menzel wrote:
looking through `src/console/Kconfig` I noticed
You mean 'src/Kconfig' ?
if SOUTHBRIDGE_INTEL_BD82X6X DEFAULT_CONSOLE_LOGLEVEL_8
This is a layering violation. We shouldn't have
On 19.02.2014 23:03, Paul Menzel wrote:
Am Mittwoch, den 19.02.2014, 00:47 +0100 schrieb Vladimir 'φ-coder/phcoder'
Serbinenko:
On 19.02.2014 00:18, Paul Menzel wrote:
But in general I think I agree with Vladimir. CBMEM console should be
supported and if not then that should be fixed.
I
You do not get raminit debug output printed in ramstage.
Unfortunately, the case of incompatible DIMMs seems to be common one
with recent AGESA ports so information from romstage what DIMMs have
worked is actually relevant.
Just read this data from registers and print it.
Kyösti
On 18.02.2014 06:21, amlo...@tfwno.gf wrote:
As a privacy and freedom oriented PC/Linux user, it scares me how modern
day devices are becoming extremely proprietary. Companies are beginning
to ship their laptops/tablets with proprietary EFI systems which have
some nasty things in them. I
On 19.02.2014 00:18, Paul Menzel wrote:
But in general I think I agree with Vladimir. CBMEM console should be
supported and if not then that should be fixed.
I also agree, but it’ll take more time and the above is a good
work-around for the mean time.
Strongly disagree workarounds are like
On 14.02.2014 13:38, Dmitry Bagryanskiy wrote:
//Enable Com3
pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c02e1);
//Enable Com4
pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x001c03e1);
GEN*_DEC should not be set to com* ports. Instead there are dedicated
bits for enabling decode of serial
On 13.02.2014 01:23, Kevin O'Connor wrote:
Looking through the output of
$ git grep k8t890 src/mainboard/
the boards Asus A8V-E Deluxe, Asus A8V-E SE, Asus K8V-X, Asus M2V-MX SE
and Asus M2V should theoretically support that.
Okay. The SeaVGABIOS implementation is expecting a
.
That is pretty normal. Some firmwares store debug log or parameters in
flash.
best regards
Mono
On Sat, Feb 08, 2014 at 03:37:40PM +0100, Vladimir 'φ-coder/phcoder'
Serbinenko wrote:
On 08.02.2014 15:27, Mono wrote:
Hallo,
On Mon, Feb 03, 2014 at 10:16:30PM +0100, Vladimir 'φ-coder/phcoder
On 14.02.2014 00:03, Mohit Gupta wrote:
I am having trouble understanding i945 ram init code especially timing
parameters. Can some explain me in layman language? When I go through
DDR2 specification, timing related text is too complex and confusing.
Interested in getting very simple
On 10.02.2014 23:47, David Hendricks wrote:
On Sun, Feb 9, 2014 at 4:50 AM, Paul Menzel
paulepan...@users.sourceforge.net
mailto:paulepan...@users.sourceforge.net wrote:
Dear coreboot folks,
currently no coreboot messages are stored for boards not supporting
CBMEM console
On 11.02.2014 01:56, mrnuke wrote:
On Tuesday, February 11, 2014 12:04:33 AM Vladimir 'φ-coder/phcoder'
Serbinenko wrote:
If we let user supply
files at all, it should be added to report, not replace files, and it
should have some prefix to clearly indicate that user was involved
On 09.02.2014 13:50, Paul Menzel wrote:
Dear coreboot folks,
currently no coreboot messages are stored for boards not supporting
CBMEM console
Is there any remaining? If so it's an issue to be fixed
(or where this option is disabled (currently by default))
Change the defaults.
or no
On 09.02.2014 14:34, Paul Menzel wrote:
Am Sonntag, den 09.02.2014, 14:18 +0100 schrieb Vladimir 'φ-coder/phcoder'
Serbinenko:
On 09.02.2014 13:50, Paul Menzel wrote:
currently no coreboot messages are stored for boards not supporting
CBMEM console
Is there any remaining? If so it's
On 08.02.2014 15:27, Mono wrote:
Hallo,
On Mon, Feb 03, 2014 at 10:16:30PM +0100, Vladimir 'φ-coder/phcoder'
Serbinenko wrote:
CY8C24794-24LFXI
My guess: it's part of keyboard + touchpad
Do you already know which port is USBdebug one?
Yes, I found out with a USB stick, dmesg and lsusb -t
On 08.02.2014 23:13, Paul Menzel wrote:
Dear coreboot folks,
just a short announcement that after FOSDEM last weekend the next free
software event (in Europe(?)) is going to be LinuxTag in Berlin from May
8–10, 2014.
I won't be able to attend
The location is going to be different this
On 07.02.2014 17:57, Rubén Torrero Marijnissen wrote:
Hi,
I grew tired today of the default firmware that comes with my Google
Chromebook 14; just when I had my Arch Linux install perfectly working
somehow, by letting it attempt to boot Chrome OS, it messed up my
partitions.
If I have
On 06.02.2014 23:46, Ramkumar Ramachandra wrote:
Hi,
I have a Dell T5500 desktop, and I'd like to know if Coreboot supports
this.
No. http://www.coreboot.org/Supported_Motherboards
According to dmidecode, the motherboard is a Dell 0D883F.
Thanks.
Ram
signature.asc
Description:
Hello, all. I've uploaded digitizer support for X*t variants. Not tested
in current form yet (was developped on Jens Erat's X201T during FOSDEM).
Please test:
- X60t owners: http://review.coreboot.org/#/c/5113/
- X201t owners: http://review.coreboot.org/#/c/5096
- X230t owners: should work without
On 03.02.2014 21:43, Mono wrote:
Hallo Vladimir, Peter and Stefan
thank you for your emails! You already helped me alot. I don't expect to
successfully close this project in a fast run and I'm willing to learn a
number of tools.
At the moment I am still collecting hardware informations
On 03.02.2014 17:37, lee.changhan wrote:
Hi, I have some info about my motherboard here according to the FAQ page
to see if anyone can tell me about the compatibility between my BIOS and
coreboot.
Your motherboard is not compatible with coreboot.
1. Gigabyte GA-Z77-HD3 Motherboard
CY8C24794-24LFXI
My guess: it's part of keyboard + touchpad
Do you already know which port is USBdebug one?
Did you already test USB debug with dbgp?
Um, there are much more 00's than for the Thinkpad X60. Not sure what
this means
Different firmware. Most likely less functions are on it
On 02.02.2014 12:05, Paul Menzel wrote:
Dear coreboot folks,
if you push patches please either check them manually or simply let the
Git commit hooks do it for you by running `make gitconfig`. I know they
take a lot of time especially when you run them the first time in a
session. This
On 31.01.2014 17:08, Roberto A. Foglietta wrote:
2014-01-31 Peter Stuge pe...@stuge.se mailto:pe...@stuge.se:
Roberto A. Foglietta wrote:
I check the list of supported motherboards and laptops but I did
not found
in them the Lenovo Thinkpad T61
That means that
On 31.01.2014 17:21, ron minnich wrote:
If your only way to flash the flash is via a program, or something
embedded in the lenovo bios, stop now, or stockpile 20 or 30 of these
laptops, because you're going to create some bricks along the way.
Let me elaborate on this:
RTFM
On 31.01.2014 20:30, ron minnich wrote:
If you want a laptop to tear into and learn from, the old samsung x86
chromebook is hard to beat. ram and disk are standard and upgradable,
you can put a clip on the flash part, ...
Lenovo X201 and X230 both have those characteristics as well. Unlike
On 26.01.2014 05:55, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
http://www.coreboot.org/Infrastructure_Projects#Provide_update_paths_and_avoid_conflicts_in_addressing
(which mentions another solution to the problem)
Flashrom solution is interesting but it doesn't handle external
flashing
http://www.coreboot.org/Infrastructure_Projects#Provide_update_paths_and_avoid_conflicts_in_addressing
(which mentions another solution to the problem)
Flashrom solution is interesting but it doesn't handle external
flashing. It would be a nice addition to checksums for internal flashing
Hello, all. Due to my failue to foresee this problem if one upgrades X60
coreboot, you need to manually reset CMOS config or your trackpad may
not work as option trackpad_enable will get a garbage value. While I
admit my part of fault, I feel like we should have a way to update
options safely. I
Original Message
Subject: Re: [coreboot] coreboot port for macbook2,1
Date: Sat, 25 Jan 2014 01:23:12 +0100
From: Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com
To: Mono m...@posteo.de
On 24.01.2014 23:20, Mono wrote:
Hallo,
Would you help me on a coreboot port? I
On 25.01.2014 01:23, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
Original Message
Subject: Re: [coreboot] coreboot port for macbook2,1
Date: Sat, 25 Jan 2014 01:23:12 +0100
From: Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com
To: Mono m...@posteo.de
On 25.01.2014 01:28, mrnuke wrote:
On Saturday, January 25, 2014 12:51:25 AM Vladimir 'φ-coder/phcoder'
Serbinenko wrote:
Hello, all. Due to my failue to foresee this problem if one upgrades X60
coreboot, you need to manually reset CMOS config or your trackpad may
not work as option
Hello, all. I've just uploaded 2 patchsets: X201 which fixes all known
issues including S3 resume but except Gnome battery reporting. Top for
x201 is at
http://review.coreboot.org/#/c/4632/
and few separate patches with theme x201 (X201-specific) and
thinkpad (having benefits for X60/T60 as well).
On 05.01.2014 07:15, Gregg Levine wrote:
Part of the problem with laptops is that there is a thing on them
called an Embedded Controller, EC for short. Those devices do all of
the housekeeping chores that the main system has delegated to them.
For example certain functions are on it.
To
By now most boards and OS don't run correctly if ACPI tables are not
supplied. Ability by user to enable/disable their generation is just
increasing configuration matrix for no benefit. So I propose to hardwire
it to HAVE_ACPI_TABLES.
I feel like in current config there are too many options of
On 07.01.2014 00:12, mrnuke wrote:
On Monday, January 06, 2014 07:52:20 PM Vladimir 'φ-coder/phcoder' Serbinenko
wrote:
By now most boards and OS don't run correctly if ACPI tables are not
supplied. Ability by user to enable/disable their generation is just
increasing configuration matrix
On 15.09.2012 05:47, Keith Hui wrote:
Hi all,
I'm back. With a new laptop.
I'm now rocking a Lenovo x230 tablet,
http://review.coreboot.org/#/c/4614/
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