Re: [Doxygen-users] Some VHDL questions

Viktor Puš wrote: > >> >> >> Forcing and releasing signals. >> >> But VHDL-2008 allows this in pure VHDL. >> >> << tb.uut.s >> <= release;-- stop overriding >> >> v <= force in '1';-- force effective value >> v <= force out '0'; -- force driving value >> >>

Re: [Doxygen-users] Some VHDL questions

> > > Forcing and releasing signals. > > But VHDL-2008 allows this in pure VHDL. > > << tb.uut.s >> <= release;-- stop overriding > > v <= force in '1';-- force effective value > v <= force out '0'; -- force driving value > > v <= release in; --

Re: [Doxygen-users] Some VHDL questions

Viktor Puš wrote: > >>> >>> >>> >> First of all check your VHDL syntax! There are some errors. >> Create a dummy entity submodule and the instantiation will be documented. >> >> > > > There were some errors, thanks. However I have another example, this time > the VHDL syntax should be

Re: [Doxygen-users] Some VHDL questions

>> >> >> > First of all check your VHDL syntax! There are some errors. > Create a dummy entity submodule and the instantiation will be documented. > > There were some errors, thanks. However I have another example, this time the VHDL syntax should be correct: entity top is port( input

Re: [Doxygen-users] Some VHDL questions

Viktor Puš wrote: > > Hi all, > > I`m trying to use Doxygen to document the VHDL code, but I`m quite new to > it (Doxygen, not VHDL). I have two questions: > > Q1: > How exactly does the automatic brief/details division work? The example at > http://www.stack.nl/~dimitri/doxygen/docblocks.htm