On 8/22/25 12:26, Michal Wilczynski wrote:
>
>
> On 8/22/25 12:04, Michal Wilczynski wrote:
>>
>>
>> On 8/22/25 11:28, Matt Coster wrote:
>>> On 21/08/2025 23:20, Michal Wilczynski wrote:
>>>> Update the Imagination PVR DRM driver to leverage th
On 8/22/25 12:04, Michal Wilczynski wrote:
>
>
> On 8/22/25 11:28, Matt Coster wrote:
>> On 21/08/2025 23:20, Michal Wilczynski wrote:
>>> Update the Imagination PVR DRM driver to leverage the pwrseq framework
>>> for managing the complex power sequence of the
On 8/22/25 11:28, Matt Coster wrote:
> On 21/08/2025 23:20, Michal Wilczynski wrote:
>> Update the Imagination PVR DRM driver to leverage the pwrseq framework
>> for managing the complex power sequence of the GPU on the T-HEAD TH1520
>> SoC.
>>
>> To cleanly
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Reviewed-by: Matt Coster
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+
s the `power-domain-names` property.
Link:
https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0...@linaro.org/ [1]
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Matt Coster
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Acked-by: Matt Coster
Signed-off-by: M
ntinue to call the appropriate functions via the ops
table.
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 22 +
drivers/gpu/drm/imagination/pvr_device.h | 17
drivers/gpu/drm/imagination/pvr_drv.c| 23 -
drivers/gpu/drm/imagination/
543eee0d70083daf4de8fe15d585
change-id: 20250414-apr_14_for_sending-5b3917817acc
Best regards,
--
Michal Wilczynski
On 8/21/25 11:02, Matt Coster wrote:
> On 20/08/2025 18:08, Ulf Hansson wrote:
>> On Wed, 20 Aug 2025 at 10:56, Michal Wilczynski
>>> +#endif /* IS_ENABLED(CONFIG_POWER_SEQUENCING) */
>>
>> Yeah, this looks really messy to me.
>>
>> If there is somethi
rs
were skewed. I shared the image in the 'Mainline Linux for RISC-V'
telegram chat.
For the current version from Icenowy it's still a bit messy to share
however it includes addition to inno-hdmi driver to make it works a bit
more like dw-hdmi currently - introduce a probe function, not just
bind, so it doesn't use component framework. Plus changes to
clocks/resets that were discussed.
>
> Did you actually manage to get display out over hdmi? The hdmi output from
> last years starfive driver gave me some strange output issues that I'm
> currently just living with, but would love to see it gone.
>
On the current version of the DC driver I'm still working on it.
Best regards,
--
Michal Wilczynski
output, intf);
> + if (IS_ERR(next)) {
> + ret = PTR_ERR(next);
> + goto err_free_bridge;
> + }
> +
> + bridge->next = next;
> +
> + ret = drm_simple_encoder_init(drm_dev, &bridge->enc,
> + (intf == VSDC_OUTPUT_INTERFACE_DPI) ?
> + DRM_MODE_ENCODER_DPI :
> + DRM_MODE_ENCODER_NONE);
> + if (ret) {
> + dev_err(drm_dev->dev,
> + "Cannot initialize encoder for output %u\n", output);
> + goto err_free_bridge;
> + }
> +
> + bridge->enc.possible_crtcs = drm_crtc_mask(&crtc->base);
> +
> + ret = drm_bridge_attach(&bridge->enc, &bridge->base, NULL,
> + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> + if (ret) {
> + dev_err(drm_dev->dev,
> + "Cannot attach bridge for output %u\n", output);
> + goto err_cleanup_encoder;
> + }
> +
> + bridge->conn = drm_bridge_connector_init(drm_dev, &bridge->enc);
> + if (IS_ERR(bridge->conn)) {
> + dev_err(drm_dev->dev,
> + "Cannot create connector for output %u\n", output);
> + ret = PTR_ERR(bridge->conn);
> + goto err_cleanup_encoder;
> + }
> + drm_connector_attach_encoder(bridge->conn, &bridge->enc);
> +
> + return bridge;
> +
> +err_cleanup_encoder:
> + drm_encoder_cleanup(&bridge->enc);
> +err_free_bridge:
> + devm_kfree(drm_dev->dev, bridge);
> +
> + return ERR_PTR(ret);
> +}
Best regards,
--
Michal Wilczynski
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
ntinue to call the appropriate functions via the ops
table.
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 22 +---
drivers/gpu/drm/imagination/pvr_device.h | 22
drivers/gpu/drm/imagination/pvr_drv.c| 27 -
drivers/gpu/drm/imagination/
s the `power-domain-names` property.
Link:
https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0...@linaro.org/ [1]
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 37 +-
1 file changed, 29 inser
https://lore.kernel.org/all/20250805-apr_14_for_sending-v11-0-b7eecefcf...@samsung.com/
---
Michal Wilczynski (4):
drm/imagination: Use pwrseq for TH1520 GPU power management
dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU support
riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node
On 8/5/25 01:25, Michal Wilczynski wrote:
> This patch series introduces support for the Imagination IMG BXM-4-64
> GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
> managing the GPU's complex power-up and power-down sequence, which
> involves multiple
s the `power-domain-names` property.
Link:
https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0...@linaro.org/ [1]
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 37 +-
1 file changed, 29 inser
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
sending-v10-0-e85802902...@samsung.com/
---
Michal Wilczynski (4):
drm/imagination: Use pwrseq for TH1520 GPU power management
dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU support
riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node
drm/imagination: Enable PowerVR drive
ntinue to call the appropriate functions via the ops
table.
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 22 +---
drivers/gpu/drm/imagination/pvr_device.h | 22
drivers/gpu/drm/imagination/pvr_drv.c| 27 -
drivers/gpu/drm/imagination/
On 8/4/25 08:13, Krzysztof Kozlowski wrote:
> On Fri, Aug 01, 2025 at 12:31:00PM +0200, Michal Wilczynski wrote:
>>
>> v10:
>> - Squashed the two dt-binding patches back into a single commit.
>> - Simplified the B-series GPU rule by removing the not clause.
>&g
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
s the `power-domain-names` property.
Link:
https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0...@linaro.org/ [1]
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 33 --
1 file changed, 25 insertions(+), 8 deletions(-)
diff --
twy1yy...@mail.gmail.com/
[2] -
https://lore.kernel.org/all/20250219140239.1378758-1-m.wilczyn...@samsung.com/
[3] -
https://lore.kernel.org/all/20250731-apr_14_for_sending-v9-0-c242dc1ff...@samsung.com/
---
Michal Wilczynski (4):
drm/imagination: Use pwrseq for TH1520 GPU power management
dt
ntinue to call the appropriate functions via the ops
table.
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 22 +---
drivers/gpu/drm/imagination/pvr_device.h | 22
drivers/gpu/drm/imagination/pvr_drv.c| 27 -
drivers/gpu/drm/imagination/
: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 36 ++
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
index
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
ntinue to call the appropriate functions via the ops
table.
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 22 +---
drivers/gpu/drm/imagination/pvr_device.h | 22
drivers/gpu/drm/imagination/pvr_drv.c| 27 -
drivers/gpu/drm/imagination/
eries GPU rule is also updated to include img,img-bxm-4-64
and to explicitly exclude the TH1520.
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 29 +-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/Documentation/devic
g/all/20250724-apr_14_for_sending-v8-0-0714bef83...@samsung.com/
---
Michal Wilczynski (5):
drm/imagination: Use pwrseq for TH1520 GPU power management
dt-bindings: gpu: img,powervr-rogue: Define power domains per variant
dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatibl
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
ki
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 32 +-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
b/Documentation/devicetree/bindings/gpu/img,powervr-
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
ntinue to call the appropriate functions via the ops
table.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 22 +---
drivers/gpu/drm/imagination/pvr_device.h | 22
drivers/gpu/drm/imagination/pvr_drv.c|
0626-apr_14_for_sending-v7-0-6593722e0...@samsung.com/
---
Michal Wilczynski (4):
drm/imagination: Use pwrseq for TH1520 GPU power management
dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible
riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node
drm/imagina
On 7/23/25 18:50, Matt Coster wrote:
> On 23/07/2025 17:26, Michal Wilczynski wrote:
>> On 7/23/25 11:45, Matt Coster wrote:
>>> On 25/06/2025 15:41, Krzysztof Kozlowski wrote:
>>>> On 25/06/2025 16:18, Michal Wilczynski wrote:
>>>>>
>>&g
On 7/23/25 11:45, Matt Coster wrote:
> On 25/06/2025 15:41, Krzysztof Kozlowski wrote:
>> On 25/06/2025 16:18, Michal Wilczynski wrote:
>>>
>>>
>>> On 6/25/25 15:55, Krzysztof Kozlowski wrote:
>>>> On 25/06/2025 14:45, Michal Wilczynski wrote:
On 7/3/25 12:21, Michal Wilczynski wrote:
>
>
> On 6/26/25 11:33, Michal Wilczynski wrote:
>> Update the Imagination PVR DRM driver to leverage the pwrseq framework
>> for managing the complex power sequence of the GPU on the T-HEAD TH1520
>> SoC.
>>
>>
On 6/26/25 11:33, Michal Wilczynski wrote:
> Update the Imagination PVR DRM driver to leverage the pwrseq framework
> for managing the complex power sequence of the GPU on the T-HEAD TH1520
> SoC.
>
> To cleanly separate platform specific logic from the generic driver,
> thi
th the specific TH1520
implementation and for other SoCs that use the B-series Rogue GPUs.
Acked-by: Krzysztof Kozlowski
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 26 +-
latform.
Add a dependency on MMU to fix a build warning on RISC-V configurations
without an MMU.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --
ewski
Reviewed-by: Drew Fustini
Signed-off-by: Michal Wilczynski
---
arch/riscv/boot/dts/thead/th1520.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi
b/arch/riscv/boot/dts/thead/th1520.dtsi
index
1db0054c4e093400e9dbebcee
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
ain
[1] -
https://lore.kernel.org/all/capdykfpi6_cd++a9sbgbvjcubsqs6ycpnttkrqhqmtwy1yy...@mail.gmail.com/
[2] -
https://lore.kernel.org/all/20250219140239.1378758-1-m.wilczyn...@samsung.com/
[3] -
https://lore.kernel.org/all/20250623-apr_14_for_sending-v6-0-6583ce0f6...@samsung.com/
---
Michal Wi
The runtime PM callbacks now call the appropriate
functions via the ops table.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/pvr_device.c | 36 +++-
drivers/gpu/drm/imagination/pvr_device.h | 17
drivers/gpu/
On 6/24/25 15:53, Matt Coster wrote:
> On 23/06/2025 12:42, Michal Wilczynski wrote:
>> Update the Imagination PVR DRM driver to leverage the pwrseq framework
>> for managing the power sequence of the GPU on the T-HEAD TH1520 SoC.
>>
>> To cleanly handle the TH1520&#x
On 6/25/25 15:55, Krzysztof Kozlowski wrote:
> On 25/06/2025 14:45, Michal Wilczynski wrote:
>>
>>
>> On 6/24/25 15:53, Matt Coster wrote:
>>> On 23/06/2025 12:42, Michal Wilczynski wrote:
>>>> Update the img,powervr-rogue.yaml to include the T-HEAD
On 6/24/25 15:53, Matt Coster wrote:
> On 23/06/2025 12:42, Michal Wilczynski wrote:
>> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's
>> specific GPU compatible string.
>>
>> The thead,th1520-gpu compatible, along with its full chain
>&g
On 6/24/25 15:54, Matt Coster wrote:
> On 23/06/2025 12:42, Michal Wilczynski wrote:
>> Several RISC-V boards feature Imagination GPUs that are compatible with
>> the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi
>> 4A board. This commit adjusts
On 6/23/25 16:32, Bartosz Golaszewski wrote:
> On Mon, Jun 23, 2025 at 1:44 PM Michal Wilczynski
> wrote:
>>
>> Introduce the pwrseq-thead-gpu driver, a power sequencer provider for
>> the Imagination BXM-4-64 GPU on the T-HEAD TH1520 SoC. This driver
>>
On 6/19/25 03:43, Drew Fustini wrote:
> On Wed, Jun 18, 2025 at 12:22:06PM +0200, Michal Wilczynski wrote:
>> This patch series introduces support for the Imagination IMG BXM-4-64
>> GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
>> managing the GPU&#
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
ewski
Reviewed-by: Drew Fustini
Signed-off-by: Michal Wilczynski
---
arch/riscv/boot/dts/thead/th1520.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi
b/arch/riscv/boot/dts/thead/th1520.dtsi
index
1db0054c4e093400e9dbebcee
s
to the GPU's "core" and "sys" clocks, and the GPU core reset. These,
along with clkgen_reset obtained from parent aon node, allow it to
perform the complete sequence.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
MAINTAINERS
g,img-bxm-4-64 is also
ensured by adding it to the relevant allOf condition.
Acked-by: Krzysztof Kozlowski
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 -
1 file chang
control of the sequencing logic.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/pmdomain/thead/Kconfig | 1 +
drivers/pmdomain/thead/th1520-pm-domains.c | 51 ++
2 files changed, 52 insertions(+)
di
functions for both manual and pwrseq-based sequences
are introduced to support this.
Reviewed-by: Ulf Hansson
Reviewed-by: Bartosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 31 +++--
dr
rtosz Golaszewski
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imagination/Kconfig
b/drivers/gpu/drm/imagination/Kconfig
index
5f9fff43d6baadc42ebf48d91729bfbf27e
ed-by: Ulf Hansson
Reviewed-by: Drew Fustini
Reviewed-by: Bartosz Golaszewski
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Michal Wilczynski
---
Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/
-
https://lore.kernel.org/all/capdykfpi6_cd++a9sbgbvjcubsqs6ycpnttkrqhqmtwy1yy...@mail.gmail.com/
[2] -
https://lore.kernel.org/all/20250219140239.1378758-1-m.wilczyn...@samsung.com/
[3] -
https://lore.kernel.org/all/20250618-apr_14_for_sending-v5-0-27ed33ea5...@samsung.com/
---
Michal Wilczynski (8):
> did you mean 'ROGUE_MMUCTRL_PAGE_4KB_RANGE_SHIFT'?
> ROGUE_MMUCTRL_PAGE_X_RANGE_SHIFT;
> ^~~~
> ROGUE_MMUCTRL_PAGE_4KB_RANGE_SHIFT
>>> drivers/gpu/drm/imagination/pvr_mmu.c:1714:1: warning: control reac
is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v4:
https://lore.kernel.org/r/20250614-apr_14_for_sending-v4-0-8e3945c81...@samsung.com
---
Michal Wilczynski (8):
power: sequencing: Add T-HEAD TH1520 GPU power sequencer driver
dt-bindin
s
to the GPU's "core" and "sys" clocks, and the GPU core reset. These,
along with clkgen_reset obtained from parent aon node, allow it to
perform the complete sequence.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
MAINTAINERS
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
arch/riscv/boot/dts/thead/th1520.dtsi
g,img-bxm-4-64 is also
ensured by adding it to the relevant allOf condition.
Acked-by: Krzysztof Kozlowski
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
t also adds the prerequisite
dt-bindings/reset/thead,th1520-reset.h include to make the
TH1520_RESET_ID_GPU_CLKGEN available. This include was previously
dropped during a conflict resolution [1].
Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1]
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczy
erage.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imagination/Kconfig
b/drivers/gpu/drm/imagination/Kconfig
index
5f9fff43d6baadc42ebf48d91729bfbf27e
functions for both manual and pwrseq-based sequences
are introduced to support this.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 31 +++--
drivers/gpu/drm/imagination/pvr_device.h
control of the sequencing logic.
Signed-off-by: Michal Wilczynski
---
drivers/pmdomain/thead/Kconfig | 1 +
drivers/pmdomain/thead/th1520-pm-domains.c | 51 ++
2 files changed, 52 insertions(+)
diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdo
ed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml
b/Documentation/devicetree/bindings/firmware/th
On 6/18/25 00:14, Drew Fustini wrote:
> On Sat, Jun 14, 2025 at 08:06:06PM +0200, Michal Wilczynski wrote:
>> This patch series introduces support for the Imagination IMG BXM-4-64
>> GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
>> managing the GPU&#
On 6/16/25 11:40, Bartosz Golaszewski wrote:
> On Sat, Jun 14, 2025 at 8:09 PM Michal Wilczynski
> wrote:
>>
>> Update the Imagination PVR DRM driver to leverage the pwrseq framework
>> for managing the power sequence of the GPU on the T-HEAD TH1520 SoC.
>>
>
without MMU
support, while MMU support is mandatory for ARM64.
Would an acceptable fix be to require an explicit dependency on the MMU,
like so?
depends on (ARM64 || RISCV) && MMU
> Selected by [y]:
> - DRM_POWERVR [=y] && HAS_IOMEM [=y] && (ARM64 || RISCV [=y]) && DRM
> [=y] && PM [=y]
>
Best regards,
--
Michal Wilczynski
create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.h
>> create mode 10064
g,img-bxm-4-64 is also
ensured by adding it to the relevant allOf condition.
Acked-by: Krzysztof Kozlowski
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
t also adds the prerequisite
dt-bindings/reset/thead,th1520-reset.h include to make the
TH1520_RESET_ID_GPU_CLKGEN available. This include was previously
dropped during a conflict resolution [1].
Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1]
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczy
ed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml
b/Documentation/devicetree/bindings/firmware/th
bling compilation on RISC-V, we expand support for these GPUs,
providing graphics acceleration capabilities and enhancing hardware
compatibility on RISC-V platforms.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 2 +-
1 file changed, 1 insertion(
control of the sequencing logic.
Signed-off-by: Michal Wilczynski
---
drivers/pmdomain/thead/Kconfig | 1 +
drivers/pmdomain/thead/th1520-pm-domains.c | 53 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdo
btain
handles to the GPU's "core" and "sys" clocks, and the GPU core reset.
These, along with clkgen_reset obtained from parent aon node, allow it
to perform the complete sequence.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
MAINTAINERS
capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC.
Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be
controlled programatically.
Reviewed-by: Ulf Hansson
Signed-off-by: Michal Wilczynski
---
arch/riscv/boot/dts/thead/th1520.dtsi
-
https://lore.kernel.org/all/20250219140239.1378758-1-m.wilczyn...@samsung.com/
[3] -
https://lore.kernel.org/all/20250530-apr_14_for_sending-v3-0-83d5744d9...@samsung.com/
---
Michal Wilczynski (8):
power: sequencing: Add T-HEAD TH1520 GPU power sequencer driver
dt-bindings: firmware: thead,th
lf Hansson
Signed-off-by: Michal Wilczynski
---
drivers/gpu/drm/imagination/Kconfig | 1 +
drivers/gpu/drm/imagination/pvr_device.c | 31 ++--
drivers/gpu/drm/imagination/pvr_device.h | 17 +++
drivers/gpu/drm/imagination/pvr_drv.c| 6 +++
drivers/gpu/drm/imag
On 6/13/25 10:25, Michal Wilczynski wrote:
>
>
> On 6/13/25 08:44, Krzysztof Kozlowski wrote:
>> On 11/06/2025 14:01, Michal Wilczynski wrote:
>>>
>>> However, this leads me back to a fundamental issue with the
>>> consumer side implementati
On 6/13/25 08:44, Krzysztof Kozlowski wrote:
> On 11/06/2025 14:01, Michal Wilczynski wrote:
>>
>> However, this leads me back to a fundamental issue with the
>> consumer side implementation in the generic pvr_device.c driver. The
>> current fallback code is:
>
On 6/5/25 10:10, Bartosz Golaszewski wrote:
> On Thu, Jun 5, 2025 at 9:47 AM Michal Wilczynski
> wrote:
>>
>>
>>
>> On 6/4/25 14:07, Krzysztof Kozlowski wrote:
>>> On 04/06/2025 13:53, Michal Wilczynski wrote:
>>>>>>
>>>&g
On 6/4/25 14:07, Krzysztof Kozlowski wrote:
> On 04/06/2025 13:53, Michal Wilczynski wrote:
>>>>
>>>> The GPU node will depend on the AON node, which will be the sole
>>>> provider for the 'gpu-power' sequencer (based on the discussion in patc
On 6/3/25 14:27, Ulf Hansson wrote:
> On Fri, 30 May 2025 at 00:24, Michal Wilczynski
> wrote:
>>
>> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD
>> TH1520 SoC used by the Lichee Pi 4A board. This node enables support for
>> the GPU us
On 6/4/25 08:36, Krzysztof Kozlowski wrote:
> On 03/06/2025 21:43, Michal Wilczynski wrote:
>>>> + * and resets. Otherwise, we fall back to managing them ourselves.
>>>> + */
>>>> + pvr_dev->pwrseq = devm_pwrseq_get(dev, "
Maybe just follow that
> pattern, add a module under drivers/power/sequencing/ called
> pwrseq-th1520-pwrseq.c and call its init function from the pm-domains
> module?
Right, sorry I haven't noticed this and responded to previous message.
Thanks for the direction !
>
> Bart
>
Best regards,
--
Michal Wilczynski
On 6/3/25 15:28, Krzysztof Kozlowski wrote:
> On Fri, May 30, 2025 at 12:23:50AM GMT, Michal Wilczynski wrote:
>> Update the Imagination PVR DRM driver to leverage the pwrseq framework
>> for managing the power sequence of the GPU on the T-HEAD TH1520 SoC.
>>
>> In pv
On 6/3/25 15:22, Krzysztof Kozlowski wrote:
> On Fri, May 30, 2025 at 12:23:53AM GMT, Michal Wilczynski wrote:
>> Add the device tree node for the T-HEAD TH1520 GPU power sequencer
>> (gpu_pwrseq) to the th1520.dtsi file.
>>
>> This node instantiates the thead,th15
On 6/3/25 14:25, Ulf Hansson wrote:
> On Fri, 30 May 2025 at 00:24, Michal Wilczynski
> wrote:
>>
>> This patch series introduces support for the Imagination IMG BXM-4-64
>> GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
>> managing the GP
On 6/3/25 15:35, Bartosz Golaszewski wrote:
> On Tue, Jun 3, 2025 at 3:19 PM Krzysztof Kozlowski wrote:
>>
>> On Mon, Jun 02, 2025 at 10:29:13PM GMT, Michal Wilczynski wrote:
>>>>> +description: |
>>>>> + This binding describes the power seque
On 6/3/25 15:20, Krzysztof Kozlowski wrote:
> On Fri, May 30, 2025 at 12:23:52AM GMT, Michal Wilczynski wrote:
>> TH1520_RESET_ID_GPU_CLKGEN and TH1520_RESET_ID_GPU are required for GPU
>> power sequencing to work. To make these symbols available, add the
>> necessary i
On 6/2/25 16:46, Bartosz Golaszewski wrote:
> On Fri, May 30, 2025 at 12:24 AM Michal Wilczynski
> wrote:
>>
>> Introduce device tree bindings for a new power sequencer provider
>> dedicated to the T-HEAD TH1520 SoC's GPU.
>>
>> The thead,th1520-gpu
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