On Sun, Feb 20, 2022 at 10:36:35PM +0100, Sam Ravnborg wrote:
> Hi José,
>
> On Sun, Feb 20, 2022 at 08:52:12PM +0100, José Expósito wrote:
> > Use the "drm_of_find_panel_or_bridge" function instead of a custom
> > version of it to reduce the boilerplate.
> Thanks for looking into this.
Hi Sam,
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 --
1
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
v2: Check if the log object allocated from local memory or system memory
and according setup the iosys_map (Lucas)
Cc: Lucas De
On 02/03/2022 02:00, Inki Dae wrote:
> Hi Krzysztof,
>
> 22. 2. 7. 01:51에 Krzysztof Kozlowski 이(가) 쓴 글:
>> On 25/03/2019 08:13, Andrzej Hajda wrote:
>>> GSCALERs in Exynos5433 have local path to DECON and DECON_TV.
>>> They can be used as extra planes with support for non-RGB formats and
>>>
Hi Nikolaus,
Le jeu., mars 3 2022 at 17:43:05 +0100, H. Nikolaus Schaller
a écrit :
Hi Neil,
Am 03.03.2022 um 17:30 schrieb H. Nikolaus Schaller
:
Hi Neil,
Am 03.03.2022 um 17:23 schrieb Neil Armstrong
:
Hi,
On 26/02/2022 18:12, H. Nikolaus Schaller wrote:
so that
https://bugzilla.kernel.org/show_bug.cgi?id=215652
--- Comment #6 from Alex Deucher (alexdeuc...@gmail.com) ---
(In reply to Erhard F. from comment #5)
>
> With CONFIG_DRM_RADEON=m radeon does not load and I still get "modprobe:
> ERROR: could not insert 'radeon': Unknown symbol in module, or
Hi Krzysztof,
On 03.03.2022 17:03, Krzysztof Kozlowski wrote:
> On 02/03/2022 02:00, Inki Dae wrote:
>> 22. 2. 7. 01:51에 Krzysztof Kozlowski 이(가) 쓴 글:
>>> On 25/03/2019 08:13, Andrzej Hajda wrote:
GSCALERs in Exynos5433 have local path to DECON and DECON_TV.
They can be used as extra
Hi,
On 26/02/2022 18:12, H. Nikolaus Schaller wrote:
so that specialization drivers like ingenic-dw-hdmi can enable polling.
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9 +
include/drm/bridge/dw_hdmi.h | 1 +
2 files changed,
Updated series about drm bridge conversion of exynos dsi.
Previous version can be accessible, here [1].
Patch 1: tc358764 panel_bridge API
Patch 2: connector reset
Patch 3: bridge attach in MIC
Patch 4: panel_bridge API
Patch 5: bridge conversion
Patch 6: atomic functions
[1]
Hi Neil,
Le jeu., mars 3 2022 at 17:23:02 +0100, Neil Armstrong
a écrit :
Hi,
On 26/02/2022 18:12, H. Nikolaus Schaller wrote:
so that specialization drivers like ingenic-dw-hdmi can enable
polling.
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9
Hi Paul and Neil,
> Am 03.03.2022 um 17:46 schrieb Paul Cercueil :
>
> Hi Neil,
>
> Le jeu., mars 3 2022 at 17:23:02 +0100, Neil Armstrong
> a écrit :
>> Hi,
>> On 26/02/2022 18:12, H. Nikolaus Schaller wrote:
>>> so that specialization drivers like ingenic-dw-hdmi can enable polling.
>>>
The "drm_plane_funcs.format_mod_supported" can be removed in favor of
the default implementation.
Signed-off-by: José Expósito
Reviewed-by: Simon Ser
---
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
Hi Paul, Neil,
> Am 03.03.2022 um 18:20 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> [snip]
>
>>> Well he said "the Ingenic DRM core" aka ingenic-drm-drv.c. You do have
>>> access to the main drm_device in the ingenic_drm_bind() function, so you
>>> can add it there (with a cleanup function
https://bugzilla.kernel.org/show_bug.cgi?id=215652
--- Comment #7 from Erhard F. (erhar...@mailbox.org) ---
(In reply to Alex Deucher from comment #6)
> You need to make sure the firmware is in your initrd. When the kernel
> loads, it loads from the initrd. There is no filesystem mounted yet
On 2/21/2022 4:37 AM, Dmitry Baryshkov wrote:
On 10/02/2022 13:34, Vinod Koul wrote:
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Also, fetch and pass DSC configuration for DSI panels to DPU
Rework the fbdev deferred-I/O to not interfere with fields of struct
page. Make the code more flexible and implement GEM SHMEM mmap on top
of it.
This patchset removes the need for a special shadow framebuffer for
fbdev mmap when using GEM SHMEM. SHMEM pages are now mmap'ed from
/dev/fb directly.
Store the per-page state for fbdev's deferred I/O in struct
fb_deferred_io_pageref. Maintain a list of pagerefs for the pages
that have to be flushed out to video memory. Update all affected
drivers.
Like with pages before, fbdev acquires a pageref when an mmaped page
of the framebuffer is being
The fbdev mmap function fb_mmap() unconditionally overrides the
driver's implementation if deferred I/O has been activated. This
makes it hard to implement mmap with anything but a vmalloc()'ed
software buffer. That is specifically a problem for DRM, where
video memory is maintained by a memory
Add drm_fb_helper_vm_page_mkwrite(), a helper to track pages written
by fbdev userspace. DRM drivers should use this function to implement
fbdev deferred I/O.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_fb_helper.c | 10 ++
include/drm/drm_fb_helper.h | 9 +
2
Implement struct drm_driver.dumb_create_fbdev for GEM SHMEM. The
created buffer object returned by this function implements deferred
I/O for its mmap operation.
Add this feature to a number of drivers that use GEM SHMEM helpers
as shadow planes over their regular video memory. The new macro
Implement struct drm_driver.dumb_create_fbdev with the helpers
provided by GEM SHMEM. Fbdev deferred I/O will now work without
an intermediate shadow buffer for mmap.
As the virtio driver replaces several of the regular GEM SHMEM
functions with its own implementation, some additional code is
Don't select shadow buffering for the fbdev console explicitly. The
fbdev emulation's heuristic will enable it for any framebuffer with
.dirty callback.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/tiny/simpledrm.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Provide struct drm_driver.dumb_create_fbdev, a callback hook for
fbdev dumb buffers. Wire up fbdev and client helpers to use the new
interface, if present.
This acknowledges the fact that fbdev buffers are different. The most
significant difference to regular GEM BOs is in mmap semantics. Fbdev
DRM drivers will be able to handle deferred I/O by themselves. So
a driver will be able to use deferred I/O without an intermediate
shadow buffer.
Prepare fbdev emulation by separating shadow buffers and deferred
I/O from each other.
Signed-off-by: Thomas Zimmermann
---
Refactor the page-write handler and export it as helper function
fb_deferred_io_page_mkwrite(). Drivers that implement struct
vm_operations_struct.page_mkwrite for deferred I/O should use the
function to let fbdev track written pages of mmap'ed framebuffer
memory.
Signed-off-by: Thomas Zimmermann
On Thu, Mar 3, 2022 at 1:17 PM Rob Clark wrote:
>
> On Thu, Mar 3, 2022 at 12:47 PM Stephen Boyd wrote:
> >
> > Quoting Rob Clark (2022-03-03 11:46:47)
> > > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> > > index fde9a29f884e..0ba1dbd4e50f 100644
> > > ---
Reviewed-by: Lyude Paul
Will push this to the appropriate drm-misc repository in just a little bit
On Mon, 2022-02-28 at 22:23 +0800, Guo Zhengkui wrote:
> Fix following coccicheck warning:
> drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c:316:11-12:
> WARNING this kind of initialization is
Quoting Vinod Polimera (2022-03-03 03:42:59)
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of supported
>
From: Rob Clark
Add a SYSPROF param for system profiling tools like Mesa's pps-producer
(perfetto) to control behavior related to system-wide performance
counter collection. In particular, for profiling, one wants to ensure
that GPU context switches do not effect perfcounter state, and might
From: Rob Clark
Any app controlled perfcntr collection (GL_AMD_performance_monitor, etc)
does not require counters to maintain state across context switches. So
clear them if systemwide profiling is not active.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 29
From: Tom Rix
Clang static analysis reports this issue
anx7625.c:876:13: warning: The left operand of '&' is
a garbage value
if (!(bcap & 0xOA01)) {
^
bcap is only set by a successful call to
anx7625_aux_trans(). So check.
Fixes: cd1637c7e480 ("drm/bridge: anx7625: add HDCP
On Thu, Mar 03, 2022 at 12:19:57PM -0600, Gustavo A. R. Silva wrote:
> On Thu, Mar 03, 2022 at 09:43:28AM -0800, Kees Cook wrote:
> > On Thu, Mar 03, 2022 at 11:25:03AM -0600, Gustavo A. R. Silva wrote:
> > > Fix the following Wstringop-overflow warnings when building with GCC-11:
> > >
> > >
On 3/3/2022 1:11 PM, Rob Clark wrote:
On Thu, Mar 3, 2022 at 12:42 PM Abhinav Kumar wrote:
Hi Rob
On 3/3/2022 11:46 AM, Rob Clark wrote:
From: Rob Clark
Update headers from mesa commit:
commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef
Author: Rob Clark
AuthorDate: Wed
Quoting Dmitry Baryshkov (2022-02-16 20:31:42)
> This is the second part of
> https://patchwork.freedesktop.org/series/91631/ reworked and cleaned up.
>
> Changes since v1:
v2?
> - Fix warning ins dpu_trace.h related to
>dpu_core_irq_unregister_callback event
Any plans to migrate to
On Thu, 3 Mar 2022 at 19:34, Rob Herring wrote:
>
> On Wed, Mar 2, 2022 at 12:01 PM Rob Herring wrote:
> >
> > On Wed, Mar 02, 2022 at 03:40:56PM +1030, Joel Stanley wrote:
> > > Convert the bindings to yaml and add the ast2600 compatible string.
> > >
> > > Signed-off-by: Joel Stanley
> > >
Quoting José Expósito (2022-03-03 18:37:20)
> On Mon, Feb 28, 2022 at 11:24:36PM +, Kieran Bingham wrote:
> > Hi José
> >
> > Quoting José Expósito (2022-02-28 18:39:54)
> > > The function "drm_of_find_panel_or_bridge" has been deprecated in
> > > favor of "devm_drm_of_get_bridge".
> > >
> >
From: Stuart Summers
If RCS is not enumerated, GuC will return invalid parameters.
Make sure we do not send RCS supported when we have not enumerated
it.
Cc: Vinay Belgaumkar
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
1
In the past we've always assumed that an RCS engine is present on every
platform. However now that we have compute engines there may be
platforms that have CCS engines but no RCS, or platforms that are
designed to have both, but have the RCS engine fused off.
Various engine-centric
On 3/3/2022 01:55, Tvrtko Ursulin wrote:
On 02/03/2022 17:55, John Harrison wrote:
I was assuming 2.5s tP is enough and basing all calculation on that.
Heartbeat or timeslicing regardless. I thought we established
neither of us knows how long is enough.
Are you now saying 2.5s is definitely
On Wed, Mar 2, 2022 at 12:01 PM Rob Herring wrote:
>
> On Wed, Mar 02, 2022 at 03:40:56PM +1030, Joel Stanley wrote:
> > Convert the bindings to yaml and add the ast2600 compatible string.
> >
> > Signed-off-by: Joel Stanley
> > ---
> > .../devicetree/bindings/gpu/aspeed,gfx.yaml | 69
From: Rob Clark
Some clever folks figured out a way to use performance counters as a
side-channel[1]. But, other than the special case of using the perf
counters for system profiling, we can reset the counters across context
switches to protect against this.
This series introduces a SYSPROF
Quoting Dmitry Baryshkov (2022-02-21 22:22:46)
> To remove possible confusion between (old) INTF_EDP and newer INTF_DP,
> stop using INTF_EDP in DPU's code. Until the 8x74/8x84 SoCs are
> supported by DPU driver, there is no point in using INTF_EDP.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Quoting Dmitry Baryshkov (2022-02-21 22:22:45)
> DPU driver never supported INTF_EDP, so let's drop the obsolete comment.
> If at some point 8x74/8x84's INTF_EDP is ported to DPU driver,
> corresponding handling will have to be ported too. Until that time, the
> comment serves no purpose.
>
>
On Fri, 4 Mar 2022 at 00:23, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-02-16 20:31:42)
> > This is the second part of
> > https://patchwork.freedesktop.org/series/91631/ reworked and cleaned up.
> >
> > Changes since v1:
>
> v2?
And the series should have been v3. Thanks for
Quoting Dmitry Baryshkov (2022-02-16 21:55:27)
> The only clock for which we set the rate is the "stream_pixel". Rather
> than storing the rate and then setting it by looping over all the
> clocks, set the clock rate directly.
>
> Signed-off-by: Dmitry Baryshkov
[...]
> diff --git
On 3/3/2022 14:34, Matt Roper wrote:
From: Stuart Summers
If RCS is not enumerated, GuC will return invalid parameters.
Make sure we do not send RCS supported when we have not enumerated
it.
Cc: Vinay Belgaumkar
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
Reviewed-by: John
On Mon, Feb 28, 2022 at 11:24:36PM +, Kieran Bingham wrote:
> Hi José
>
> Quoting José Expósito (2022-02-28 18:39:54)
> > The function "drm_of_find_panel_or_bridge" has been deprecated in
> > favor of "devm_drm_of_get_bridge".
> >
> > Switch to the new function and reduce boilerplate.
> >
>
On Thu, Mar 3, 2022 at 12:42 PM Abhinav Kumar wrote:
>
> Hi Rob
>
> On 3/3/2022 11:46 AM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Update headers from mesa commit:
> >
> >commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef
> >Author: Rob Clark
> >AuthorDate: Wed Mar 2 17:11:10
Quoting Dmitry Baryshkov (2022-02-21 22:22:44)
> This enum value does not correspond to any of actual interface types,
> it's not used by the driver, and the value of INTF_WB is greater than
> INTF_TYPE_MAX. Thus this symbol serves no purpose and can be removed.
>
> Signed-off-by: Dmitry Baryshkov
On Thu, Mar 3, 2022 at 12:47 PM Stephen Boyd wrote:
>
> Quoting Rob Clark (2022-03-03 11:46:47)
> > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> > index fde9a29f884e..0ba1dbd4e50f 100644
> > --- a/drivers/gpu/drm/msm/msm_gpu.h
> > +++
Quoting Dmitry Baryshkov (2022-02-21 22:22:43)
> Based on the discussions on the mailing list, document enum
> dpu_intf_type and it's controversial fields: INTF_DP and INTF_EDP.
>
> INTF_EDP is used for older eDP interface found on msm8x74/msm8x84
> INTF_DP is used for both eDP and DP interfaces
We are seeking nominations for candidates for election to the X.org Foundation
Board of Directors. However, as we presently do not have enough nominations to
start the election - the decision has been made to extend the timeline by 2
weeks. Note this is a fairly regular part of the elections
Quoting Dmitry Baryshkov (2022-02-16 21:55:26)
> "ctrl_link" is the clock from DP_CTRL_PM module. The result of setting
> the rate for it would be a call to dev_pm_opp_set_rate(). Instead of
> saving the rate inside struct dss_module_power, call the
> devm_pm_opp_set_rate() directly.
>
>
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat will kick in eventually
and cause a reset of the hung engine.
However, this does not work well in
From: John Harrison
Compute workloads are inherently not pre-emptible for long periods on
current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was disabled. This is undesirable with GuC
submission as it prevents per engine reset of hung contexts. Hence
From: John Harrison
An earlier patch added support for compute engines. However, it missed
enabling the anti-pre-emption w/a for the new engine class. So move
the 'compute capable' flag earlier and use it for the pre-emption w/a
test.
Fixes: c674c5b9342e ("drm/i915/xehp: CCS should use RCS
From: John Harrison
Compute workloads are inherently not pre-emptible on current hardware.
Thus the pre-emption timeout was disabled as a workaround to prevent
unwanted resets. Instead, the hang detection was left to the heartbeat
and its (longer) timeout. This is undesirable with GuC submission
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst case scenario is approximately
110 seconds. Rather than allowing the user to set higher values
Hi,
On Thu, Mar 3, 2022 at 1:40 AM Vinod Polimera wrote:
>
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated
On 2022-03-03 12:25, Gustavo A. R. Silva wrote:
> Fix the following Wstringop-overflow warnings when building with GCC-11:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:493:17: warning:
> ‘dp_decide_lane_settings’ accessing 4 bytes in a region of size 1
>
From: Rob Clark
It was always expected to have a use for this some day, so we left a
placeholder. Now we do. (And I expect another use in the not too
distant future when we start allowing userspace to allocate GPU iova.)
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c |
pass the correct size value computed using the max_order.
[ 68.124177][ T1] UBSAN: shift-out-of-bounds in include/linux/log2.h:67:13
[ 68.125333][ T1] shift exponent 4294967295 is too large for 32-bit type 'long
unsigned int'
[ 68.126563][ T1] CPU: 0 PID: 1 Comm: swapper Not tainted
Quoting Rob Clark (2022-03-03 11:46:47)
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index fde9a29f884e..0ba1dbd4e50f 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -330,6 +337,24 @@ struct msm_file_private {
>
Quoting Dmitry Baryshkov (2022-02-16 20:31:47)
> Remove additional indirection: specify IRQ callbacks and IRQ indices
> directly rather than through the pointer in the irq structure. For each
> IRQ we have a constant IRQ callback. This change simplifies code review
> as the reader no longer needs
Quoting Vinod Polimera (2022-03-03 01:40:01)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated value during the
Quoting Vinod Polimera (2022-03-03 01:40:00)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated value during the
Quoting Rob Clark (2022-03-03 13:47:14)
> On Thu, Mar 3, 2022 at 1:17 PM Rob Clark wrote:
> >
> > On Thu, Mar 3, 2022 at 12:47 PM Stephen Boyd wrote:
> > >
> > > Quoting Rob Clark (2022-03-03 11:46:47)
> > > > +
> > > > + /* then apply new value: */
> > >
> > > It would be safer to swap
From: Akeem G Abodunrin
Starting with DG2, preemption can no longer be controlled using userspace
on a per-context basis. Instead, the hardware only allows us to enable or
disable preemption in a global, system-wide basis. Also, we lose the
ability to specify the preemption granularity (such as
Quoting Dmitry Baryshkov (2022-02-16 20:31:45)
> DPU interrupts code allows multiple callbacks per interrut. In reality
> none of the interrupts is shared between blocks (and will probably never
> be). Drop support for registering multiple callbacks per interrupt to
> simplify interrupt handling
On 2/21/2022 10:22 PM, Dmitry Baryshkov wrote:
Recent dicussion on the mailing list [1], [2] outlined a need to document
which intf type is used for DP and which one is used for eDP interfaces.
This series implements my proposal [3]:
- Keep INTF_EDP reserved for 8x74/8x84
- Use INTF_DP for
On Thu 03 Mar 13:22 PST 2022, Stephen Boyd wrote:
> Quoting Dmitry Baryshkov (2022-02-16 20:31:42)
> > This is the second part of
> > https://patchwork.freedesktop.org/series/91631/ reworked and cleaned up.
> >
> > Changes since v1:
>
> v2?
>
> > - Fix warning ins dpu_trace.h related to
> >
Quoting Vinod Polimera (2022-03-03 01:39:58)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated value during the
Quoting Vinod Polimera (2022-03-03 01:39:59)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated value during the
Quoting Dmitry Baryshkov (2022-02-16 21:55:25)
> DPU driver contains code to parse clock items from device tree into
> special data struct and then enable/disable/set rate for the clocks
> using that data struct. However the DPU driver itself uses only parsing
> and enabling/disabling part (the
Quoting Dmitry Baryshkov (2022-02-16 21:55:29)
> In order to simplify DP code, drop hand-coded loops over clock arrays,
> replacing them with clk_bulk_* functions.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Quoting Dmitry Baryshkov (2022-02-16 21:55:28)
> Inline the dp_power_clk_set_rate() function, replacing it with the call
> to msm_dss_enable_clk().
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Quoting Abhinav Kumar (2022-02-04 13:17:13)
> This series adds support for writeback block on DPU. Writeback
> block is extremely useful to validate boards having no physical displays
> in addition to many other use-cases where we want to get the output
> of the display pipeline to examine whether
Quoting Dmitry Baryshkov (2022-01-19 14:40:02)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/msm_mdss.c
> similarity index 58%
> rename from drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> rename to drivers/gpu/drm/msm/msm_mdss.c
> index 9f5cc7f9e9a9..f5429eb0ae52
Quoting Dmitry Baryshkov (2022-01-19 14:40:05)
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 759076357e0e..f83dca99f03d 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -314,11 +314,11 @@ static const struct
On Thu, 3 Mar 2022 at 14:43, Vinod Polimera wrote:
>
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of
On Thu, Mar 03, 2022 at 09:36:25AM -0500, Theodore Ts'o wrote:
> On Thu, Mar 03, 2022 at 02:23:33PM +0900, Byungchul Park wrote:
> > I totally agree with you. *They aren't really locks but it's just waits
> > and wakeups.* That's exactly why I decided to develop Dept. Dept is not
> > interested in
Hi,
On Tue, Mar 1, 2022 at 6:11 PM Brian Norris wrote:
>
> DP AUX transactions can consist of many short operations. There's no
> need to power things up/down in short intervals.
>
> I pick an arbitrary 100ms; for the systems I'm testing (Rockchip
> RK3399), runtime-PM transitions only take a
Quoting Dmitry Baryshkov (2022-01-19 14:40:03)
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index be06a62d7ccb..f18dfbb614f0 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -1211,19 +1212,32 @@ static int
On Fri, 4 Mar 2022 at 02:56, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-03-03 15:50:50)
> > On Thu, 3 Mar 2022 at 12:40, Vinod Polimera
> > wrote:
> > >
> > > Kernel clock driver assumes that initial rate is the
> > > max rate for that clock and was not allowing it to scale
> > >
From: Rob Clark
Any app controlled perfcntr collection (GL_AMD_performance_monitor, etc)
does not require counters to maintain state across context switches. So
clear them if systemwide profiling is not active.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 29
Since now there is just one mdss subdriver, drop all the indirection,
make msm_mdss struct completely opaque (and defined inside msm_mdss.c)
and call mdss functions directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 29 +++
drivers/gpu/drm/msm/msm_kms.h | 16
Currently the msm platform driver is a multiplex handling several cases:
- headless GPU-only driver,
- MDP4 with flat device nodes,
- MDP5/DPU MDSS with all the nodes being children of MDSS node.
This results in not-so-perfect code, checking the hardware version
(MDP4/MDP5/DPU) in several places,
Let's make the match's data pointer a (sub-)driver's private data. The
only user currently is the msm_drm_init() function, using this data to
select kms_init callback. Pass this callback through the driver's
private data instead.
Signed-off-by: Dmitry Baryshkov
---
MSM DRM driver already allows one to compile out the DP or DSI support.
Add support for disabling other features like MDP4/MDP5/DPU drivers or
direct HDMI output support.
Suggested-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig| 50
On Fri, 4 Mar 2022 at 01:32, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-02-16 21:55:27)
> > The only clock for which we set the rate is the "stream_pixel". Rather
> > than storing the rate and then setting it by looping over all the
> > clocks, set the clock rate directly.
> >
> >
Quoting Dmitry Baryshkov (2022-03-03 20:23:06)
> On Fri, 4 Mar 2022 at 01:32, Stephen Boyd wrote:
> >
> > Quoting Dmitry Baryshkov (2022-02-16 21:55:27)
> > > The only clock for which we set the rate is the "stream_pixel". Rather
> > > than storing the rate and then setting it by looping over all
On Thu, Mar 03, 2022 at 02:37:35PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> An earlier patch added support for compute engines. However, it missed
> enabling the anti-pre-emption w/a for the new engine class. So move
> the 'compute capable' flag earlier and use it for
On Fri, 4 Mar 2022 at 01:54, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-01-19 14:40:03)
> > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> > index be06a62d7ccb..f18dfbb614f0 100644
> > --- a/drivers/gpu/drm/msm/msm_drv.c
> > +++
On Thu, 3 Mar 2022 at 12:40, Vinod Polimera wrote:
>
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated value
v1: https://lore.kernel.org/all/20220302051056.678367-1-j...@jms.id.au/
This series cleans up the bindings for the ASPEED GFX unit.
The old text files are deleted for both the description under gpu, and the
placeholder one under mfd.
The mfd one existed because pinctrl for the 2500 depends on
The example needs updating to match the to be added yaml bindings for
the gfx node.
Signed-off-by: Joel Stanley
---
.../bindings/pinctrl/aspeed,ast2500-pinctrl.yaml | 16
1 file changed, 16 insertions(+)
diff --git
Convert the bindings to yaml and add the ast2600 compatible string.
The legacy mfd description was put in place before the gfx bindings
existed, to document the compatible that is used in the pinctrl
bindings.
Signed-off-by: Joel Stanley
---
.../devicetree/bindings/gpu/aspeed,gfx.yaml | 69
On 3/3/22 13:54, Maxime Ripard wrote:
[...]
Regarding the default value -- there are no in-tree users of this driver yet
(per git grep in current linux-next), do we really care about backward
compatibility in this case?
If it hasn't been in a stable release yet, no. If it did, yes
It was
On Thu, Mar 03, 2022 at 12:38:39PM +, Hyeonggon Yoo wrote:
> On Thu, Mar 03, 2022 at 06:48:24PM +0900, Byungchul Park wrote:
> > On Thu, Mar 03, 2022 at 08:03:21AM +, Hyeonggon Yoo wrote:
> > > On Thu, Mar 03, 2022 at 09:18:13AM +0900, Byungchul Park wrote:
> > > > Hi Hyeonggon,
> > > >
>
From: Rob Clark
It was always expected to have a use for this some day, so we left a
placeholder. Now we do. (And I expect another use in the not too
distant future when we start allowing userspace to allocate GPU iova.)
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c |
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