On Mon, Apr 25, 2022 at 02:12:50PM -0700, Matt Roper wrote:
The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now (although they'll continue to require force_probe until the
usual requirements are met).
Fix spelling typo in comment.
Signed-off-by: pengfuyuan
---
drivers/gpu/drm/arm/malidp_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/malidp_regs.h
b/drivers/gpu/drm/arm/malidp_regs.h
index 514c50dcb74d..3bc16db70ddb 100644
---
While technically Xen dom0 is a virtual machine too, it does have
access to most of the hardware so it doesn't need to be considered a
"passthrough". Commit b818a5d37454 ("drm/amdgpu/gmc: use PCI BARs for
APUs in passthrough") changed how FB is accessed based on passthrough
mode. This breaks
Signed-off-by: oushixiong
---
drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 7bd763361d6e..b7a1e2116e7e 100644
---
Fix spelling typo in comment.
Signed-off-by: pengfuyuan
---
drivers/gpu/drm/arm/malidp_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/malidp_regs.h
b/drivers/gpu/drm/arm/malidp_regs.h
index 514c50dcb74d..59f63cc2b304 100644
---
Signed-off-by: oushixiong
---
drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 7bd763361d6e..b7a1e2116e7e 100644
---
Hi Laurent,
On Do, Apr 21, 2022 at 07:33:18 +0300, Laurent Pinchart wrote:
> On Thu, Apr 21, 2022 at 06:12:59PM +0200, Eugeniu Rosca wrote:
> > Since the meat of the Renesas patch [1]
> > is basically a printk in the interrupt context and an array storing
> > the total number of underruns
The IT6505 is using functions provided by the DRM_DP_HELPER driver.
In order to avoid having the bridge enabled but the helper disabled,
let's add a select in order to be sure that the DP helper functions are
always available.
Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver")
Signed-off-by:
On Tue, Apr 26, 2022 at 05:29:31PM +0200, Neil Armstrong wrote:
> On 26/04/2022 16:15, Fabien Parent wrote:
> > The IT6505 is using functions provided by the DRM_DP_HELPER driver.
> > In order to avoid having the bridge enabled but the helper disabled,
> > let's add a select in order to be sure
On Tue, 26 Apr 2022 21:43:12 -0300
Igor Torrente wrote:
> On 4/26/22 04:09, Pekka Paalanen wrote:
> > On Mon, 25 Apr 2022 21:56:12 -0300
> > Igor Torrente wrote:
> >
> >> Hi Pekka,
> >>
> >> On 4/25/22 04:56, Pekka Paalanen wrote:
> >>> On Sat, 23 Apr 2022 12:12:51 -0300
> >>> Igor
On Tue, 26 Apr 2022 22:22:22 -0300
Igor Torrente wrote:
> On April 26, 2022 10:03:09 PM GMT-03:00, Igor Torrente
> wrote:
> >
> >
> >On 4/25/22 22:54, Igor Torrente wrote:
> >> Hi Pekka,
> >>
> >> On 4/25/22 05:10, Pekka Paalanen wrote:
> >>> On Sat, 23 Apr 2022 15:53:20 -0300
> >>> Igor
drm-misc-fixes-2022-04-27:
drm-misc-fixes for v5.18-rc5:
- Single fix removing applying PHYS_OFFSET twice in sunxi.
The following changes since commit 94f4c4965e5513ba624488f4b601d6b385635aec:
drm/amdgpu: partial revert "remove ctx->lock" v2 (2022-04-21 11:26:20 +0200)
are available in the Git
Am 26.04.22 um 20:50 schrieb Chia-I Wu:
On Tue, Apr 26, 2022 at 11:02 AM Christian König
wrote:
Am 26.04.22 um 19:40 schrieb Chia-I Wu:
[SNIP]
Well I just send a patch to completely remove the trace point.
As I said it absolutely doesn't make sense to use this for
visualization, that's what
Hi Matt,
The proposal looks good to me.
Looking forward to try it on drm-tip.
-Lionel
On 20/04/2022 20:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given kernel?
I assume older kernels are going to reject object creation if we use
this flag?
I didn't plan to use __drm_i915_query_vma_info, but isn't it
inconsistent to select
Well usually we increment the drm minor version when adding some new
flags on amdgpu.
Additional to that just one comment from our experience with that: You
don't just need one flag, but two. The first one is a hint which says
"CPU access needed" and the second is a promise which says "CPU
On Thu, Apr 21, 2022 at 1:54 PM Maxime Ripard wrote:
>
> On Thu, Apr 21, 2022 at 01:15:54PM +0530, Jagan Teki wrote:
> > + Linus
> > + Marek
> > + Laurent
> > + Robert
> >
> > On Thu, Apr 21, 2022 at 4:40 AM Bjorn Andersson
> > wrote:
> > >
> > > Commit '80253168dbfd ("drm: of: Lookup if child
On 27/04/2022 00:12, Kuogee Hsieh wrote:
Current DP driver implementation has adding safe mode done at
dp_hpd_plug_handle() which is expected to be executed under event
thread context.
However there is possible circular locking happen (see blow stack trace)
after edp driver call
On Tue, 26 Apr 2022 21:53:19 -0300
Igor Torrente wrote:
> Hi Pekka,
>
> On 4/21/22 07:58, Pekka Paalanen wrote:
> > On Mon, 4 Apr 2022 17:45:15 -0300
> > Igor Torrente wrote:
> >
> >> Adds this common format to vkms.
> >>
> >> This commit also adds new helper macros to deal with
Disable ABM feature when the system is running on AC mode to get the more
perfect contrast of the display.
v2: remove "UPSTREAM" from the subject.
v3: adv->pm.ac_power updating by amd gpu_acpi_event_handler.
V4: Add the file I lost to fix the build error.
Signed-off-by: Ryan Lin
---
On 20/04/2022 18:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture.
https://bugzilla.kernel.org/show_bug.cgi?id=215892
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Sorry for late reply,
On Thu, 2022-04-14 at 17:13 +0100, Robert Beckett wrote:
>
>
> On 14/04/2022 15:05, Thomas Hellström wrote:
> > On Tue, 2022-04-12 at 15:18 +, Robert Beckett wrote:
> > > stolen/kernel buffers should not be mmapable by userland.
> > > do not provide callbacks to
Tested-by: Kuogee Hsieh
On 4/26/2022 2:21 PM, Abhinav Kumar wrote:
On 4/26/2022 1:52 PM, Doug Anderson wrote:
Hi,
On Tue, Apr 26, 2022 at 1:46 PM Abhinav Kumar
wrote:
On 4/26/2022 1:21 PM, Douglas Anderson wrote:
If we're unable to read the EDID for a display because it's corrupt /
* Passthrough guest's avic pages that can be passed through
- logical id table
- avic backing page
* Passthrough AVIC's mmio range
- nested guest is responsible for marking it RW
in its NPT tables.
* Write track physical id page
- all peer's avic backing pages
This will be used on SVM to reload shadow page of the AVIC physid table
No functional change intended
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm-x86-ops.h | 2 +-
arch/x86/include/asm/kvm_host.h| 3 +--
arch/x86/kvm/vmx/vmx.c | 8
arch/x86/kvm/x86.c
The DRM_DP_AUX_CHARDEV and DRM_DP_CEC Kconfig symbols enable code that use
DP helper functions, that are only present if CONFIG_DRM_DISPLAY_DP_HELPER
is also enabled.
But these don't select the DRM_DISPLAY_DP_HELPER symbol, meaning that it
is possible to enable any of them without
This is V3 of my nested AVIC patches.
I fixed few more bugs, and I also split the cod insto smaller patches.
Review is welcome!
Best regards,
Maxim Levitsky
Maxim Levitsky (19):
KVM: x86: document AVIC/APICv inhibit reasons
KVM: x86: inhibit APICv/AVIC when the guest and/or host
These days there are too many AVIC/APICv inhibit
reasons, and it doesn't hurt to have some documentation
for them.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/include/asm/kvm_host.h
Neither of these settings should be changed by the guest and it is
a burden to support it in the acceleration code, so just inhibit
it instead.
Also add a boolean 'apic_id_changed' to indicate if apic id ever changed.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 3 +++
AVIC is now inhibited if the guest changes apic id, thus remove
that broken code.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index
On 4/27/2022 9:55 AM, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for DG2.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
Implement the shadow physical id table and its
write tracking code which will be soon used for the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 461 +++-
arch/x86/kvm/svm/svm.h | 71 +++
2 files changed, 524 insertions(+), 8
For each vCPU
- store a linked list of all shadow physical id entries
which address it.
- Update those entries when this vCPU is scheduled
in/out
- update this list, when physid tables are modified by
other means (guest write and/or table sync)
To avoid races vs vcpu schedule,
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc:
This allows to enable the write tracking only when KVMGT is
actually used and doesn't carry any penalty otherwise.
Tested by booting a VM with a kvmgt mdev device.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/Kconfig | 3 ---
arch/x86/kvm/mmu/mmu.c | 2 +-
This will be used to enable write tracking from nested AVIC code
and can also be used to enable write tracking in GVT-g module
when it actually uses it as opposed to always enabling it,
when the module is compiled in the kernel.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
This will make the code a bit easier to read when nested AVIC support
is added.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 51 +++--
arch/x86/kvm/svm/svm.h | 14 ++-
2 files changed, 37 insertions(+),
This is a tiny refactoring, and can be useful to check
if a GPA/GFN is within a memslot a bit more cleanly.
Signed-off-by: Maxim Levitsky
---
include/linux/kvm_host.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/kvm_host.h
If a non leaf mmu page is write tracked externally for some reason,
which can in theory happen if it was used for nested avic physid page
before, then this code will enter an endless loop of page faults because
unprotecting the mmu page will not remove write tracking, nor will the
write tracker
This implements a few helpers that help manipulate the AVIC's
physical and logical id table entries.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.h | 45 ++
1 file changed, 45 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.h
This patch adds few tracepoints that will be used
to debug/profile the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/trace.h | 157 ++-
arch/x86/kvm/x86.c | 13
2 files changed, 169 insertions(+), 1 deletion(-)
diff --git
Fix the following -Wstringop-overflow warnings when building with GCC-11:
drivers/gpu/drm/i915/intel_pm.c:3106:9: warning: ‘intel_read_wm_latency’
accessing 16 bytes in a region of size 10 [-Wstringop-overflow=]
3106 | intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
|
This patch implements the doorbell msr emulation
for nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 49 +
arch/x86/kvm/svm/svm.c | 2 ++
arch/x86/kvm/svm/svm.h | 1 +
3 files changed, 52 insertions(+)
diff --git
Hi Yuji,
Thank you for the patch. It's nice to see contributions from Toshiba in
the image acceleration domain :-)
I'll start with a high-level question before diving into detailed
review. Why is this implemented in drivers/soc/ with a custom userspace
API, and not as a V4L2 memory-to-memory
On 4/27/22 04:43, Pekka Paalanen wrote:
On Tue, 26 Apr 2022 22:22:22 -0300
Igor Torrente wrote:
On April 26, 2022 10:03:09 PM GMT-03:00, Igor Torrente
wrote:
On 4/25/22 22:54, Igor Torrente wrote:
Hi Pekka,
On 4/25/22 05:10, Pekka Paalanen wrote:
On Sat, 23 Apr 2022 15:53:20 -0300
An AVIC table invalidation is not supposed to happen often, and can
only happen when the guest does something suspicious such as:
- It places physid page in a memslot that is enabled/disabled and memslot
flushing happens.
- It tries to update apic backing page addresses - guest has no
* SVM_EXIT_AVIC_UNACCELERATED_ACCESS is always forwarded to the L1
* SVM_EXIT_AVIC_INCOMPLETE_IPI is hidden from the guest if:
- is_running was false in shadow physid page because L1's vCPU
was scheduled out - in this case, the vCPU is waken up,
and it will process nested AVIC on
The DRM_DP_AUX_CHARDEV and DRM_DP_CEC boolean Kconfig symbols enable code
that use DP helper functions, exported by the display-helper module.
But these don't select the DRM_DISPLAY_DP_HELPER and DRM_DISPLAY_HELPER
symbols, to make sure that the functions used will be present. This leads
to the
On 4/26/2022 5:26 PM, Daniele Ceraolo Spurio wrote:
The huc_is_authenticated function return is based on our SW tracking of
the HuC auth status. However, around suspend/resume and reset this can
go out of sync with the actual HW state, which is why we use
huc_check_state() to look at the
Tested-by: Kuogee Hsieh
On 4/26/2022 2:17 PM, Doug Anderson wrote:
Hi,
On Tue, Apr 26, 2022 at 2:11 PM Abhinav Kumar wrote:
On 4/26/2022 1:26 PM, Doug Anderson wrote:
Hi,
On Tue, Apr 26, 2022 at 12:20 PM Abhinav Kumar
wrote:
Missed one more comment.
On 4/26/2022 12:16 PM, Abhinav
On 4/27/2022 11:24, Timo Aaltonen wrote:
john.c.harri...@intel.com kirjoitti 27.4.2022 klo 19.55:
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this set includes a revert of that patch before applying
the new
By default, peers of a vCPU, can send it doorbell messages,
only when that vCPU is assigned (loaded) a physical CPU.
However when doorbell messages are not allowed, this causes all of
the vCPU's peers to get VM exits, which is suboptimal when this
vCPU is not halted, and therefore just temporary
This patch enables and exposes to the nested guest
the support for the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 099329711ad13..431281ccc40ef 100644
---
On Wed, Apr 27, 2022 at 5:41 PM Harry Wentland wrote:
>
>
>
> On 2022-04-27 06:52, Pekka Paalanen wrote:
> > Hi Ville and Alex,
> >
> > thanks for the replies. More below.
> >
> > TL;DR:
> >
> > My take-away from this is that I should slam 'max bpc' to the max by
> > default, and offer a knob for
On 4/27/22 22:25, Javier Martinez Canillas wrote:
> The DRM_DP_AUX_CHARDEV and DRM_DP_CEC boolean Kconfig symbols enable code
> that use DP helper functions, exported by the display-helper module.
>
[snip]
> @@ -32,6 +32,8 @@ config DRM_DISPLAY_HDMI_HELPER
> config DRM_DP_AUX_CHARDEV
>
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the
Rather than storing subslice masks internally as u8[] (inside the sseu
structure) and u32 (everywhere else), let's move over to using an
intel_sseu_ss_mask_t typedef compatible with the operations in
linux/bitmap.h. We're soon going to start adding code for a new
platform where subslice masks are
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
This series makes a handful of updates to i915's internal handling of
slice/subslice/EU (SSEU) data to handle recent platforms like Xe_HP in a
more natural manner and to prepare for some additional upcoming
platforms we have in the pipeline (the first of which I'll probably
start sending patches
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated. Given that modern
platforms (gen11 and beyond) are architecturally guaranteed to have
equivalent EU masks
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 85
1 file changed,
Hi Laurent,
Thank you for your comment.
We had never imagined that affine driver can be a V4L2 driver.
Affine is one of the accelerators in Visconti, and some accelerators
receive/yield non-picture data.
Also, as the original accelerator drivers were implemented for kernel 4.19.x,
we were not
Hi Dave, Daniel,
Fixes for 5.18.
The following changes since commit b2d229d4ddb17db541098b83524d901257e93845:
Linux 5.18-rc3 (2022-04-17 13:57:31 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.18-2022-04-27
for you to
++Laurent ,Dmitry, and Abhinav
Hi,
Can you have a look at the private implementation i915 is currently going with
till
we can figure out how to work with drm core .
Regards,
Suraj Kandpal
> A patch series was floated in the drm mailing list which aimed to change the
> drm_connector and
Now that the necessary GuC-based hardware workarounds have landed, we're
finally ready to actually enable compute engines for use by userspace.
All of the "under-the-hood" heavy lifting already landed a while back in
other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE
to the
From: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
We'll be adding a new type of engine soon. Let's document the existing
engine classes first to help make it clear what each type of engine is
used for.
Cc: Andi Shyti
Signed-off-by: Matt Roper
---
include/uapi/drm/i915_drm.h | 53 -
1 file changed, 47
Compute engines have a separate register that the driver should use to
perform MMIO-based TLB invalidation.
Note that the term "context" in this register's bspec description is
used to refer to the engine instance (in the same way "context" is used
on bspec 46167).
Bspec: 43930
Cc: Prathap Kumar
We're now ready to start exposing compute engines to userspace.
v2:
- Move kerneldoc for other engine classes to a separate patch. (Andi)
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Cc: Jordan Justen
Cc: Szymon Morek
UMD (mesa):
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc:
On Wed, Apr 27, 2022 at 03:14:16PM -0700, John Harrison wrote:
On 4/27/2022 11:24, Timo Aaltonen wrote:
john.c.harri...@intel.com kirjoitti 27.4.2022 klo 19.55:
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this
++Laurent ,Dmitry, Abhinav and Rob
> -Original Message-
> From: Kandpal, Suraj
> Sent: Thursday, April 21, 2022 10:38 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com;
> Murthy, Arun R ; Kandpal, Suraj
>
>
++Laurent ,Dmitry, Abhinav and Rob
> Adding support for writeback transcoder to start capturing frames using
> interrupt mechanism
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
>
This series is the AFFINE image processing accelerator driver for Toshiba's ARM
SoC, Visconti[0].
This provides DT binding documentation, device driver, MAINTAINER files.
The second patch "soc: visconti: Add Toshiba Visconti image processing
accelerator common source"
is commonly used among
Adds common operations for image processing accelerator drivers
including dma-buf control and ioctl definitiion
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
v1 -> v2:
- apply checkpatch.pl --strict
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile
Adds the Device Tree binding documentation that allows to describe
the AFFINE image processing accelerator found in Toshiba Visconti SoCs.
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
.../soc/visconti/toshiba,visconti-affine.yaml | 53 +++
1 file changed, 53
On Wed, Apr 13, 2022 at 06:12:59PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer
>
> Instead of relying on it getting pulled in indirectly.
>
> Signed-off-by: Michel Dänzer
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/tiny/bochs.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
On Wed, Apr 27, 2022 at 05:23:22PM +0300, Jani Nikula wrote:
> On Wed, 27 Apr 2022, Daniel Vetter wrote:
> > On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
> >> On Mon, 11 Apr 2022, Alex Deucher wrote:
> >> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede
> >> > wrote:
> >> >>
>
LGTM
Acked-by: Siva Mullati
On 06/04/22 14:48, Vivekanandan, Balasubramani wrote:
> When copying RSA use io memcpy functions if the destination address
> contains a GPU local memory address. Considering even the source
> address can be on local memory, a bounce buffer is used to copy from io
>
On 2022-04-26 22:31, Hangyu Hua wrote:
On 2022/4/26 22:55, Andrey Grodzovsky wrote:
On 2022-04-25 22:54, Hangyu Hua wrote:
On 2022/4/25 23:42, Andrey Grodzovsky wrote:
On 2022-04-25 04:36, Hangyu Hua wrote:
When drm_sched_job_add_dependency() fails, dma_fence_put() will be
called
On Mon, Apr 18, 2022 at 10:18:54PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> On 4/18/22 21:38, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 18.04.22 um 00:37 schrieb Dmitry Osipenko:
> >> Replace drm_gem_shmem locks with the reservation lock to make GEM
> >> lockings more consistent.
> >>
> >>
On Tue, Apr 19, 2022 at 11:40:41PM +0300, Dmitry Osipenko wrote:
> On 4/19/22 10:22, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 18.04.22 um 00:37 schrieb Dmitry Osipenko:
> >> Introduce a common DRM SHMEM shrinker. It allows to reduce code
> >> duplication among DRM drivers that implement theirs
On 2022-04-27 04:08, Ryan Lin wrote:
Disable ABM feature when the system is running on AC mode to get the more
perfect contrast of the display.
v2: remove "UPSTREAM" from the subject.
v3: adv->pm.ac_power updating by amd gpu_acpi_event_handler.
V4: Add the file I lost to fix the build
On Wed, Apr 20, 2022 at 09:24:11AM +0200, Javier Martinez Canillas wrote:
> Learning about the DRM subsystem could be quite overwhelming for newcomers
> but there are lots of useful talks, slides and articles available that can
> help to understand the needed concepts and ease the learning curve.
On Wed, Apr 27, 2022 at 08:55:07AM +0200, Christian König wrote:
> Well usually we increment the drm minor version when adding some new flags
> on amdgpu.
>
> Additional to that just one comment from our experience with that: You don't
> just need one flag, but two. The first one is a hint which
On 2022-04-27 06:52, Pekka Paalanen wrote:
> Hi Ville and Alex,
>
> thanks for the replies. More below.
>
> TL;DR:
>
> My take-away from this is that I should slam 'max bpc' to the max by
> default, and offer a knob for the user in case they want to lower it.
>
>
> On Tue, 26 Apr 2022
On 27/04/2022 07:48, Lionel Landwerlin wrote:
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given kernel?
I assume older kernels are going to reject object creation if we use
this flag?
From some offline discussion with
Hi,
I withdraw this series of patches.
I'm going to submit updated version after applying checkpatch.pl with strict
option.
Best regards,
Yuji
> -Original Message-
> From: Yuji Ishikawa
> Sent: Tuesday, April 19, 2022 4:20 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> ; Sumit Semwal
>
On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
> On Mon, 11 Apr 2022, Alex Deucher wrote:
> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede wrote:
> >>
> >> Hi,
> >>
> >> On 4/8/22 17:11, Alex Deucher wrote:
> >> > On Fri, Apr 8, 2022 at 10:56 AM Hans de Goede
> >> > wrote:
> >>
On Wed, 27 Apr 2022, Daniel Vetter wrote:
> On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
>> On Mon, 11 Apr 2022, Alex Deucher wrote:
>> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede wrote:
>> >>
>> >> Hi,
>> >>
>> >> On 4/8/22 17:11, Alex Deucher wrote:
>> >> > On Fri, Apr 8,
On Tue, Apr 26, 2022 at 01:40:31PM +0530, Jagan Teki wrote:
> On Tue, Apr 26, 2022 at 1:24 PM Paul Kocialkowski
> wrote:
> >
> > Hi,
> >
> > On Thu 21 Apr 22, 10:59, Paul Kocialkowski wrote:
> > > Hi Maxime,
> > >
> > > On Thu 21 Apr 22, 10:23, Maxime Ripard wrote:
> > > > On Thu, Apr 21, 2022 at
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dd36acc87..231b2c6f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2796,12 +2796,14 @@ F:
Adds support to AFFINE image processing accelerator on Toshiba Visconti ARM
SoCs.
This accelerator supoorts affine transform, lens undistortion and LUT transform.
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
v1 -> v2:
- apply checkpatch.pl --strict
- renamed identifiers;
This patch fixes a bug where GEN1 VMs doesn't allow resolutions greater
than 64 MB size (eg 7680x4320). Unnecessary PCI check limits Gen1 VRAM
to legacy PCI BAR size only (ie 64MB). Thus any, resolution requesting
greater then 64MB (eg 7680x4320) would fail. MMIO region assigning this
memory
On Wed, Apr 20, 2022 at 03:50:00PM -0700, Niranjana Vishwanathapura wrote:
> On Thu, Mar 31, 2022 at 01:37:08PM +0200, Daniel Vetter wrote:
> > One thing I've forgotten, since it's only hinted at here: If/when we
> > switch tlb flushing from the current dumb implementation
> > we now have in i915
Since it's inception in 2012 it has been understood that the DRM GEM CMA
helpers do not depend on CMA as the backend allocator. In fact the first
bug fix to ensure the cma-helpers work correctly with an IOMMU backend
appeared in 2014. However currently the documentation for
drm_gem_cma_create()
Give each per-line conversion helper pointers of type void and the
number of pixels in the line. Remove the unused swab parameters.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 87 +
1 file changed, 50 insertions(+), 37 deletions(-)
Provide format-independent conversion helpers for system and I/O
memory. Implement most existing helpers on top of it. The source and
destination formats of each conversion is handled by a per-line
helper that is given to the generic implementation.
Signed-off-by: Thomas Zimmermann
---
Replace the inner loop of drm_fb_swab() with helper functions that
swap the bytes in each pixel. This will allow to share the outer
loop with other conversion helpers.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 60 +
1 file changed, 35
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