TCON TOP mux blocks in R40 are registering clock using
tcon top clock index numbers.
Right now the code is using, real numbers start with 0, but
we have proper macros that defined these name index numbers.
Use the existing macros, instead of real numbers for more
code readability.
TCON LCD0, LCD1 in allwinner R40, are used for managing
LCD interfaces like RGB, LVDS and DSI.
Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
tcon top.
Add support for it, in tcon driver.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
drivers/gpu/drm/sun4i/sun4i_tcon.c | 8
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M2U board.
DSI panel connected via board DSI port with,
- DCDC1 as VCC-DSI supply
- PH18 gpio for lcd enable pin
- PD17 gpio for lcd reset pin
- PD16 gpio for backlight enable pin
Signed-off-by: Jagan Teki
---
Changes for v3:
-
The MIPI DSI controller on Allwinner R40 is similar on
the one on A64 like doesn't associate any DSI_SCLK gating.
So, add R40 compatible and append A64 compatible as fallback.
Signed-off-by: Jagan Teki
---
Changes for v3:
- update the binding in new yaml format
Thierry - I would appreciate feedback from you on this approach!
There is an increasing number of new simple panels.
Common for all simple panels are that they have a
mandatory power-supply and some of them have backlight and / or
an enable gpio.
The binding file to describe these panels adds
Hi Dave and Daniel,
2 fixes, 1 of which is marked for stable.
drm-misc-fixes-2019-12-31:
-sun4i: Fix double-free in connector/encoder cleanup (Stefan)
-malidp: Make vtable static (Ben)
Cc: Ben Dooks
Cc: Stefan Mavrodiev
Cheers, Sean
The following changes since commit
On 2019-12-30 11:00 p.m., Lin, Wayne wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
Make sure to select the correct AIP designation for public emails. See
my email on that from yesterday. :)
>>
>> From: Wentland, Harry
>> Sent: Monday,
https://bugzilla.kernel.org/show_bug.cgi?id=205977
--- Comment #1 from stefansp...@gmail.com ---
Created attachment 286549
--> https://bugzilla.kernel.org/attachment.cgi?id=286549=edit
Testcase: Manually disabling ACG
Manually disabling ACG leads to max. clocks being accepted all the time, but
On Tue, 31 Dec 2019 at 11:23, Artur Świgoń wrote:
> >
> > The order of patches should reflect first of all real dependency.
> > Whether it compiles, works at all and does not break anything. Logical
> > dependency of "when the feature will start working" is
> > irrelevant to DTS because DTS goes
On Mon, 23 Dec 2019, Sam Ravnborg wrote:
> Hi Jani.
>
> On Mon, Dec 23, 2019 at 01:29:19PM +0200, Jani Nikula wrote:
>> On Sat, 21 Dec 2019, Sam Ravnborg wrote:
>> > There are a lot of cases where we have a device * but no drm_device *.
>> > Add drm_dev_* variants of the logging functions to
Am Dienstag, 24. Dezember 2019, 15:38:59 CET schrieb Miquel Raynal:
> Add the PHY which outputs MIPI DSI and LVDS.
>
> Signed-off-by: Miquel Raynal
applied for 5.6 (picked early due to it being shared between lvds and dsi)
Thanks
Heiko
___
Am Dienstag, 31. Dezember 2019, 12:56:14 CET schrieb Heiko Stuebner:
> Am Dienstag, 24. Dezember 2019, 15:38:59 CET schrieb Miquel Raynal:
> > Add the PHY which outputs MIPI DSI and LVDS.
> >
> > Signed-off-by: Miquel Raynal
>
> applied for 5.6 (picked early due to it being shared between lvds
Declare the temp variable as __be16 to address the following sparse
warning:
drivers/gpu/drm/panel/panel-lg-lg4573.c:45:20: warning: incorrect type in
initializer (different base types)
drivers/gpu/drm/panel/panel-lg-lg4573.c:45:20:expected unsigned short
[unsigned] [usertype] temp
False alarm. Since DRM sets normalized ZPOS there should be no gaps
and all should work as expected.
On Mon, Dec 30, 2019 at 1:25 PM Roman Stratiienko
wrote:
>
> Please HOLD this until v3.
> I forgot about blender channel frame coords that updated according to
> zpos and can have gap between
From: Roman Stratiienko
According to DRM documentation the only difference between PRIMARY
and OVERLAY plane is that each CRTC must have PRIMARY plane and
OVERLAY are optional.
Allow PRIMARY plane to have dimension different from full-screen.
Fixes: 90212fffa4fc ("drm/sun4i: Use values
As the if statement only checks for the value of the offset_name
variable, it can be replaced by the more conscise BUG_ON macro for error
reporting.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
Hi,
On Mon, 2019-12-30 at 16:44 +0100, Krzysztof Kozlowski wrote:
> On Fri, Dec 20, 2019 at 12:56:50PM +0100, Artur Świgoń wrote:
> > This patch adds the following properties to the Exynos4412 DT:
> > - exynos,interconnect-parent-node: to declare connections between
> > nodes in order to
Please HOLD this until v3.
I forgot about blender channel frame coords that updated according to
zpos and can have gap between channels.
I will also try to simplify this patch.
On Sun, Dec 29, 2019 at 6:28 PM wrote:
>
> From: Roman Stratiienko
>
> To set blending channel order register software
kfree() was called for the same variable twice within an if branch.
Fix it by deleting a duplicate function call.
Fixes: 29cd13cfd762 ("drm/v3d: Fix memory leak in v3d_submit_cl_ioctl")
Signed-off-by: yu kuai
---
drivers/gpu/drm/v3d/v3d_gem.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Roman Stratiienko
DE3.0 VI layers supports plane-global alpha channel.
DE2.0 FCC block have GLOBAL_ALPHA register that can be used as alpha source
for blender.
Add alpha property to the DRM plane and connect it to the
corresponding registers in the mixer.
Signed-off-by: Roman Stratiienko
Hi tiantao,
Thanks for the patches.
I see you sent two patches about resolution. Could you just send them as a
series?
Xinliang
On Sat, 28 Dec 2019 at 08:59, Tian Tao wrote:
> In the previous version, the callback function mode_valid of
> drm_connector_helper_funcs directly returned MODE_OK.
From: Roman Stratiienko
DE2.0 and DE3.0 UI layers supports plane-global alpha channel.
Add alpha property to the DRM plane and connect it to the
corresponding registers in mixer.
Signed-off-by: Roman Stratiienko
---
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 29 ++
since we can get the BO from drm_fb rather than hibmc_fb,do not need
the hibmc_fb.so we delete the local variable hibmc_fb.
Signed-off-by: Tian Tao
Signed-off-by: Gong junjie
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
match_string() returns the array index of a matching string.
Use it instead of the open-coded implementation.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git
From: Roman Stratiienko
To set blending channel order register software needs to know state and
position of each channel, which impossible at plane commit stage.
Move this procedure to atomic_flush stage, where all necessary information
is available.
Fixes: f88c5ee77496 ("drm/sun4i: Implement
Since the introduction of commit 2d99ced787e3 ("drm/msm: async commit
support"), command-mode panels began throwing the following errors:
msm fd90.mdss: pp done time out, lm=0
Let's fix this by enabling the autorefresh feature that's available in
the MDP starting at version 1.0. This
From: Jitao Shi
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
Reviewed-by: Daniel Kurtz
[uli: followed API changes, removed FW update feature]
Signed-off-by: Ulrich Hecht
Signed-off-by: Enric Balletbo i Serra
Tested-by: Hsin-Yi Wang
Since the introduction of commit 2d99ced787e3 ("drm/msm: async commit
support"), command-mode panels began throwing the following errors:
msm fd90.mdss: pp done time out, lm=0
Let's fix this by enabling the autorefresh feature that's available in
the MDP starting at version 1.0. This
tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0,
tcon-ch1 which are referring tcon_top clocks via index
numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1
respectively.
Use the macro in place of index numbers, for more code
readability.
Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu
Add MIPI DSI pipeline for Allwinner R40.
Unlike conventional Display pipeline in allwinner, R40 have
TCON TCOP which would interact various block like muxes,
tcon lcd, tcon_tv for better pipeline fitting.
For MIPI DSI pipeline, we have to configure the tcon_lcd0
block which would interact with
The MIPI DSI PHY controller on Allwinner R40 is similar
on the one on A31.
Add R40 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
---
Changes for v3:
- update the binding in new yaml format
.../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 1 +
1
TCON TOP is processing clock gates and reset control for
TV0, TV1 and DSI channels during bind and release the same
during unbind component ops.
The usual DSI initialization would setup all controller
clocks along with DPHY clocking during probe.
Since the actual clock gates (along with DSI
This is v3 version for supporting MIPI-DSI on Allwinner R40 from
initial version[1].
The controller look similar like, Allwinner A64 but with associated
R40 TCON TOP for DSI pipeline.
Changes for v3:
- collect Rob, Chen-Yu r-b, a-b tags
- move tcon top reset control methods into probe
- rebase
Like TCON TV0, TV1 allwinner R40 has TCON LCD0, LCD1 which
are managed via TCON TOP.
Add tcon lcd compatible R40, the same compatible can handle
TCON LCD0, LCD1.
Signed-off-by: Jagan Teki
Acked-by: Chen-Yu Tsai
Reviewed-by: Rob Herring
---
Changes for v3:
- none
On 2019-11-17 12:22 p.m., Aditya Pakki wrote:
> program_hpd_filter() currently fails to check for the errors
> returned in construct(). This patch returns error in
> case of failure.
>
> Signed-off-by: Aditya Pakki
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
> 1 file changed,
On Mon, Dec 30, 2019 at 2:41 PM Wambui Karuga wrote:
>
> As the if statement only checks for the value of the offset_name
> variable, it can be replaced by the more conscise BUG_ON macro for error
> reporting.
>
> Signed-off-by: Wambui Karuga
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5
On 2019-12-31 2:17 pm, Martin Blumenstingl wrote:
Hi Robin,
On Mon, Dec 30, 2019 at 1:47 AM Robin Murphy wrote:
On 2019-12-29 11:19 pm, Martin Blumenstingl wrote:
Hi Robin,
On Sun, Dec 29, 2019 at 11:58 PM Robin Murphy wrote:
Hi Martin,
On 2019-12-27 5:37 pm, Martin Blumenstingl wrote:
On Tue, Dec 31, 2019 at 6:21 AM Sam Ravnborg wrote:
>
> Thierry - I would appreciate feedback from you on this approach!
For the record, I'm in favor of this.
>
> There is an increasing number of new simple panels.
> Common for all simple panels are that they have a
> mandatory power-supply and
On Thu, Dec 19, 2019 at 1:47 AM Maxime Ripard wrote:
>
> The Allwinner SoCs have a display engine composed of several controllers
> assembled differently depending on the SoC, the number and type of output
> they have, and the additional features they provide. A number of those are
> supported in
On Tue, Dec 31, 2019 at 08:18:01AM +0100, Artur Świgoń wrote:
> Hi,
>
> On Mon, 2019-12-30 at 16:44 +0100, Krzysztof Kozlowski wrote:
> > On Fri, Dec 20, 2019 at 12:56:50PM +0100, Artur Świgoń wrote:
> > > This patch adds the following properties to the Exynos4412 DT:
> > > -
Add the three new pll config for corresponding resolution 1440x900 and
1600x900, 640x480 for hibmc
Signed-off-by: Tian Tao
Signed-off-by: Gong junjie
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 3 +++
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 2 ++
2 files changed, 5
From: Roman Stratiienko
At system start blink of u-boot ghost framebuffer can be observed.
Fix it.
Fixes: 9d75b8c0b999 ("drm/sun4i: add support for Allwinner DE2 mixers")
Signed-off-by: Roman Stratiienko
Reviewed-by: Jernej Skrabec
---
v2:
- Picked 'Reviewed-by' line
- Added 'Fixes' line
---
Hi Daniel:
Thanks you very much ,I will follow your suggestion to split this to
three patches.
Best
在 2019/12/30 18:23, Daniel Stone 写道:
Hi Tian,
On Sat, 28 Dec 2019 at 01:14, Tian Tao wrote:
@@ -118,11 +119,9 @@ static void hibmc_plane_atomic_update(struct drm_plane
*plane,
From: Jitao Shi
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
Signed-off-by: Ulrich Hecht
Signed-off-by: Enric Balletbo i Serra
---
I maintained the ack from Rob Herring and the review
Hi all,
This is another version of the driver. Note that the driver changed
significally and is a more simply because now is using the panel_bridge
helpers. Apart from this, I addressed the comments from Maxime, Laurent
and Ezequiel.
This bridge is required to have the embedded display working
From: Roman Stratiienko
Create callback to update engine's registers on mode change.
Signed-off-by: Roman Stratiienko
---
v2:
- Split commit in 2 parts.
- Add description to mode_set callback
- Dropped 1 line from sun4i_crtc_mode_set_nofb()
- Add struct drm_display_mode declaration (fix build
Hi Robin,
On Sun, Dec 29, 2019 at 11:58 PM Robin Murphy wrote:
>
> Hi Martin,
>
> On 2019-12-27 5:37 pm, Martin Blumenstingl wrote:
> > Most platforms with a Mali-400 or Mali-450 GPU also have support for
> > changing the GPU clock frequency. Add devfreq support so the GPU clock
> > rate is
Hi,
On Tue, 2019-12-24 at 13:56 +0900, Inki Dae wrote:
> Hi,
>
> 19. 12. 20. 오후 8:56에 Artur Świgoń 이(가) 쓴 글:
> > From: Marek Szyprowski
> >
> > This patch adds interconnect support to exynos-mixer. The mixer works
> > the same as before when CONFIG_INTERCONNECT is 'n'.
> >
> >
The Rockship DRM GEM code uses vmap()/vunmap() so vmalloc header must be
included to avoid warnings like (on IA64, compile tested):
drivers/gpu/drm/rockchip/rockchip_drm_gem.c: In function
‘rockchip_gem_alloc_iommu’:
drivers/gpu/drm/rockchip/rockchip_drm_gem.c:134:20: error:
On Tue, Dec 31, 2019 at 10:41:47AM +0100, Artur Świgoń wrote:
> On Tue, 2019-12-31 at 10:22 +0100, Krzysztof Kozlowski wrote:
> > On Tue, Dec 31, 2019 at 08:18:01AM +0100, Artur Świgoń wrote:
> > > Hi,
> > >
> > > On Mon, 2019-12-30 at 16:44 +0100, Krzysztof Kozlowski wrote:
> > > > On Fri, Dec
Hi Qiang,
On Tue, Dec 31, 2019 at 3:54 AM Qiang Yu wrote:
[...]
> > diff --git a/drivers/gpu/drm/lima/lima_sched.c
> > b/drivers/gpu/drm/lima/lima_sched.c
> > index f522c5f99729..851c496a168b 100644
> > --- a/drivers/gpu/drm/lima/lima_sched.c
> > +++ b/drivers/gpu/drm/lima/lima_sched.c
> > @@
Hi Robin,
On Mon, Dec 30, 2019 at 1:47 AM Robin Murphy wrote:
>
> On 2019-12-29 11:19 pm, Martin Blumenstingl wrote:
> > Hi Robin,
> >
> > On Sun, Dec 29, 2019 at 11:58 PM Robin Murphy wrote:
> >>
> >> Hi Martin,
> >>
> >> On 2019-12-27 5:37 pm, Martin Blumenstingl wrote:
> >>> Most platforms
Hi Heiko,
Heiko Stuebner wrote on Tue, 31 Dec 2019 13:14:02
+0100:
> Am Dienstag, 31. Dezember 2019, 12:56:14 CET schrieb Heiko Stuebner:
> > Am Dienstag, 24. Dezember 2019, 15:38:59 CET schrieb Miquel Raynal:
> > > Add the PHY which outputs MIPI DSI and LVDS.
> > >
> > > Signed-off-by:
On Tue, 2019-12-31 at 10:22 +0100, Krzysztof Kozlowski wrote:
> On Tue, Dec 31, 2019 at 08:18:01AM +0100, Artur Świgoń wrote:
> > Hi,
> >
> > On Mon, 2019-12-30 at 16:44 +0100, Krzysztof Kozlowski wrote:
> > > On Fri, Dec 20, 2019 at 12:56:50PM +0100, Artur Świgoń wrote:
> > > > This patch adds
On Tue, 2019-12-31 at 11:02 +0100, Krzysztof Kozlowski wrote:
> On Tue, Dec 31, 2019 at 10:41:47AM +0100, Artur Świgoń wrote:
> > On Tue, 2019-12-31 at 10:22 +0100, Krzysztof Kozlowski wrote:
> > > On Tue, Dec 31, 2019 at 08:18:01AM +0100, Artur Świgoń wrote:
> > > > Hi,
> > > >
> > > > On Mon,
Hi!
Sorry that I missed few details in first review. Please take a look below.
Dne nedelja, 29. december 2019 ob 17:28:27 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> According to DRM documentation the only difference between PRIMARY
> and OVERLAY plane
On Tue, 2019-12-31 at 11:38 +0100, Krzysztof Kozlowski wrote:
> On Tue, 31 Dec 2019 at 11:23, Artur Świgoń wrote:
> > >
> > > The order of patches should reflect first of all real dependency.
> > > Whether it compiles, works at all and does not break anything. Logical
> > > dependency of "when
The local variable `pclks` is defined and set but not used and can
therefore be removed.
Issue found by coccinelle.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/nouveau/dispnv04/arb.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
Hi!
Dne ponedeljek, 30. december 2019 ob 19:08:41 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> DE2.0 and DE3.0 UI layers supports plane-global alpha channel.
> Add alpha property to the DRM plane and connect it to the
> corresponding registers in mixer.
>
Explicitly declare constants are unsigned long to address the following
sparse warnings:
warning: constant is so big it is long
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c | 2 +-
Hi!
Dne nedelja, 29. december 2019 ob 17:28:26 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> Create callback to update engine's registers on mode change.
>
> Signed-off-by: Roman Stratiienko
Reviewed-by: Jernej Skrabec
Best regards,
Jernej
> ---
> v2:
From: Dhinakaran Pandiyan
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Mika Kahola
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Imre Deak
Reviewed-by: Mika Kahola
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
v2: Update code comment describing the color plane order for YUV
semiplanar formats.
Cc:
Probably want ULL for 32-bit arches to be correct here too.
On Tue, Dec 31, 2019 at 3:53 PM Wambui Karuga wrote:
>
> Explicitly declare constants are unsigned long to address the following
> sparse warnings:
> warning: constant is so big it is long
>
> Signed-off-by: Wambui Karuga
> ---
>
Hi Robin,
On Tue, Dec 31, 2019 at 5:40 PM Robin Murphy wrote:
>
> On 2019-12-31 2:17 pm, Martin Blumenstingl wrote:
> > Hi Robin,
> >
> > On Mon, Dec 30, 2019 at 1:47 AM Robin Murphy wrote:
> >>
> >> On 2019-12-29 11:19 pm, Martin Blumenstingl wrote:
> >>> Hi Robin,
> >>>
> >>> On Sun, Dec 29,
Hi!
Dne ponedeljek, 30. december 2019 ob 19:08:42 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> DE3.0 VI layers supports plane-global alpha channel.
> DE2.0 FCC block have GLOBAL_ALPHA register that can be used as alpha source
> for blender.
>
> Add alpha
Hi!
Dne nedelja, 29. december 2019 ob 17:28:25 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> To set blending channel order register software needs to know state and
> position of each channel, which impossible at plane commit stage.
>
> Move this procedure
Replace the use of 0 in the pointer assignment with NULL to address the
following sparse warning:
drivers/gpu/drm/nouveau/nouveau_hwmon.c:744:29: warning: Using plain integer as
NULL pointer
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/nouveau/nouveau_hwmon.c | 2 +-
1 file changed, 1
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