V3:
(1) Reset QuestionStoredInBitField to FALSE at end opcode(EFI_IFR_END_OP)
(2) Fix typo and format issues(line alignment for debug print message
and value assignment...)
V2:
(1)Remove the VarOffsetBitLevel/StorageWidthBitLevel to reduce the final
VarCheckBinSize and update the implementation
Reviewed-by: Star Zeng
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Dandan Bi
Sent: Sunday, November 5, 2017 6:06 PM
To: edk2-devel@lists.01.org
Cc: Gao, Liming ; Dong, Eric ;
The code logic is good. :) Below are my some minor comments.
1. Fix the typo 'form' to 'from' in "// Get the value form the bit field.".
2. Remove one extra whitespace in "if (StoredInBitField) {" to "if
(StoredInBitField) {".
3. Make the assignment in ParseHiiQuestionNumeric()and etc to be
Reviewed-by: Liming Gao
>-Original Message-
>From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
>Sent: Friday, November 03, 2017 7:34 PM
>To: edk2-devel@lists.01.org; leif.lindh...@linaro.org; ler...@redhat.com;
>Gao, Liming
>Cc: Ard
1) Yes, multiple APs may get exception at same time. BSP can send startup
all APs.
2) Yes, I think we need get clear on how we support PEI in the future.
If we use same API but with different behavior, people may get confused. �C
That is my concern.
Thank you
Yao Jiewen
From:
Jiewen,
For 1), this is good question for both global variable solution and new API
solution.
My suggestion is only to use one global stack for BSP, since only BSP is
support before CpuDxe produced Cpu MP service Protocol.
And in InitializeCpuInterruptHandlers() (consumed by CpuDxe) to register
Jiwen,
For 1), the stack is used for exception only. Is there any chance that the same
exception is triggered by both BSP and AP at the same time?
For 2), separate stack is used mainly for Stack Guard feature which is
supported only by DXE (because it needs paging to work). I think we don’t
Jian,
In EDKII, DS == SS on most of cases. I don’t think there is any issue to use
data range for stack.
Jeff
From: Wang, Jian J
Sent: Monday, November 6, 2017 8:30:29 AM
To: Fan Jeff; Yao, Jiewen; Kinney, Michael D;
I think we need consider 2 additional things:
1) how to support different stack for ap?
2) how to support pei phase, when the global variable is read only?
thank you!
Yao, Jiewen
在 2017年11月6日,上午8:30,Wang, Jian J
> 写道:
Jeff,
That’s a good
Hi, Laurie:
Got it!
Thanks a lot!
I just wanted to revise the delay for the shell before executing startup.nsh.
Best wishes,
-邮件原件-
发件人: Jarlstrom, Laurie [mailto:laurie.jarlst...@intel.com]
发送时间: 2017年11月4日 4:54
收件人: Jarlstrom, Laurie ; jim.dai...@dell.com;
Reviewed-by: Hao Wu
Best Regards,
Hao Wu
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Ard
> Biesheuvel
> Sent: Sunday, November 05, 2017 5:31 PM
> To: edk2-devel@lists.01.org
> Cc: Tian, Feng; Dong, Eric; Zeng, Star;
Jim,
RellocatePool() will free old buffer but AllocateCopyPool() will not. So not
all cases in which they can be replaced for each other.
Thanks,
Jian
> -Original Message-
> From: jim.dai...@dell.com [mailto:jim.dai...@dell.com]
> Sent: Friday, November 03, 2017 7:44 PM
> To: Ni, Ruiyu
Star,
Thanks for the comments. It's a good suggestion. I didn't know ReallocatePool()
can do that.
Thanks
Jian
> -Original Message-
> From: Zeng, Star
> Sent: Friday, November 03, 2017 5:14 PM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Dong, Eric
Ruiyu,
Thanks for the comments.
> -Original Message-
> From: Ni, Ruiyu
> Sent: Friday, November 03, 2017 4:23 PM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Carsey, Jaben ; Bi, Dandan
> Subject: RE: [PATCH 2/3]
Jeff,
That’s a good suggestion. Do you know if there’s any pitfall in using data
segment memory as stack?
Thanks,
Jian
From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Friday, November 03, 2017 4:59 PM
To: Yao, Jiewen ; Kinney, Michael D
> On 5 Nov 2017, at 16:52, Ard Biesheuvel wrote:
>
> This library, which is intended to encapsulate the hardware specifics
> of the ARM PL031 RTC, also implements its own input validation routines,
> and even makes a feeble attempt at timezone and DST handling.
>
>
This library, which is intended to encapsulate the hardware specifics
of the ARM PL031 RTC, also implements its own input validation routines,
and even makes a feeble attempt at timezone and DST handling.
The input validation belongs in the core driver, and has been introduced
there, so we can
RealTimeClockRuntimeDxe defers the hardware/platform specific handling
of reading/setting the hardware clock to RealTimeClockLib, but for
unknown reasons, it also defers common functionality such as input
validation and recording the timezone and DST settings (which are
informational only and not
On 5 November 2017 at 16:27, Ard Biesheuvel wrote:
> On 5 November 2017 at 05:52, Leif Lindholm wrote:
>> On Fri, Nov 03, 2017 at 11:33:52AM +, Ard Biesheuvel wrote:
>>> DEBUG builds of PEI code will print a diagnostic message regarding
On 5 November 2017 at 05:52, Leif Lindholm wrote:
> On Fri, Nov 03, 2017 at 11:33:52AM +, Ard Biesheuvel wrote:
>> DEBUG builds of PEI code will print a diagnostic message regarding
>> the utilization of temporary RAM before switching to permanent RAM.
>> For
On 5 November 2017 at 10:05, Ard Biesheuvel wrote:
> On 5 November 2017 at 05:38, Leif Lindholm wrote:
>> On Wed, Nov 01, 2017 at 01:11:44PM +, Ard Biesheuvel wrote:
>>> Introduce a PPI counterpart of the existing 'embedded GPIO' protocol,
This patch applies necessary modifications, which allow to use
MvSpiFlash driver in variable support as a runtime service.
Its type is modified to DXE_RUNTIME_DRIVER, as well as
an event is created, which converts the pointers to the
SpiMasterProtocol and its routines.
Contributed-under:
This patch applies necessary modifications, which allow to use
MvSpiDxe driver in variable support as a runtime service.
Its type is modified to DXE_RUNTIME_DRIVER, as well as
a new callback is introduced as a part of the SpiMasterProtocol.
It is supposed to configure the memory space for mmio
Hi,
Basing on the latest SPI improvements, I submit the variable
support for the Marvell platforms. It relies on a memory mapped
SPI read access, configured in ARM-TF. The new driver (MvFvbDxe)
uses the Marvell SPI protocols, thanks to which it is ready to work
with different host controllers and
MvFvbDxe driver introduces non-volatile EFI variable support
for Armada platforms. It relies on memory-mapped SPI read access.
Implementation of EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
is done with using existing Marvell SPI infrastructure
(SpiMasterProtocol and SpiFlashProtocol), thanks to which
this
Wire up the non-volatile EFI variable store support, by switching from
the emulation driver to the real one. Define default values for
memory mapped SPI access, which must be configured by the early
firmware. In order to ensure proper execution, configure initialization
order with Depex entries.
V2:
(1)Remove the VarOffsetBitLevel/StorageWidthBitLevel to reduce the final
VarCheckBinSize and update the implementation accordingly.
(2)Update the VAR_CHECK_HII_REVISION
(3)Refine the Debug message and function comments,like update oneof",
"checkbox", "numeric" to "OneOf", "CheckBox",
In patch 2, we will introduce DEBUG_INFO in VarCheckHiiLib,in order to keep
consistence, replace all EFI_D_INFO with DEBUG_INFO firstly in this pacth.
Cc: Star Zeng
Cc: Eric Dong
Cc: Liming Gao
Contributed-under: TianoCore
V2:
Patch 1: Replace EFI_D_INFO with DEBUG_INFO in VarCheckHiiLib.
Patch 2:
(1)Remove the VarOffsetBitLevel/StorageWidthBitLevel to reduce the final
VarCheckBinSize and update the implementation accordingly.
(2)UPdate the VAR_CHECK_HII_REVISION
(3)Refine the Debug message and function
On 5 November 2017 at 05:38, Leif Lindholm wrote:
> On Wed, Nov 01, 2017 at 01:11:44PM +, Ard Biesheuvel wrote:
>> Introduce a PPI counterpart of the existing 'embedded GPIO' protocol,
>> so we can manipulate GPIOs from PEI modules. This allows things like
>> setting
Currently, we complete a synchronous operation without unmapping the
DMA mappings, and free the pages using FreePages () rather than calling
EFI_PCI_IO_PROTOCOL::FreeBuffer. This is simply incorrecnt, but it also
breaks non-coherent DMA as well as DMA protection and/or memory encryption
so let's
Hi Leif,
2017-11-05 7:13 GMT+01:00 Leif Lindholm :
> On Fri, Nov 03, 2017 at 06:57:09PM +0100, Marcin Wojtas wrote:
>> Hi,
>>
>> I submit corrected version of the Armada SPI improvements
>> after the first round of review. There were no significant changes
>> comparing
On Fri, Nov 03, 2017 at 06:57:09PM +0100, Marcin Wojtas wrote:
> Hi,
>
> I submit corrected version of the Armada SPI improvements
> after the first round of review. There were no significant changes
> comparing to v1, please check the changelog below for the details.
>
> Patches are available
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