The following series adds ARM compilation support for the VS2017 toolchain.
* PATCH 1 targets the disabling of VS Level 4 warnings. The warnings we
chose to remove are the ones that were seen generated more than 5 times,
during the compilation of a QEMU firmware.
* PATCH 2 adds a NULL handler
Reviewed-by: Chasel Chiu
-Original Message-
From: Zeng, Star
Sent: Monday, December 4, 2017 6:01 PM
To: edk2-devel@lists.01.org
Cc: Zeng, Star ; Yao, Jiewen ; Chiu,
Chasel ; Chiang, Dakota
Mike,
In that case - do you think it should be added to MdeModulePkg?
Should it be implemented simply as a wrapper on IoLib (depending on
it)?
/
Leif
On Fri, Dec 01, 2017 at 10:41:26PM +, Kinney, Michael D wrote:
> Udit,
>
> I agree with your concern.
>
> I am in favor of adding new
Sort and merge memory resource entries to handle the case that
the memory resource HOBs are reported differently between
BOOT_ON_FLASH_UPDATE boot mode and normal boot mode, and the
capsule buffer from UpdateCapsule at normal boot sits across
two memory resource descriptors at BOOT_ON_FLASH_UPDATE
That means we can't share page table pool between DxeIpl and CpuDxe. If this is
acceptable, I can remove them.
> -Original Message-
> From: Zeng, Star
> Sent: Monday, December 04, 2017 5:11 PM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Yao, Jiewen
Recommend to not introduce the new header file and PCDs as new interfaces, but
handle the page table pool separately in DxeIpl and CpuDxe.
Thanks,
Star
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jian J
Wang
Sent: Monday, December 4, 2017
> v2:
>newly added
This file is added to definition of gPageTablePoolGuid. In addition,
following structure type is defined to describe the page table pool
information which can be used by different drivers to allocate memory
for new page tables. It's supposed to be at the start address of
> v2:
>Introduce page table pool to ease the page table memory allocation and
>protection, which replaces the direct calling of AllocatePages().
This patch will set the memory pages used for page table as read-only
memory after the paging is setup. CR0.WP must set to let it take into
> v2:
> newly added
PcdPageTablePoolUnitSize is used to specify the smallest size of memory pool
reserved for page table.
PcdPageTablePoolAlignment is used to specify the alignment of the memory pool
reserved for page table.
gPageTablePoolGuid is used to identify the memory pool used for page
> v2 changes:
> a. Enable protection on any newly added page table after DxeIpl.
> b. Introduce page table pool concept to make page table allocation
> and protection easier and error free.
Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe.
But the memory pages
> v2:
>Use the page table pool to allocate new page tables and save code
>to enable protection for them separately.
One of the functionalities of CpuDxe is to update memory paging attributes.
If page table protection is applied, it must be disabled temporarily before
any attributes update
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