Hi Mike,
Processor trace feature need to get three inputs from end user. 1.
Enabe/disable, 2. Memory size, 3, Output scheme.
It will have three menus in UI to let end user to select. I want the default
value for all three menus are disabled, so I add invalid or disable for both
PCDs. Maybe I
Eric,
For a setup page, the scheme can be greyed out or
hidden if the feature is disabled. If the feature
is disabled, it does not make sense to allow the
user to set the memory size or the scheme.
Mike
> -Original Message-
> From: Dong, Eric
> Sent: Wednesday, August 16, 2017 11:48
When update MSR values, current code use BITxx to modify the MSR values. Enhance
the code to use corresponding MSR's data structures to make it more user
friendly.
Cc: Michael Kinney
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution
Hi Eric,
I recommend that PROC_TRACE_TOPA_ENTRY be added to
UefiCpuPkg\Include\Register\ArchitecturalMsr.h after
MSR_IA32_RTIT_CTL_REGISTER that contains the TOPA
enable bit.
How is the value of MAX_TOPA_ENTRY_COUNT determined?
If that value of 2 is from the SDM, we may want to
add this define
Thanks for the explanation.
Yes, I agree we need resolve the build issue.
I do not suggest to remove the API in SecFspSecPlatformLibNull, because we need
provide a good sample to real FSP implementation.
Can we add empty symbol in FspApiEntryM.nasm and FspApiEntryS.nasm?
Thank you
Yao Jiewen
Yes. This way does work. We will update the patch for it.
From: Yao, Jiewen
Sent: Thursday, August 17, 2017 3:53 PM
To: Gao, Liming ; Song, BinX ;
edk2-devel@lists.01.org
Subject: RE: [PATCH] IntelFsp2Pkg: Delete useless external TempRamInitApi API
On Thu, Aug 17, 2017 at 01:47:59AM +0200, Laszlo Ersek wrote:
> On 08/17/17 00:37, Jordan Justen wrote:
> > On 2017-08-16 12:23:49, Leif Lindholm wrote:
>
> [snip]
>
> >> - the value proposition
> >> for Linaro is that having maintainer parity ArmVirtPkg/OvmfPkg
> >> simplifies the task of
Mike,
The PROC_TRACE_TOPA_ENTRY definition has a little difference with the spec
definition, as I have raised in the comments for "Address" field.
///
/// [Bit 12:63] Output Region Base Physical Address.
/// ATTENTION: The size of the address field is determined by the
Adding Ray
On 08/17/17 06:50, Eric Song wrote:
> Hi, experts
> If there is 2 root bridges under 1 host bridge on the PCI hierarchy,
> whether EDK2 Pci bus driver can support it ? the answer is YES, but
> some confused things in it.
>
> 1) On BDS phase, ConnectController is called for every
On 08/16/17 01:10, Jordan Justen wrote:
> Reviewed-by: Jordan Justen
Thank you, pushed as commit ca56256d5e0b.
Laszlo
> On 2017-08-15 10:09:14, Laszlo Ersek wrote:
>> When UefiCpuPkg/MpInitLib is built for X64 with gcc-7, using the DEBUG
>> build target and the GCC5
Hello,
Do anyone know uefi application that can simulator multi processor dispatch
logic in OS ?
UEFI defines EFI_MP_SERVICES_PROTOCOL, usually bios use this protocol to do
BSP and AP initlizaition. StartupAllAPs is called to run the same logic
function.
Any EFI application can divide
Eric,
Firstly, PciBus driver can support single-segment-multiple-rootbridge system or
multiple-segment-multiple-rootbridge very well. (I agree the enumeration logic
confuses you.)
Take a platform containing 2 root bridges for example, your understanding
is correct. PciBus does the full
Mike,
My reason to defined disable options for memory size and output scheme is I can
use them as my default policy(all in disable status). If not define disable
options, I don't know which default value are better than others. Also disable
options also defined clearly invalid tag and valuable
Hi, Laszlo
Many thanks for rapidly reply.
Your analyze is very clear. But while the PciBusDxe driver is binding a
root bridge, why the PciBusDxe driver do host bridge enumeration. It is
illogical.
Even though it maybe has no side effect, it is confused for users.
Thanks
I believe what you want is a multi-threading capable tiny OS.
I don't know a real project for your purpose.
But I guess there should be plenty of such projects there, just need porting
effort.
Thanks/Ray
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On
On 08/17/17 03:02, Zeng, Star wrote:
> Very good commit log, history information and code change. :)
>
> Reviewed-by: Star Zeng
Thank you all for the comments; patch pushed as commit 5f0f5e90ae8c.
Cheers,
Laszlo
> -Original Message-
> From: Laszlo Ersek
The ArmPkg implementation of DmaLib uses double buffering to ensure
that any attempt to perform non-coherent DMA on unaligned buffers cannot
corrupt adjacent unrelated data which happens to share cachelines with
the data we are exchanging with the device.
Such corruption can only occur on bus
On 17 August 2017 at 13:25, Ard Biesheuvel wrote:
> The ArmPkg implementation of DmaLib uses double buffering to ensure
> that any attempt to perform non-coherent DMA on unaligned buffers cannot
> corrupt adjacent unrelated data which happens to share cachelines with
>
Hi, Ray
Thank you very much for explanations.
I agree with your summary, and I also have tested it.
But I can't found Pci Io handle is created when a light enumeration.
So the sequence is as follows:
1) 1st root bridge handler will trigger Pci bus start()
On 08/17/17 12:12, Leif Lindholm wrote:
> On Thu, Aug 17, 2017 at 01:47:59AM +0200, Laszlo Ersek wrote:
>> On 08/17/17 00:37, Jordan Justen wrote:
>>> On 2017-08-16 12:23:49, Leif Lindholm wrote:
>>
>> [snip]
>>
- the value proposition
for Linaro is that having maintainer parity
On Thu, Aug 17, 2017 at 01:25:46PM +0100, Ard Biesheuvel wrote:
> The ArmPkg implementation of DmaLib uses double buffering to ensure
> that any attempt to perform non-coherent DMA on unaligned buffers cannot
> corrupt adjacent unrelated data which happens to share cachelines with
> the data we
On 17 August 2017 at 13:43, Leif Lindholm wrote:
> On Thu, Aug 17, 2017 at 01:25:46PM +0100, Ard Biesheuvel wrote:
>> The ArmPkg implementation of DmaLib uses double buffering to ensure
>> that any attempt to perform non-coherent DMA on unaligned buffers cannot
>>
On Thu, Aug 17, 2017 at 01:45:58PM +0100, Ard Biesheuvel wrote:
> On 17 August 2017 at 13:43, Leif Lindholm wrote:
> > On Thu, Aug 17, 2017 at 01:25:46PM +0100, Ard Biesheuvel wrote:
> >> The ArmPkg implementation of DmaLib uses double buffering to ensure
> >> that any
Add an android kernel loader that could load kernel from storage
device.
This android boot image BDS add addtitional cmdline/dtb/ramfs
support besides kernel that is introduced by Android boot header.
This patch is derived from Haojian's code as below link.
https://patches.linaro.org/patch/94683/
This patch series add new definition for RTIT Topa table entry and
update code to use MSR structure instead of BITxx style to make code
more user friendly.
Eric Dong (2):
UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition.
UefiCpuPkg/CpuCommonFeaturesLib: Use MSR data
Add RTIT TOPA table entry definition to architecturalMsr.h file.
Cc: Michael Kinney
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong
---
Cc: Ye Ting
Cc: Fu Siyuan
Cc: Shao Ming
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
---
MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf | 3 +--
Reviewed-by: Fu Siyuan
-Original Message-
From: Wu, Jiaxin
Sent: Friday, August 18, 2017 10:52 AM
To: edk2-devel@lists.01.org
Cc: Ye, Ting ; Fu, Siyuan ; Shao, Ming
; Wu, Jiaxin
Hello all,
I need a piece of information about DNS driver.
We are aware that the NetworkPkg contains DNS driver.
Is this driver able to relay a request that has come from another DNS client?
Thank you
Naveen
___
edk2-devel mailing list
The SPC-4 spec says about the INQUIRY data, in "Table 138 -- Peripheral
qualifier":
> Qualifier = 011b The device server is not capable of supporting a
> peripheral device on this logical unit. For this
> peripheral qualifier the peripheral device type shall
>
The code after the "if" statement is only reachable if the first branch
with the "break" is not taken. Therefore we can move the "else" branch
after the "if" statement, simplifying the code.
Cc: Eric Dong
Cc: Feng Tian
Cc: Hannes Reinecke
The commit messages say it all.
Repo: https://github.com/lersek/edk2.git
Branch: nonexistent_luns
Cc: Eric Dong
Cc: Feng Tian
Cc: Hannes Reinecke
Cc: Paolo Bonzini
Cc: Star Zeng
Thanks
The SPC-4 says about INQUIRY,
> In response to an INQUIRY command received by an incorrect logical unit,
> the SCSI target device shall return the INQUIRY data with the peripheral
> qualifier set to the value defined in 6.4.2. The INQUIRY command shall
> return CHECK CONDITION status only when
When update MSR values, current code use BITxx to modify it. Enhance the code
to use corresponding MSR's data structures to make it more user friendly.
Cc: Michael Kinney
Cc: Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.1
yes, small tiny OS that can run on UEFI is OK for me
At 2017-08-17 18:01:23, "Ni, Ruiyu" wrote:
>I believe what you want is a multi-threading capable tiny OS.
>I don't know a real project for your purpose.
>But I guess there should be plenty of such projects there,
On 2017年08月10日 21:04, Leif Lindholm wrote:
You've reworked this to be targeted for edk2-platforms, which is
excellent! However:
- Please update subject line to match.
- Please also cc edk2-devel@lists.01.org (since you are with Linaro,
it makes sense to still cc linaro-uefi)
To get the
On 2017年08月10日 23:00, Leif Lindholm wrote:
On Wed, Aug 09, 2017 at 10:12:39PM +0800, Jun Nie wrote:
Add platform build system files, including *.dsc *.fdf *.dec
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jun Nie
---
On 2017年08月10日 22:03, Leif Lindholm wrote:
On Wed, Aug 09, 2017 at 10:12:37PM +0800, Jun Nie wrote:
Runtime service is not supported yet.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jun Nie
---
.../Zx6718RealTimeClockLib/Zx296718RealTimeClock.c
On Thu, Aug 17, 2017 at 11:43:37PM +0800, Jun Nie wrote:
> On 2017年08月10日 22:03, Leif Lindholm wrote:
> > On Wed, Aug 09, 2017 at 10:12:37PM +0800, Jun Nie wrote:
> > > Runtime service is not supported yet.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.0
> > > Signed-off-by:
On 2017年08月10日 22:41, Leif Lindholm wrote:
On Wed, Aug 09, 2017 at 10:12:38PM +0800, Jun Nie wrote:
Add boot manager lib and entries, including Android and Grub.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jun Nie
---
On Thu, Aug 17, 2017 at 11:42:23PM +0800, Jun Nie wrote:
> On 2017年08月10日 21:04, Leif Lindholm wrote:
> > > diff --git a/Silicon/Sanchip/Zx296718/Include/Zx296718.h
> > > b/Silicon/Sanchip/Zx296718/Include/Zx296718.h
> > > new file mode 100644
> > > index 000..3ace9ab
> > > --- /dev/null
> >
Hi Mike,
I have updated the patch to follow your suggest. Please help to review the new
patches.
BTW, why we can't use UINT64 bit fields? Does it have potential issue in 32
bits system?
Thanks,
Eric
From: Kinney, Michael D
Sent: Friday, August 18, 2017 1:33 AM
To: Dong, Eric
Eric,
You should not us UINT64 for bitfields. Please use UINT32 instead, and make
sure bitfields do not cross 32-bit boundaries. Other than that, adding this
structure to ArchitectureMsrs.h with the comments you have looks correct to me.
I agree that MAX_TOPA_ENTRY_COUNT should remain in the
On Thu, Aug 17, 2017 at 11:45:52PM +0800, Jun Nie wrote:
> On 2017年08月10日 22:41, Leif Lindholm wrote:
> > On Wed, Aug 09, 2017 at 10:12:38PM +0800, Jun Nie wrote:
> > > Add boot manager lib and entries, including Android and Grub.
> > >
> > > Contributed-under: TianoCore Contribution Agreement
Eric,
Define PcdCpuFeaturesSetting set to 0x10 ProcTraceMemDisable
as the default. If this PCD is 0x10, then the ProcTrace
feature is enabled. If this PCD is less than 0x10, then the
ProcTrace feature is enabled. Basically, if the PCD is
configured to allocate memory for the feature then the
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