I currently don't have an answer to the MOSFET question, but I did
receive the switmod.asc file that was attached.
Though, I have "My membership settings" set to "Each email" in my Google
account. Refer to the "Change your own subscription settings" section
on the page at:
The Electric cmosedu tutorials at [1] or Electric manual pages such as
[1,2] can probably help you with that.
As seen at [2], it might be under "Editing Modes" that you need the
selection icon selected and under "Object or Area" that you may need the
Object icon selected. Or if the well is
On the first slide of the video, I see:
Prepared by
Sherlock-MBV Consulting, LLC
holmes at sherlock-mbv.com
It looks like that might have been a startup, but I wonder if it went
out of business.
As it looks like Holmes left that company and may now be at Ozark
Integrated Circuits, Inc.:
As far as I know, Electric 9.07 released in 2016 is still the latest
stable binary release, which is at:
https://www.staticfreesoft.com/productsFree.html
However, it looks the source code in the trunk has some changes from 4
weeks ago:
http://svn.savannah.gnu.org/viewvc/electric/
That
was area optimal)
Regards,
Bibin
On Sun, 6 Jun 2021, 10:43 pm Gavin Abo, <mailto:gabo13...@gmail.com>> wrote:
I could be wrong as it been quite some time since I did an Electric
layout, but I thought one (or more) of the tutorials at [1] went over
changing the wire sizes (e.
Have you looked into ASAP7 [1,2], Open-Cell FreePDK Libraries [3-5], and
cadence generic PDK [6-9] to see if they will work for you or not?
[1] http://asap.asu.edu/asap/
[2]
Use the search box on the webpage for this google group as there were
previous discussions on this in the past that you might find useful.
Electric has several built in technologies:
https://www.staticfreesoft.com/jmanual/mchap07-01-01.html
However, there is not yet any for 45 nm that I'm
As far as I know, the answer is No, such that Electric currently does
not support Liberty file generation.
To generate Liberty (.lib) files, I believe you would need a commercial
program like:
Synopsys SiliconSmart [
I'm not that familiar with using a subcircuit in LTSPICE, but an
observation:
It looks like the subcircuit is defined as:
.SUBCKT _4_variable A ABCD B C D gnd vdd
It looks like it tries to call the subcircuit with the line:
X_4_variab@0 inA out inB inC inD gnd vdd 4_variable
It looks like
Yes, it would be nice if MOSIS and/or TSMC had Electric support files
for TSMC180. I have never tried to contact MOSIS and TSMC about it. It
sounds like you contacted them such that is unfortunate to hear that
they don't have the support files at this time.
The NDA is perhaps a bit
Never tried it, so I don't know. I also don't have Calibre by Mentor
Graphics or Assura and PVS by Cadence Design Systems [
https://en.wikipedia.org/wiki/Design_rule_checking#Commercial_software ]
for exporting GDSII. Perhaps there is some free third party tool output
there for converting
This is a known problem.
I believe it started in LTspice XVII that Analog Devices changed the raw
file format. Thus, Electric is not able to read the new raw file. So
on the LTSPICE side, you would have to contact Analog Devices to see if
they can make a new version that outputs the old raw
Unless the functionality has changed in a newer version of LTSPICE, the
LTSPICE Mac version will not work as it does not take command line input
[
https://www.mail-archive.com/electricvlsi@googlegroups.com/msg01141.html ].
A workaround on a Mac may be to use wine [
If you search the Google Groups "Electric VLSI Editor" archive at:
https://groups.google.com/forum/#!forum/electricvlsi
There should be a post with the subject "Re: Physical Design from
Verilog File to synthesis - floorplanning - placement" on 12/30/2017.
If I recall correctly, I think there
If I understand correctly, when you do a write spice deck, it is writing
transistors names to your netlist (.spi) different from what you need
them to be, such that you are editing the transistors names in the .spi
file (instead of in Electric).
I believe you can change the transistor names
I believe the variables would be length, width, height, and resistance
or capacitance [resistance/volume for the resistor and
capacitance/volume for the capacitor (of the poly) , where volume =
length*width*height].
The resistive voltage divider tutorial and the poly1–poly2 capacitor and
RC
I believe that error (Unknown schematic syntax) with the LTspice XVII
Aug 9 2018 release [1] has been fixed.
Try the LTspice XVII Sep 4 2018 release at [2] or in LTSPICE try
upgrading the release to that by clicking Tools -> Sync Release.
[1]
That should be due to a problem with both LTspice and Electric.
The problem with LTspice is that the raw file format has changed.
As evidence of that, there is the statement at [1]:
"Regarding the error with LTSpice XVII, as Joshua Jones pointed out, the
error is due to the new version of
Hi,
I updated my LTspice XVII(x64) to the current Aug 9 2018 release [
http://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
], and when I try to drag and drop the attached test.spi file into
LTspice (with C5_models.txt placed in C:\Electric) it no longer
Sorry, I have never had an Electric layout fabricated by the MOSIS
foundry. So I don't know.
Have you tried contacting and asking the MOSIS foundry, it looks like
their contact information should be at:
https://www.mosis.com/support/contact-us
On 5/2/2018 4:10 PM, Oriero Enahoro wrote:
I
I'm not an expert on that, and I haven't found the time to try it.
However, I think you have to first obtain or determine the design rules
for your technology.
If your technology uses the FreePDK45 design rules, it looks like you
could get them at:
I could be wrong, but as far as I know, Electric has no PDK import.
Since you should be able to get the Electric source code [
http://www.staticfreesoft.com/jmanual/mchap01-04-01.html ], almost
anything should be possible with it. You could try writing yourself
additional code for Electric
For LTSPICE? For a netlist for SPICE, like LTSPICE, use Write Spice
Deck... [ http://www.staticfreesoft.com/jmanual/mchap09-04-01.html ].
On 4/18/2018 8:52 PM, Salar Parast wrote:
Hi there,
How can generate the Netlist for a project?
Thanks a lot for your help.
Cheers,
Salar
--
You
Have a look at lab 6 on cmosedu.com, maybe the LTSPICE or IRSIM example
there can help:
http://cmosedu.com/jbaker/courses/ee421L/f13/students/solori12/lab6/lab6.htm
If you cannot generate the waveform that you want with PULSE, maybe it
can be created from a PWL statement or PWL File instead:
I believe the IRSIM commands supported in the .cmd Stimuli file by
Electric's IRSIM plugin are:
*|* a comment in the command file
*!* command to print gate info
*?* command to print source/drain info
*activity*
*alias*
*ana*
*assert* command to test signal value
*assertWhen*
*back*
*c* command
No, the Electric manual is the most complete reference that I know of
for that.
For the "Old Way", there is an example "Electric VLSI Silicon Compiler
Verilog.pdf" that you should be able to find in the Google Groups
"Electric VLSI Editor" archive at:
First, layout and netlist should be two different things.
Maybe they forgot to generate a new netlist (Write Spice Deck) after
removing VDD in the layout. Though, maybe it will error and won't even
properly write one if one does that.
The netlist for the reported problem is:
*** TOP LEVEL
I could be wrong, but as far as I know, the schematic program that
Electric has cannot do this. My experience is that Electric uses Write
Spice Deck to output a netlist (.spi) file. The .spi is used to
simulate Electric's schematic in LTspice. I have almost no experience
using the schematic
If you have never used Electric before, it is recommended to start with
Tutorial 1 at:
http://cmosedu.com/videos/electric/electric_videos.htm
After that, do Tutorial 2 before doing the Tutorial 3.
If you just do Tutorial 3, the starting Electric library is the
tutorial_2.jelib file that you
Sorry, I currently don't know what is wrong with your circuit. Are you
following Hathaway's Lab 6 [1]?
If so, get the lab6.jelib (from [1]) and compare it with what you have
until you find out what is different.
[1]
If you download the tutorial_1.jelib file at
http://cmosedu.com/videos/electric/tutorial1/electric_tutorial_1.htm
open it in Electric (File -> Open Library), then write the spice deck
(Tools -> Simulation (Spice) -> Write Spice Deck). Does the same error
happen or does it only occur with
The file size of the electric-9.07 file looks okay. So it is not as
likely to be a problem with the jar file.
So, I suspect that the problem is more likely related to the JAVA
installation.
I suggest that you Google that JAVA error message, because maybe a
solution for it will come up in
, Gavin Abo wrote:
I found a gbr file here:
https://github.com/sleemanj/gerbv/blob/master/example/pick-and-place/LED.frontsilk.gbr
In Electric, File->Import->Gerber... was selected to load the file,
then LED.frontsilk{lay} was clicked on under the Explorer tab.
The layer in Electric
Maybe the TSMC plugin is needed for this. The one indicated in the
program when you click Help->About Electric, then click Plugins and see
"Missing: Technologies (cmos90, tsmc180)".
The ChangeLog.txt in the source code of the repository hints that the
developers, like SMR, GVG, JKG, and DN,
I imported your problem_prefs.xml. It looks like the preferences set
the Metal-2 and Metal-3 layers as invisible, unlike the visible Metal-1
that has a check mark next to it (Invisible Metal-2.jpg). Have you tried
selecting the Metal-2 and Metal-3 layers under the Layers tab and
clicked on
Try the "h" key [
http://www.staticfreesoft.com/jmanual/mchap02-04-01.html ].
On 7/7/2016 10:45 AM, Sean Brasfield wrote:
Hello everyone,
I'm trying to figure out how to change the step size when moving
components. At the moment I'm trying to build a schematic and I can
only move
Sorry, I don't have a Mac. So I cannot say for sure, but I believe it
is only an issue with the LTSPICE Mac version (LTspiceIV.dmg). It seems
like the LTSPICE Mac version does not take command line input.
The following site mentions that -ascii did not work with the LTSPICE
Mac version:
*Method 1 (Preferred method):*
When you switched to using the Cadence color scheme (Window->Color
Schemes->Cadence Colors, Layers and Keystrokes), you should have saved
the xml file (electricPrefsBack.xml) when the Electric program prompted
you to.
If you click File->Preferences, then click
Check the documentation for the version of the SPICE program that you
are using. It could be that your SPICE program does not have the lvlcod
option [
https://www.mail-archive.com/electricvlsi@googlegroups.com/msg01033.html
]. It could be that lvlcod option has become obsolete [
When writing the Spice deck, before clicking the Save button, select
"All Files" for the "Files of type", then enter your "File name" with
the .cir extension [
http://www.ee.virginia.edu/~mrs8n/electric/Tutorial1.htm ].
If you already saved the the Spice deck file with the .spi extension,
I haven't used a Chromebook. However, Google's support site for Chrome
devices says that they do not support JAVA:
https://support.google.com/chrome/a/answer/1290513?hl=en=1289187=topic
Electric requires JAVA.
You might be able to get around it by performing a hack, using Remote
Access and
If the format of the text file is compatible with Electric, you should
be able to use the "Load Parameters" button. If not, you will have to
manually (by hand) enter the data from the text file into the Technology
Creation Wizard. [ http://www.staticfreesoft.com/jmanual/mchap08-11.html ]
Or
In preferences>tools>spice/cdl>with args: What is filename that we
put?any random name ? or does it have to be the library or cell name?
Have you tried specifying a variable instead like ${FILENAME}?
Refer to:
[1] http://cmosedu.com/cmos1/ltspice/ltspice_electric.htm
[2]
Dear Estevao,
Thanks for confirming that you also see that the antenna error is
detected in version 9.05 of Electric, but not in 9.06. As I mentioned
previously, this seems to be because ret = ERCANTPATHGATE; on line 596
is not returned in the followNode function (line 462) such that the if
if this is the right fix or if different
changes are needed?
On 8/15/2015 3:56 PM, Gavin Abo wrote:
See the attached example in antenna_error.pdf and the accompanying
antenna_error.jelib.
On 8/15/2015 7:56 AM, Estevao Teixeira wrote:
Hi everyone:
I've tried to force an antenna error in my designs
I see that you are using electricBinary-9.05.jar. Have you tried the
latest electricBinary-9.06.jar [
http://www.staticfreesoft.com/productsFree.html ] to see if the same
thing happens? The 9.05 was released on 06-27-2014 and 9.06 was
released on 06-15-2015. In your email, I see that a
This group is dedicated to Electric and not LTspice. So you would
probably get a better response to your question from the LTspice group [
https://groups.yahoo.com/neo/groups/LTspice/info ]. You might have a
look at section 17. Project 13: Noise Simulation on page 113 in the
Spice-Simulation
I'm not completely sure, but I thinking that it might happen if the file
cmosedu_models.txt is missing or the cmosedu_models.txt is missing the
model that it is looking for (which in this case according to your error
message seems to be the n_50n for the m1 transistor).
I guess you are doing
I don't think all SPICE programs have the lvlcod option. Check your
T-SPICE documentation to see if the option is available or not. If it is
not available, then you probably have to edit the T-SPICE input file and
remove it.
On 3/8/2015 9:43 AM, aa.ara...@gmail.com wrote:
i designed an
I have never used T-SPICE.
However, as far as I know, there is no 45 nm technology file available
to the public for Electric. You have to make your own [
https://www.mail-archive.com/electricvlsi@googlegroups.com/msg01009.html ].
Regarding 45 nm SPICE models for T-SPICE, it says on the FAQ
it. The problem with the AntennaRules dialog is
fixed.
Thanks,
Gavin Abo
*Building Electric with NetBeans*
1. Register on java.net (skipped, optional).
1.Downloaded the All bundle of NetBeans (netbeans-8.0.2-windows.exe) at:
https://netbeans.org/downloads/
2.Installed NetBeans (netbeans-8.0.2
Electric has only design rules from MOSIS right?
No, Electric has design rules for more than just MOSIS.
You can have a look at:
http://www.staticfreesoft.com/jmanual/mchap07-04-02.html
The use of MOSIS with SCMOS design rules is probably most common.
However, as it describes in section
You can use a SPICE simulator with Electric like
LTspice:
http://cmosedu.com/cmos1/ltspice/ltspice_electric.htm
or WinSpice:
http://www.ee.virginia.edu/~mrs8n/electric/Tutorial1.htm
or HSPICE
http://cmosedu.com/cmos1/hspice/hspice.htm
Then, you can get the simulated voltage and power from
To use it, would you get the OPS.xml file (for 45 nm) in the latest
OpenPDK Open Process Specification package (Si2_OPDKC_OPS_1.2.tar.gz)?
Does Electric source code or a conversion script need to be written to
convert the data in the OPS.xml file to make it compatible with Electric?
If
Sorry, I don't know, but what technology do you have selected for
Antenna Rules under Tools in File-Preferences. I wonder if your
technology with 4 metals has to be selected, but maybe mocmos is instead
selected that has 6 metals.
On 2/10/2015 10:19 PM, suppmine wrote:
Hi everyone...
I run
I'm not familiar with the GDI technique. However, it looks to me that a
basic GDI cell is just a circuit with one NMOS and one PMOS transistor
where the gates of both the NMOS and PMOS are connected together to
create an input G terminal, the source and drain of the NMOS are
connected
Your question is not clear. I guess you are saying that you designed an
inverter circuit on a piece of paper, but now you want to make the
layout of the circuit in Electric.
I suggest you see the Electric tutorials on the cmosedu.com website at:
Someone else (like a developer of Electric) can probably better answer that.
If you check Technology-Scale in File-Preferences [
http://www.staticfreesoft.com/jmanual/mchap07-02-01.html ], I think the
default scale is 300 nm for mocmos. So my guess is that the design
rules are for 300 nm.
I'm not completely sure.
I believe those blocks in the xml technology file are for the values
that appear in Parasitic Preferences:
http://www.staticfreesoft.com/jmanual/mchap09-10-01.html#mchap09-10-01
minResistance value=4.0/ = My guess is in ohm (When it says you
can set its unit
I am quite new to LTSpice and as I was going through Prof Jacob
Baker's video lecture even in chapter 1 examples,
I have some issues in understanding the SPICE Deck.
I hope someone of u can clarify to me the following with respect to
the Figure attached:
1. The independent voltage source is
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