...@ieee.org}
Subject: RE: EMC Design Question for a Backplane ...
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Doug,
I have had the same discussion with both the designers and the board
layout
uy. Turns out that our standard proctice is to punch holes
Doug,
I have had the same discussion with both the designers and the board layout
guy. Turns out that our standard proctice is to punch holes for each connector
pin. The holes are usually 0.100 on the surface layer and 0.130 on the inner
layers. The result is overlapping holes that end up
Punch like a sieve i.e. one hole for each pin insted of a large cut-out. That
reduces the inductance of the power/ground plane. The increased noise coupling
in insignificant compared to the lost benefits of the low plane inductance.
Besides, you reduce the current flow capacity and create
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