I'm having a lively discussion with one of our
design engineers about backplane PCB design.
Here's the case:
1. Multilayer board, let's say 10 layers,
1 power plane (+5vdc), 3 ground planes,
6 signal planes.
2. Outside world connections to the
backplane with several connectors
Why is it that I frequently get e-mails that have the first letter of
each line missing? Is there anything that can be done about this?
Thanks,
Jim Eichner
Statpower Technologies Corp.
Burnaby, B.C., Canada
jeich...@statpower.com
Any opinions expressed are those of my invisible friend, who
Good point Eric - but I would have thought that IF the manufacturer does
not have an office in Australia and is relying upon the
importer/distributor to apply the c-tick mark then it would be
recommended that the manufacturer test at a NATA accredited lab (or at
least an impartial test-house)
Pat,
The times I had the analyzer jump to 1 Hz were when I had the 0 (zero) Hz
trace on the screen along with my signal to be measured and I had pushed
the PEAK SEARCH or MKR- function. Sometimes one can have the zero Hz
trace right on the far left vertical graticule of the display and not
Doug,
I have had the same discussion with both the designers and the board layout
guy. Turns out that our standard proctice is to punch holes for each connector
pin. The holes are usually 0.100 on the surface layer and 0.130 on the inner
layers. The result is overlapping holes that end up
Our HP8594EM does the same thing if you are spanning too wide a frequency
range. I suggest you break the CISPR 0.15 to 30 MHz band into three
subbands as: 0.15 to 1 MHz, 1 MHz to 10 MHz, then 10 MHz to 30 MHz. When
measuring a signal very close to 0.15 MHz, I further reduce the sweep range
to
Punch like a sieve i.e. one hole for each pin insted of a large cut-out. That
reduces the inductance of the power/ground plane. The increased noise coupling
in insignificant compared to the lost benefits of the low plane inductance.
Besides, you reduce the current flow capacity and create
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