[flashrom] Re: Release preparations

On Mon, Mar 21, 2022 at 4:48 PM Thomas Heijligen wrote: > Beside from the documentation, the meson file currently only works for > Linux and was never announced as official way to build flashrom. > The original reason for adding Meson was to support fwupd, a very important use case which AFAIK

[flashrom] Re: Truncating flash for oversized image

On Sun, Oct 31, 2021 at 10:10 AM Rob Shore wrote: > Hello! > > I've just discovered Flashrom as a way to use a Dediprog SPI programmer > with MacOS, which is awesome. I've got a bit of a strange question though: > > I've got a 1Mbit rom on a board, but the image I was given for it is for a >

[flashrom] Re: Wiki Edit Access

Hello Henry, We're gradually moving documentation into the flashrom git repository, giving us better versioning and eliminating the need to maintain additional accounts. Rather than putting more effort into the wiki which we hope to deprecate, perhaps you can you start a bbb text or markdown file

[flashrom] Re: One build system to rule them all (Meson)

Tossing in my $0.02 On Wed, Oct 28, 2020 at 4:19 PM Nico Huber wrote: > > Meson makes it possible to build fwupd as a subproject of fwupd, on > > any architecture, on any distro, which means we can use libflashrom on > > machines that don't ship a new enough distro version. > > That doesn't

[flashrom] Re: S25FL127S-128k

On Fri, Jul 10, 2020 at 1:33 PM ruckzuck--- via flashrom wrote: > List only S25FL127S-64kB and S25FL127S-256k > but not S25FL127S-128k why ? need flashrom a update ? The suffix indicates the sector layout - 64kB "hybrid" sectors or 256kB uniform sectors. > Probing for Spansion S25FL127S-64kB,

[flashrom] Re: Hardware Support

> Is the Spansion S25FL127S 128-Mb supportet Yes, however it's currently marked as "untested": https://review.coreboot.org/cgit/flashrom.git/tree/flashchips.c#n15558 ___ flashrom mailing list -- flashrom@flashrom.org To unsubscribe send an email to

[flashrom] Re: Uprgrae SPIROM for Skylake-D platform

Hello Hubert, Thanks for your help, I finally able to upgrade BIOS and Intel ME with "-c > "Opaque flash chip"" parameter. > I'm glad you got it working! For what it's worth you probably don't even need to use the '-c' option when using hardware sequencing. > But I can't find description of

[flashrom] Re: Do you have support for W25Q128FW and W25Q256.W?

7:20 PM > *To:* kcshe...@winbond.com > *Cc:* jl...@winbond.com; yl...@winbond.com; Wu, Amin ; > flashrom@flashrom.org; David Hendricks > *Subject:* Re: [flashrom] Re: Do you have support for W25Q128FW and > W25Q256.W? > > > > [CAUTION: External Email] > > Dear

[flashrom] Re: Uprgrae SPIROM for Skylake-D platform

Hi Hubert, > I have modified OPTYPE and OPMENU to support OPCODE 0x20 sector erase, but it > still failed. > //=== > Running OPCODE 0x20 failed at address 0x00 (payload length was 0). > spi_write_cmd failed during command execution at

[flashrom] Re: Uprgrae SPIROM for Skylake-D platform

Hello Hubert, There was some discussion about Skylake-D a few months ago: https://www.mail-archive.com/flashrom@flashrom.org/msg14426.html . There were some PCI IDs which were added (https://review.coreboot.org/c/flashrom/+/39780) after flashrom-v1.2 The problems you describe are strange,

[flashrom] Re: Current state of meson

> Well, as I stated previously, flashrom built with meson results in the > `-o` option not working at all. When helping others via IRC, we > recommend fetching flashrom logs using that option so that no messages > get lost, so not being able to rely on it is rather inconvenient. Ouch... Yeah,

[flashrom] Re: Do you have support for W25Q128FW and W25Q256.W?

distributions provide very old versions. On Wed, Apr 22, 2020 at 1:33 AM Wu, Amin wrote: > [AMD Official Use Only - Internal Distribution Only] > > > > Hi David Hendricks, > > “No EEPROM/flash device found” pop after I added below code to > flashchips.c and flashchi

[flashrom] Re: Do you have support for W25Q128FW and W25Q256.W?

Yes and yes :-) On Mon, Apr 20, 2020 at 10:05 PM Wu, Amin wrote: > [AMD Official Use Only - Internal Distribution Only] > > Hi > > Do you have support for W25Q128FW and W25Q256.W? Thanks > > > > > > BR > > AMIN > ___ > flashrom mailing list --

[flashrom] Re: Flashrom tool failed on the Intel Bakerville platform(CPU:SKY-D)

(Resending to the mailing list) From: David Hendricks Sent: Monday, March 2, 2020 2:50:24 PM To: flashrom@flashrom.org ; Ocean Huang Subject: Re: [flashrom] Flashrom tool failed on the Intel Bakerville platform(CPU:SKY-D) Hello Ocean, At the moment we do

[flashrom] flashrom-v1.2 tagged and released

Hello everyone, Flashrom v1.2 is out. A tarball has been added to download.flashrom.org/releases, and a new branch (1.2.x) and tag (v1.2) have been pushed. This release was rushed a bit so that we have a release that includes numerous build fixes that have been merged since v1.1. Fedora's build

[flashrom] Re: "pcidev.c: Factor out pcidev_validate() into pure fn" broke PCI programmers

> I am working locally on building out a test infrastructure that uses EM100's > to emulate flashchips and a bunch of different Chromebooks to exercise > flashrom more. The idea I have is to turn this into a upstream CI bot somehow > but I have to work out how that would work in practice and if

[flashrom] Re: Stepping Down as Flashrom Maintainer/Developer

Hi Nico, Thanks again for all the work you've done! As others have said it's much appreciated. I hope you'll find time to stay engaged. One thing I believe is frustrating to all of us is the state of paralysis that might be (at least partially) solved with better tools and automation. For

[flashrom] Re: ST 95XXX chips

Hello, Thanks for the PR (https://github.com/flashrom/flashrom/pull/84). I actually started to review this a long time ago, but apparently never finished :-/ My bad. The patch has a few merge conflicts, lots of dead code, and makes changes that appear unrelated to ST 95XXX support. Please resolve

[flashrom] Re: GitHub PRs

On Sat, Nov 30, 2019 at 7:37 AM Angel Pons wrote: > > Hi everyone, > > On Sat, Nov 30, 2019, 14:15 Nico Huber wrote: >> >> Hi all, >> >> the GitHub PR topic popped up from time to time on IRC in the past but >> it seems we never discussed it here or came to any conclusion that led >> to action.

[flashrom] Re: Flashrom using slowest item from block_erasers list

Hi Ryan, > What would be the best solution here? Would it make sense to submit this > change for this particular chip? I understand there may also be a speed/wear > tradeoff. > > I am also interested in the more general case. Do larger erase sizes tend to > reprogram a chip faster? If so, why

[flashrom] Re: Multiple flash chip defs on one chip

Hi Christopher, This means that Macronix reuses chip IDs for multiple chips with different capabilities (hence why there are multiple chip entries). It's very frustrating. I recommend avoiding Macronix and using a different flash chip vendor if you can. On Tue, Nov 19, 2019 at 9:45 PM OMGdaDPS

[flashrom] Re: Info

On Sat, Oct 5, 2019 at 8:31 PM Patrick Rogers wrote: > > Hello Ray, > > The hardware that you would need is something called a BIOS programmer. > Usually they use a USB port and might be found cheaply online. Flashrom > has a list of supported programmers: > >

[flashrom] Re: Kaby Lake R - not detecting chip & size correctly

Hi Rafael, > So would the solution be to flash the larger chip with some external tool > like a Raspberry Pi and adjust the size of the CBFS in coreboot (can do both, > shouldn't be a problem). That's part of it. However, you still need to update the flash descriptor contents (bottom 4KiB of

[flashrom] Re: flashrom support for Atmel/Adesto AT25SF041

Hi Jens, Thanks for the patch, it looks good. There's one important thing missing though: https://www.flashrom.org/Development_Guidelines#Sign-off_Procedure. Once we have your "sign-off" we can go forward with merging it. On Fri, May 24, 2019 at 3:06 PM Jens Gollasch wrote: > Hi folks, > > I

[flashrom] Re: Intel Atom E3845

Hi Karthik I'm working on Opencellular (https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/) which is based on Intel Atom E3845. I have built the coreboot image and would like to flash onto the Opencellular board. Could you tell how to flash only

[flashrom] Re: patch for allowing the use of the SOCKET target of the SF600

Looks good to me. Thanks! FWIW, I actually wrote a patch that is very similar, but never quite completed it: https://review.coreboot.org/c/flashrom/+/19673 So at least we know your patch is already tested ;-) On Mon, Jan 14, 2019 at 5:02 AM Florian Kaiser wrote: > Hello Nico, > > thanks for

[flashrom] Re: Is it possible to change only DMI data using flashrom ?

Hi, The answer is usually "no", but it depends on your BIOS. DMI data is usually not stored in the BIOS image in a structured format, and sometimes the strings (such as serial number) are also in a compressed region. On Tue, Jan 8, 2019 at 4:30 AM Марк Коренберг wrote: > I want to change, say,

[flashrom] Re: Help with a Winbond W25Q16

Hi, Thanks for posting the verbose output. It looks like the device ID bytes are showing up inconsistently - Sometimes probe_spi_rdid_generic shows 0x4011 and sometimes 0x4015. Often this indicates that your connection is bad or you are running the programmer too fast. The output also shows:

Re: [flashrom] 80/100/132 column line width policy

Regarding exceptions, I was taught that function signatures in header > files are an exception too. I don't mind either way, but if the rules > disagree with the current practice, we should make that explicit. > This makes sense, but can linters be taught the difference between source and header

Re: [flashrom] 80/100/132 column line width policy

This topic came up in a patch submission, and it occurred to me that we never actually wrote down canonical limits in the wiki. So I went ahead and added the proposed limits here: https://www.flashrom.org/Development_Guidelines#Coding_style It seems that we never really decided on 112-characters

Re: [flashrom] [LinuxBoot] FOSDEM 2019 deadline today

On Fri, Nov 2, 2018 at 9:15 AM 'Ron Minnich' via linuxboot < linuxb...@googlegroups.com> wrote: > I"m leaning to yes, by which I mean if you do it, I'll show up. > > I can't believe I said that. > On Fri, Nov 2, 2018 at 7:20 AM Carl-Daniel Hailfinger > wrote: > > > > Hi! > > > > FOSDEM next year

Re: [flashrom] flashrom error code message

Hello, I've seen this issue in cases where the voltage is not set correctly. What programmer are you using? A verbose log will also help. On Mon, Oct 15, 2018 at 11:28 PM MIAN VEREST wrote: > Recently i start to use flashrom software, moreless in a winbond chip i > receive this message, is

Re: [flashrom] FAILED: grunt

On Mon, Jul 9, 2018 at 5:05 AM, Charles Marslett wrote: > Well, never mind, I rebooted the target and the host systems, did a "repo > sync" of my chromeos setup, did a full firmware rebuild (described in the > care and feeding doc) then did a flash of the coreboot firmware, followed by > a flash

Re: [flashrom] Why does the flash content differ

On Mon, Jul 9, 2018 at 6:37 PM, microsoft gaofei wrote: > The commands are just the following: > sudo flashrom -w newbios --programmer internal > The operation is successful, BIOS content is replaced and the computer can > reboot successfully. > sudo flashrom -r compare --programmer internal > I

Re: [flashrom] Fail to flash W25X40

On Wed, May 30, 2018 at 9:03 AM, Yang Hu wrote: > Hi, > > I'm trying to rewrite a W24X40AL flash on a Seagate hard drive motherboard. > I can successfully read the data, although some weird things happened. > (First dumped code is nonsense, second time works fine, third or the rest > are just

Re: [flashrom] Update bios (not full flash) with flashrom

On Sun, May 27, 2018 at 11:44 AM, Skoll RC wrote: > Hi everyone, > > I would like to update my GA-8I915P-MF's bios with flashrom but Gigabyte > only provide updates and no full bios so when I try to update with > flashrom -p internal -w 8i9pmf.f2 I have an error message: Error: Image size >

Re: [flashrom] program MX25R3235F

Hi Daniel, Thanks for the report and confirming getting it initially working. I filed an issue on github to add support: https://github.com/flashrom/flashrom/issues/43 If you have time, send a patch: https://www.flashrom.org/Development_Guidelines#Patch_submission. On Sun, May 13, 2018 at

Re: [flashrom] MX66l51235f

On Mon, May 14, 2018 at 9:48 AM, Nico Huber wrote: > Hi Ron, > > On 14.05.2018 18:01, ron minnich wrote: > > anyone got the incantation to flash this with an sf100 ;-) > > TLDR; If it doesn't work with current master, you can try [1]. > > 512M, huh? what's that for, UbuntuBoot? xD

Re: [flashrom] [coreboot] flashrom on osx ...

[+flashrom, coreboot --> bcc] What version of OSX? I looked at this a bit last year, and they changed their frameworks in Sierra such that DirectHW needs to be updated. Stefan Tauner mentioned using osxcross ( https://github.com/tpoechtrager/osxcross.git) to build for OSX, but I've never used it.

Re: [flashrom] reading the flash image of my Celsius H265

> of `flashrom -p internal:laptop=force_I_want_a_brick -V`. IIRC, it >> also tells from which bus the BIOS was loaded. >> >> I think the ME has some logging enabled and simply writes to the flash. >> >> Nico >> >> > On 2018-05-10 23:24, David Hendrick

Re: [flashrom] reading the flash image of my Celsius H265

On Wed, May 9, 2018 at 1:12 PM, Elmar Stellnberger wrote: > When I boot with iomem=relaxed and enable flash writing in my BIOS I get > the following result with my Celsius H265 notebook: > > > flashrom -p internal:laptop=force_I_want_a_brick --read celsius2.rom > flashrom

Re: [flashrom] FAILED: Soraka DVT1

Hello Hongxia, Were you able to get in touch with someone on the chromiumos team? It appears that you attempted to write the entire firmware ROM, but it failed to write the flash descriptor region. You should target the region(s) you want updated using the -i option, along with --fast-verify, so

Re: [flashrom] Failed flash on Intel Bay Trail platform

Hi Quinn, On Wed, Jan 31, 2018 at 5:01 AM, Quinn Plattel wrote: > 13:56 < quinn> flashrom shows warning when reading or writing: BIOS region > SMM >protection is enabled! > Did you have any luck with this? There might be a BIOS setting in the menu that allows

Re: [flashrom] Github PRs

Hi Miklos, Yes, coreboot's gerrit system is likely where the review will take place. The github repository is a mirror of coreboot's flashrom repository, however we recognize that a lot of people do development on github so we work with pull requests as well. We also still have patch

Re: [flashrom] CrOS flashrom compatibility and upstreaming of CrOS features

On Wed, Jan 24, 2018 at 10:36 AM, Nico Huber wrote: > Hey folks, > > during review of commits that port per-region file arguments [1] from > CrOS flashrom over here, we ran into a discussion about the command line > interface changes. The basic question that arose is > > Do we

Re: [flashrom] GPG signature on flashrom release

Hi Bruno, Try again, it should be posted now (I used keys.gnupg.net). On Thu, Jan 11, 2018 at 9:44 AM, Archange wrote: > Hi, > > It seems that flashrom provides GPG sigs for the tarball, e.g. > http://download.flashrom.org/releases/flashrom-1.0.tar.bz2.asc, which is >

Re: [flashrom] [announce] flashrom 1.0

On Wed, Jan 3, 2018 at 10:05 AM, Nico Huber wrote: > > It is very discouraging - after 2 years of > > waiting to not see them at 1.0 > > It is indeed. There are also unmerged patches that are nearly 8 years > old... (not to mention patches in forks of flashrom). But things might >

Re: [flashrom] Bad MX25L4005AM2C ?

Hi Ondrej, The MX25L4005A is listed in the flashchips database as being supported, but as you point out the incorrect ID is being seen by the programmer. This is likely due to a signal integrity problem. Please try the following: 1. Slow down the SPI interface by setting a higher divisor value in

Re: [flashrom] chipset not found

On Wed, Dec 6, 2017 at 8:29 PM, David Velasco wrote: > Hi carl, > > I have the following error: > > # flashrom --programmer internal > flashrom v0.9.9-rc1-r1942 on Linux 4.10.0-40-generic (x86_64) > flashrom is free software, get the source code at https://flashrom.org > >

Re: [flashrom] particular spi flash controller

On Fri, Dec 1, 2017 at 12:11 AM, Andriy Gapon wrote: > > Hello. > > I wonder if anyone here encountered an SPI flash controller (master) that > has a > three register interface where the first register is used for control and > status > bits, the second register is used for

Re: [flashrom] winbond 25q128jvfm

Hi Ron, Can you check the full part number? There appears to be a couple versions of this chip, one with ID 0x4018 (like the existing W25Q128.V chips) and another version with additional instructions that identifies with 0x7018. I found a W25Q128JVSIQ and it reads/writes successfully with the

Re: [flashrom] Patch to flashrom for Macronix M25U12835F flash support and write protection bug fix

Hello Alex, Thank you for this patch and your friendly nudge in the other thread. I have uploaded it to chromium.org so that they can review, test, and merge it: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/753007 On Mon, Sep 4, 2017 at 8:47 PM,

Re: [flashrom] Future flashrom development

On Wed, Oct 25, 2017 at 4:04 AM, Nico Huber wrote: > > On 23.10.2017 09:39, Stefan Tauner wrote: >> >> On Fri, 13 Oct 2017 17:42:11 +0200 >> Nico Huber wrote: >> >>> What I didn't realize last night: the `staging` branch contains >>> valuable information in lots of

Re: [flashrom] Future flashrom development (Stefan's PoV II)

On Mon, Oct 23, 2017 at 7:03 PM, Stefan Tauner wrote: > Hi again, > > just to summarize my last email (since it's been over a week again): > there was quite some work done behind the scenes for flashrom's git > conversion that also included a proposed change in the

Re: [flashrom] Future flashrom development (Stefan's PoV I)

On Wed, Oct 18, 2017 at 10:31 AM, Nico Huber <nic...@gmx.de> wrote: > On 17.10.2017 01:14, David Hendricks wrote: > >> On Sat, Oct 14, 2017 at 7:20 AM, Stefan Tauner <stefan.tau...@gmx.at> >> wrote: >> >>> While there was a bunch of patches that

Re: [flashrom] Future flashrom development (Stefan's PoV I)

Thanks for the detailed write-up. I suppose there's another part coming so I don't want to get too deep into discussion just yet, but one part in particular caught my eye: On Sat, Oct 14, 2017 at 7:20 AM, Stefan Tauner wrote: > While there was a bunch of patches that have

Re: [flashrom] Unsupported Chip

Hello Abran, Can you post a verbose log (flashrom -V ...)? The chip should be supported, though there might be some limitation with your programmer that prevents it from being flashed, especially if you're using an Intel platform. On Sun, Oct 15, 2017 at 3:48 PM, Abran DeCarlo Hernandez <

Re: [flashrom] Future flashrom development

On Fri, Oct 13, 2017 at 11:42 PM, Nico Huber wrote: > On 13.10.2017 02:40, Nico Huber wrote: > >> So I propose the following: Forget the two branches model, start >> a `master` branch with either the current state of `staging` or >> my proposed move to `stable` [3] and release

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

t text ... From: flashrom <flashrom-boun...@flashrom.org> on behalf of Sandy Zhang <sanzh...@celestica.com> Sent: Monday, August 14, 2017 4:36:00 AM To: David Hendricks Cc: flashrom@flashrom.org Subject: Re: [flashrom] When flashrom support Intel Purley platform L

Re: [flashrom] Using libflashrom from fwupd

On Tue, Aug 15, 2017 at 4:55 AM, Richard Hughes wrote: > Hi all, > > I'm the maintainer of fwupd, which is a daemon for doing firmware > updates in Linux. Using fwupd about 200,000 people update firmware > every month. At the moment I have an out-of-tree patch to use the >

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang <sanzh...@celestica.com> wrote: > Hi David, > > I'm inline. > I don't see your responses. Did you intend to reply to my comments? > > 2017-08-14 9:17 GMT+08:00 David Hendricks <david.hendri...@gmail.com>: > >

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Hi Sandy, Responses in-line. On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang wrote: > Hi David, > > Sorry, I have a doubt about the range outside, from the binary map, > we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 = 0x1, > and the binary size

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

ill can't flash, it prompts > "Transaction error between offset 0x00ff and 0x00ff003f (= 0x00ff003f > + 63)"! > > > > > 2017-08-10 15:29 GMT+08:00 David Hendricks <david.hendri...@gmail.com>: > >> Hi Sandy, >> Recent Intel PCHs use hardware sequenc

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

o add the patch to flashrom-0.9.9, but I >> found the difference is a bit big between these files, I'm very hard to add >> the patch completely, so, could you send the latest package to me to try >> this on my system? >> Thanks for your great help! >> >> >

Re: [flashrom] flash verification failure over and over

On Wed, Aug 9, 2017 at 8:22 AM, Ian Stewart wrote: > Thanks David, > > Yes, the chip is detected and I'm able to read the chip just fine. Would > this indicate everything is hooked up properly? Or could missing the /HOLD > /WP /RESET cause write issues, but not read

Re: [flashrom] "Intel Braswell" with PCI ID 8086:229c

Thanks! Patch to mark Braswell as tested: https://review.coreboot.org/#/c/20923/ On Mon, Aug 7, 2017 at 6:06 AM, Vieweg, Uwe wrote: > Dear Ladies and Gentlemen. > > *”**Found chipset "Intel Braswell" with PCI ID 8086:229c.* *This chipset > is marked as **untested* > >

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

on your system. On Tue, Aug 8, 2017 at 7:09 PM, Sandy Zhang <sanzh...@celestica.com> wrote: > Hi David, > > Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI" has > been tested with the flashrom? thank you! > > > > > > > 2017-0

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

engineer, it is a bit difficult for me to complete this. >> Do you know when will make it into a release tarball? >> >> >> >> BR >> Sandy >> >> 2017-08-05 0:05 GMT+08:00 David Hendricks <david.hendri...@gmail.com>: >> >>> On Aug 3,

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

rg/Downloads;? thank you! > The Skylake patches have not made it into a release tarball yet. Can you try using the git sources from https://review.coreboot.org/cgit/flashrom.git? E.g: git clone https://review.coreboot.org/flashrom.git git checkout origin/staging make > > > > B

Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Hi Sandy, Skylake support was recently merged: https://review.coreboot.org/18973 However you may need to add your PCH PCI ID. What does `lspci -nn | grep LPC` show on your test system? And yes, a 32MB ROM should work fine. On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang

Re: [flashrom] Larger SPI NOR flash parts

On Wed, Jun 21, 2017 at 6:51 PM, Ed Swierk <eswi...@skyportsystems.com> wrote: > On Mon, Apr 17, 2017 at 9:54 PM, David Hendricks > <david.hendri...@gmail.com> wrote: > > Getting 4-byte address support in is something I'm interested in as > well. In fact I have parts c

[flashrom] Flashrom and DirectHW on MacOS

I am interested in getting flashrom running on MacOS, but it seems that the DirectHW package [1] which it depends on hasn't been updated for quite some time and won't install on Sierra (10.12.4). There's an updated branch of DirectHW from PureDarwin [2] that resolves compilation errors due to

Re: [flashrom] Namespace prefix for libflashrom

On Sun, Apr 23, 2017 at 7:07 AM, Stefan Tauner <stefan.tau...@gmx.at> wrote: > On Sat, 22 Apr 2017 11:16:18 -0700 > David Hendricks <david.hendri...@gmail.com> wrote: > > > Thanks for getting this discussion going on the list, Nico. > > > > For reference, fo

Re: [flashrom] Namespace prefix for libflashrom

Thanks for getting this discussion going on the list, Nico. For reference, folks can view the proposed libflashrom.h at https://review.coreboot.org/#/c/17946 to get a better idea for how these prefixes will look in libflashrom functions and data structures. Also, let's add "fi_" for flashrom

Re: [flashrom] Larger SPI NOR flash parts

Hi Alex, Getting 4-byte address support in is something I'm interested in as well. In fact I have parts coming in the mail this week :-) On Mon, Apr 17, 2017 at 6:43 PM, Alex Henderson < ahender...@aparnasystems.com> wrote: > Hi there: > >I just started experimenting with

Re: [flashrom] question on padding

That comes up once in a while, but the idea usually gets shot down because the size check is more important for the general case. Deciding whether to place the content at the top or bottom is another matter. For chromiumos I added a command to get the flash chip's size (--get-size IIRC) so that

Re: [flashrom] Terminology to help distinguish different ways of using Flashrom

On Sun, Mar 19, 2017 at 10:42 AM, Sam Kuper wrote: > Is there a term that unambiguously describes method 2(b)? Just to clarify, in that situation is the ROM is in a dedicated programmer such as http://www.dediprog.com/pd/universal-programmer/progmaster-u4 ? I'd describe it

Re: [flashrom] Layout Aware Flash Reading and Erase Blocks

On Fri, Mar 10, 2017 at 8:02 AM, Nico Huber wrote: > > Hi, > > I've just updated my solution to _the_ layout problem that I wrote last > year [1]. I'm not asking for a review at this moment. There are at least > two competing approaches that I want to discuss first (I

Re: [flashrom] FAILED: GA-B75M-D3V

Looks like it failed to overwrite the descriptor region (Intel ME-related headache): https://www.flashrom.org/ME You can target regions more carefully using a layout file. It appears the other regions (ME, BIOS, GbE) are unlocked, so you can try creating a layout that includes only those regions.

Re: [flashrom] (no subject)

.coreboot.org/cgit/flashrom.git -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. ___ flashrom mailing list flashrom@flashrom.org https://www.flashrom.org/mailman/listinfo/flashrom

Re: [flashrom] Apollo Lake

try accessing locked regions. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. ___ flashrom mailing list flashrom@flashrom.org https://www.flashrom.org/mailman/listinfo/flashrom

Re: [flashrom] [PATCH] RFC: enable flashrom to write images of arbitrary size

ame)) { > + size = read_buf_from_file(newcontents, size, filename); > + if (size < 0) { > ret = 1; > goto out; > } > - > + flash->chip->total_size = size / 1024;

Re: [flashrom] Can't find Write protect screw on Samsung XE500C21

wrote: > Actually, I checked on the ribbon cables and it says Alex. I might of > typed in the wrong model number, Whoops https://www.chromium.org/ > chromium-os/developer-information-for-chrome-os-devices/samsung-series-5- > chromebook > > On Fri, Oct 14, 2016 at 7:13 PM, David Hendri

Re: [flashrom] Can't find Write protect screw on Samsung XE500C21

it? > Regards > -Chris > > ___ > flashrom mailing list > flashrom@flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

Re: [flashrom] Development flashrom

What exactly are you trying to do? How do you plan to use the CC3200? How is the flash memory connected / accessed? TI has some information about flashing it here: http://processors.wiki.ti.com/index.php/CC31xx_%26_CC32xx_FTDI_Flashing If you'd like, you can try adding support for the FTDI chip

Re: [flashrom] [RFC] [PATCH] Add ability to lock bootblock on Winbond Flash ROMs

nt selfcheck(void); > -int doit(struct flashctx *flash, int force, const char *filename, int > read_it, int write_it, int erase_it, int verify_it); > +int doit(struct flashctx *flash, int force, const char *filename, int > read_it, int write_it, int erase_it, int verify_it, int lock_it); > int read_buf_from_file(unsigned char *buf, unsigned long size, const char > *filename); > int write_buf_to_file(const unsigned char *buf, unsigned long size, const > char *filename); > > Index: spi.h > === > --- spi.h (revision 1955) > +++ spi.h (working copy) > @@ -121,6 +121,11 @@ > #define JEDEC_RDSR_OUTSIZE 0x01 > #define JEDEC_RDSR_INSIZE 0x01 > > +/* Read Status Register 2 */ > +#define JEDEC_RDSR20x35 > +#define JEDEC_RDSR2_OUTSIZE0x01 > +#define JEDEC_RDSR2_INSIZE 0x01 > + > /* Status Register Bits */ > #define SPI_SR_WIP (0x01 << 0) > #define SPI_SR_WEL (0x01 << 1) > > ___ > flashrom mailing list > flashrom@flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. ___ flashrom mailing list flashrom@flashrom.org https://www.flashrom.org/mailman/listinfo/flashrom

Re: [flashrom] Aspire One

On Fri, Aug 5, 2016 at 10:49 PM, wrote: > Hi, > > In the Laptop table the Aspire one is listed as BAD > But as there are so many different aspire one models i wonder if ALL Aspire > one models are BAD > > In my case i have the ZG5 model also known as AOA110 (512MB) and

Re: [flashrom] Writing to a specific Flash region with Layout approach

;> The current layout system will only limit the actually written area, >> not change the requirements of the flash file being the size of the >> chip, so in this case you'd need to pad the bootloader.img to 8MB. >> > > ___ > flashrom mailing list > flashrom@flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. ___ flashrom mailing list flashrom@flashrom.org https://www.flashrom.org/mailman/listinfo/flashrom

Re: [flashrom] RFC: New testing script with remote test capabilities and region awareness

rom 8af85a07966b9486ea78c381c948aeb44bdcca7c Mon Sep 17 00:00:00 2001 From: David Hendricks <dhend...@chromium.org> Date: Sun, 19 Jun 2016 12:53:22 -0700 Subject: [PATCH] WIP: New test script for flashrom ** work in progress ** Shiny new testing capabilities for Flashrom: - Region awareness - Remot

Re: [flashrom] RFC: New testing script with remote test capabilities and region awareness

On Tue, Jul 5, 2016 at 12:11 AM, Stefan Tauner wrote: > > I don't have time to look at the code right now No rush - It's still in flux and the script itself is pretty monstrous so I don't expect a thorough review any time soon. So far I've been the only person

[flashrom] RFC: New testing script with remote test capabilities and region awareness

that would be better in another script or as a whitebox test (more on that later...). Here's the patch as of revision #14 on chromium.org's gerrit server: https://chromium-review.googlesource.com/#/c/353912/ As in the gerrit message, Signed-off-by: David Hendricks < dhend...@chromiu

Re: [flashrom] Ideas for implementing support for 2nd status register

On Fri, Jun 17, 2016 at 6:32 PM, Hatim Kanchwala wrote: > Hi, > > Regarding block protection scheme, I am very glad to say I have had a > breakthrough observation. After having sifted through around 90 datasheets, > I was able to spot a pattern that majority of chips follow.

Re: [flashrom] [PATCH 0/6] 4-bytes addressing support

create mode 100644 spi4ba.h > > -- > 2.1.4 > > > ___ > flashrom mailing list > flashrom@flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. ___ flashrom mailing list flashrom@flashrom.org https://www.flashrom.org/mailman/listinfo/flashrom

Re: [flashrom] Ideas for implementing support for 2nd status register

Hi Hatim, On Tue, May 31, 2016 at 3:25 AM, Hatim Kanchwala <ha...@hatimak.me> wrote: > On Sunday 29 May 2016 02:40 PM, David Hendricks wrote: > >> Hi Hatim, >> Interesting approach. It seems to work well for pretty printing, though >> I am curious how this will tran

Re: [flashrom] Ideas for implementing support for 2nd status register

Hi Hatim, Interesting approach. It seems to work well for pretty printing, though I am curious how this will translate into ranges. Do you have an example for translating status_register_layout structs to a range of bytes protected, for example 0x00-0x1f?

Re: [flashrom] New SPI NOR Flash product Support

mber to choose from. > > > > Regards, > > > > Victor > > > > > > *From:* David Hendricks [mailto:dhend...@google.com] > *Sent:* Sunday, May 8, 2016 7:43 PM > *To:* Victor Lim <v...@gigadevice.com> > *Cc:* Hatim Kanchwala <ha...@hatimak.me>;

Re: [flashrom] [PATCH 2/2] dediprog: Fix bug where too many transfers would be queued

Looks good to me. Acked-by: David Hendricks <david.hendri...@gmail.com> On Wed, May 4, 2016 at 4:37 AM, Nico Huber <nico.hu...@secunet.com> wrote: > We didn't check the total number of queued transfers in the inner most > loop. Up to DEDIPROG_ASYNC_TRANSFERS - 1 inval

Re: [flashrom] [PATCH 1/2] dediprog: Reimplement target chip option

Looks good to me. Acked-by: David Hendricks <david.hendri...@gmail.com> On Wed, May 4, 2016 at 4:37 AM, Nico Huber <nico.hu...@secunet.com> wrote: > Signed-off-by: Nico Huber <nico.hu...@secunet.com> > --- > dediprog.c | 17 ++--- > 1 file changed,

Re: [flashrom] Giving to -i option some real use

On Thu, Apr 21, 2016 at 1:41 PM, Salvador Eduardo Tropea < salva...@inti.gob.ar> wrote: > Hi David: > > Thanks for your comments. > > > El 20/04/16 a las 20:42, David Hendricks escribió: > >> Hello Salvador, >> Yes, this is a very useful feature - w

Re: [flashrom] Giving to -i option some real use

.gob.ar/ > Unidad Técnica Sistemas Inteligentes Av. General Paz 5445 > Tel: (+54 11) 4724 6300 ext. 6919 San Martín - B1650KNA > FAX: (+54 11) 4754 5194 Buenos Aires * Argentina > > > > > > ___ &

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