Hi
All,
So my
last question got such a resounding reply (none) that I figured I'd try another
question.
On a
hybrid disk that has it's volatilewrite cache enabled andhas been
written to, when a flush command is received is the disk obligated to flush all
the way to the rotating media,
Hi
Folks,
The
Set NV Cache Power Mode command (cmd=B6h, features=0) specifies a count value
that is a "Minimum High-Power Time", but what does this really
mean?
Does
this time mean that the disk shall be spun-down immediately after the disk goes
idle for this time period, or is ittruly
Hi All,
As I read this specification, I don't understand how
Test Unit Ready is converted to a Check Power Mode, or more importantly how the
Check Power Mode result value isreported back to the requestor.
Could someone please describe how the CPM "Sector Count" values of 00h (device
in
Title: List for ATA8 additions
Good morning, everyone.
Is there a single document that enumerates the new features for ATA8?
Thanks, MKE.
This message is from the T13 list server.
It basically means that you program the HBA for the specific DMA
transfer before any data can be transferred.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of
kepler
Sent: Thursday, June 08, 2006 10:49 PM
To:
Title: What is STOR-ATA50?
Jeff, you are right. It is a logo requirements
item.
From: Wolford, Jeff [mailto:[EMAIL PROTECTED]
Sent: Friday, July 01, 2005 12:00 PMTo: Eschmann, Michael
K; forum@t13.orgSubject: RE: [t13] What is
STOR-ATA50?
That
has an amazing similarity to a Windows
Title: What is STOR-ATA50?
Has anyone ever heard of the term ATA50 or STOR-ATA50? What does this refer to?
I see it at various sites that describe a computer with ATA100 HDDs will also mention ATA50.
Thanks,
Michael K. Eschmann
STG, I/O Architecture, S/W Infrastructure and Algorithms
In d1532v1r4b, volume 1, look at the first
paragraph in section 4.20("Queued feature set"). It says "If a
queue exists when a non-queued command is received, the non-queued command shall
be command aborted and the commands in the queue shall be
discarded." The sentence has been there since
Title: SAT-r02 Posted
I don't know if a spec is available, but I've seen
"information" at http://www.ce-ata.org
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Josef ZeeviSent:
Wednesday, February 23, 2005 11:09 AMTo:
Forum@t13.orgSubject: [t13] CE-ATA?
I apologize if
Title: ATAPI Overlap and Queuing
Hmmm. Seems to me that ATAPI only supported
overlap and _not_ queuing. Where is queuing for ATAPI documented?
Maybe having brain-farts, MKE.
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Mark OverbySent:
Tuesday, December 07, 2004 2:05
Matt,
No, the busy and DRQ wait only happen for a PIO write (and
write multiple), so DMA ca just start the DMA engine and device command and then
wait for an interrupt. I hope this helps.
TTFN, MKE
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Matt HensonSent:
This message is from the T13 list server.
Hale and I were discussing an issue with the Execute Device
Diagnostics command, and I'd like to see if there's enough collective
memory as to why the spec is the way it is.
Ever since ATA5 there is a host-side state diagram that shows a
transition to
This message is from the T13 list server.
Greetings Singh,
First off, being 48-bit capable is really not relevant. If you're using a 28-bit
command, what it's behavior to that command is all that matters.
Now for the conditions. The max number of sectors for a 28-bit command is 268,435,456
This message is from the T13 list server.
In case you weren't aware, ATA 48-bit extended read and write supports
1 to 65536 sectors so the comment about it only supporting 256 sectors
is incorrect. TTFN, MKE.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On
Title: ABRT bit usage in SATA
Folks,
The ATA7 document describes error responses for all data commands with an interesting side-effect. In all read or write commands the following abort definition exists:
ABRT shall be set to one if this command is not supported or if an error,
This message is from the T13 list server.
James, I'm supprised you have to ask. I've been harping on having
standardized log entries for some time. Today most of them are
proprietary to each disk manufacturer. This has been something that the
disk folks have resisted for some time, with the
19, 2004 12:20 PM
To: Eschmann, Michael K; [EMAIL PROTECTED]
Subject: RE: [t13] How to detect whether a host adapter complies with
1510D
Agreed.
If ProgIF does not indicate native mode (or native mode capability that
is
not used) then BAR's 0-4 would be not programmable and would use
This message is from the T13 list server.
Hale, The flow you suggest is heavy-handed. Might I suggest some more
lenient methods? Read more below. MKE.
If you find a disabled controller, the device doesn't implement device
hiding, which is probably a bad idea. However an OS doesn't need to
This message is from the T13 list server.
Not exactly. 1510D includes ADMA, which your information is correct.
However non-ADMA HBA's are harder to detect. I can tell you everything
with Class+SubClass 0101 and VID=8086 are generally compliant with this,
but UDMA capabilities are dependent on
This message is from the T13 list server.
Hi Thomas,
What is in 1510D for non-ADMA represents Intel ATA controllers. Each
chip in the PIIX family (1,3,4) and ICH family (0,1,2,4,5,6) includes
some level of support for these features, with everything from ICH2
through ICH6 supporting the full
This message is from the T13 list server.
Mark, you are correct. The base PCI configuration registers should be
applicable to all ATA controllers, but note that not all support native
PCI so BAR's 0-4 are not used (should be zero). Everything from offset
40h and beyond are Intel's register
This message is from the T13 list server.
My comments interleaved below marked with MKE.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Pat
LaVarre
Sent: Tuesday, February 17, 2004 8:37 AM
To: [EMAIL PROTECTED]
Subject: Re: [t13] o x3F6 DeviceControl
Title: Message
Steve,
why in the world would one bit be off and the other on? There's no
enable/disable control for this feature, sothese bitsmust correlate
with each other. If you allowbit mis-correlation in your
drives, I can guarantee you that most drivers will not operate 48-bit
This message is from the T13 list server.
Curtis Stevens, if you are still out there please reply to this email.
Thanks, MKE.
Title: Message
Are
the minutes ready for December's plenary meeting?
9:15 PM
To: Eschmann, Michael K; [EMAIL PROTECTED]
Subject: Re: [t13] Anyone know the status of EDD3?
OK, maybe I should say comething...
I have a new draft of EDD3, but I have not had a sponsor to go to the
meetings. EDD2 is now published by ANSI as an standard, ANSI INCITS
363-2002. The last
(actually points to an early
draft of EDD2) whereas the Project Drafts link is correct. This could
be confusing some folks, so could we get this fixed?
Thanks, MKE.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of
Eschmann, Michael K
Sent: Thursday, December
This message is from the T13 list server.
I'm a little confused over which EDD document is which on the T13 web site. D1448r3
(BIOS Enhanced Disk Drive Services -2 (EDD-2)) seems to actually be the EDD-3 draft,
whereas D1386r5a (Enhanced Disk Drive Services 3.0 revision 5a) seems to actually
This message is from the T13 list server.
For UDMA interface CRC error, you should get status=51h and error=84h. UNC bit
would not be set since the data is correct on the media, and the error occurred during
transfer across the cable. Now is it possible to get an error value of C4h? I'd
This message is from the T13 list server.
Hale,
I believe that the SiI proposal is trying to describe any generic SATA-2-PATAPI brige,
but their specific interest is producing an ATAPI device that has an onboard bridge.
This case would mean that a bridge could support lesser capabilities
This message is from the T13 list server.
I agree with a lot of what you say here, Hale. I'd like to get some feedback on
changes I'd like to propose to this document:
A. Move the new bits in ID word 63 up to some unused (reserved) field. I'd suggest
offset 62, and the data out there would
. The integrated bridge
can push this responsibility to the ATAPI device, whereas the stand-alone bridge must
do it for the ATAPI device.
TTFN, MKE.
-Original Message-
From: Pat LaVarre [mailto:[EMAIL PROTECTED]
Sent: Thursday, November 20, 2003 12:41 PM
To: Eschmann, Michael K
Cc: [EMAIL
This message is from the T13 list server.
Since Curtis Stevens is on the lamb (at least that's the last I heard), who owns the
EDD3 project?
Thanks,
Michael K. Eschmann
Intel Americas, Inc.
TMG, I/O Architecture Lab
816-524-7418 (alt -7215)
This message is from the T13 list server.
Hi Jim,
What will be the duration of these meetings?
Thanks, MKE.
-Original Message-
From: Jim Hatfield [mailto:[EMAIL PROTECTED]
Sent: Monday, August 25, 2003 12:04 PM
To: [EMAIL PROTECTED]
Subject: [t13] Meeting: T13 ad hoc working group
This message is from the T13 list server.
Could it be that all our meeting minutes have attendee email addresses, plus lifting
the senders address from reflected emails is where the list comes from? Who out there
did not see two recent Nigerian-like scams apparently from the reflector? MKE.
This message is from the T13 list server.
My (humble?) opinion is that FUA is necessary and is not dangerous as long as a disk
drive properly deals with outstanding requests.
First off a flush is very slow, affecting system benchmark scores by as much as 5%.
The more interesting fact is that
This message is from the T13 list server.
Andre, I get the feeling your using drugs (again?)!
Give me a scenario that you perceive will fail using FUA on queued or non-queued
commands, then we can have a useful discussion. Just blowing smoke, as you've done
below, does nothing to resolve
This message is from the T13 list server.
Only the FUA command's data would be affected. Since a FLUSH command already affects
all commands in the write cache and FLUSH adversely affects performance, the FUA
command gives us the ability to target specific requests as non-cacheable so we can
This message is from the T13 list server.
Most OS drivers will send a request-sense command when a check-condition response to
a command comes in. In Windows-based systems drivers do send request-sense and the
result doe get logged in an event log, and higher-level drivers do react to those
This message is from the T13 list server.
Andre, I don't see your point. PATA and SATA are two separate transport
layers, so describing them separately seems quite obvious to me. And how
does this all relate to T10 and any claims of superiority? Thanks, MKE.
-Original Message-
This message is from the T13 list server.
Hi Hale,
The latest Microsoft hardware logo requirements (their enforcement arm)
still has some lingering SFF8070 requirements:
B10.5.2.3 SFF 8070i (ATAPI Removable Rewritable Media Devices specification)
for block rewritable optical ATAPI devices
This message is from the T13 list server.
And Word 83 bit 10 must also be set too.
What about Word 86 bit 10; should it also be set, or just one of the two
supported bits?
MKE.
-Original Message-
From: Gary Laatsch [mailto:[EMAIL PROTECTED]]
Sent: Friday, September 27, 2002 9:13 AM
This message is from the T13 list server.
James, all,
I gotta pipe-in with everyone else.
The features that show supported bits, but don't require specific enabling,
do not have a Set Features to control it; the feature just works (specific
enable flag bit says supported instead of enabled).
This message is from the T13 list server.
Hey Pete,
I called Bally's (702-739-4111) and they don't have a T13 (Fujitsu) group
meeting on the books so I couldn't reserve a room relative to the T13
group/meeting.
Can we get a verification that the meeting is at Bally's and we can reserve
rooms
This message is from the T13 list server.
Since Curtis Stevens moseyed from Phoenix to PD, who officially owns editing
of the EDD3 spec?
To get down to brass tacks, I've been getting calls about support for 48-bit
LBA in OS's that require the Int13 Fn48 call to return back the correct size
for
This message is from the T13 list server.
Hi Sergei,
The slot number is the same as the PCI Device number. In some non-T13
documents, the slot number is a combination of PCI Bus, Device and Function
numbers, but here it is just the PCI Device number.
MKE.
-Original Message-
From:
This message is from the T13 list server.
I don't see a spec value for the CDB length in the ATA/ATAPI-6 spec, so it
doesn't explicitly allow or disallow sizes other than 12 bytes. Note that
the SFF 8020r26 document states specifically that the CDB is 12 bytes (6
words).
MKE.
-Original
This message is from the T13 list server.
Pat, the drivers I've worked with will first turn off DMA at the controller
(by clearing the BMIDE command register Start/Stop Bus Mastering bit,
otherwise known as the START bit. Then the SRST bit will be hit on the
PIO-driven control register.
This message is from the T13 list server.
I'll add that PIO works better than MW/SW-DMA, since many folks have screwed
up those versions of DMA quite imaginitively. UDMA seems to be quite
healthy on the vast majority of devices I've seen. Most ATAPI devices of
more than a year old (and even
been used.
But I will respond to a few specific comments...
===
On Wed, 13 Feb 2002 08:01:35 -0800, Eschmann, Michael K wrote:
When you first started this thread you said you wanted a simple state
machine that says something started moving, versus DMA PRD count hit, and
DMA PRD count exceeded
Title: RE: [t13] FW: 48-bit address implications on partition table
Jim,
NTFS
may be able to handle 64-bit LBA's, but the class layer beneath them can only
handle 32bit LBA's.
The
SRBstructure defined in the Windows DDK only has a 34-bit LBA field.
Microsoft is quite aware of the issue
This message is from the T13 list server.
But Andre,
the devices are mostly MW2 or slower, so don't put the issue on UDMA. UDMA
has a fairly clear spec, where MW/SW operation gets screwed up by too many
people since documentation is few-and-far-between.
I've also seen CD-R,RW fail running
This message is from the T13 list server.
Pat, why do you insist that ATA/ATAPI can ever stop at an odd-byte boundary?
It transfers data as atomic words (except for CFA, which I hope you aren't
gonna confuse matters by talking about that).
You may be getting this on the host-side of a
This message is from the T13 list server.
I don't know of any host will send more data than we program; thats what the
PRD/scatter-gather table are for. When we program N words, only this many
words are transferred by the device.
Now some crazy person could write a driver that prepared more
transfers.
Hope this helps, thanks in advance.Pat LaVarre
Eschmann, Michael K [EMAIL PROTECTED] 01/30/02 08:51 AM
This message is from the T13 list server.
Pat, why do you insist that ATA/ATAPI can ever stop at an odd-byte boundary?
It transfers data as atomic words (except for CFA, which I
Yaniv,
Typically the"Active" bit (in the status
register) will follow the "Start" bit (in the Bus Master command
register). Using Intel ATA controllers, you have the following definitions
for each bit:
Start/Stop
Bus Master (SSBM). 1=Start;
0=Stop. When this bit is set to 1, bus master
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