Yaniv,
Typically the "Active" bit (in the status
register) will follow the "Start" bit (in the Bus Master command
register). Using Intel ATA controllers, you have the following definitions
for each bit:
Start/Stop
Bus Master (SSBM). 1=Start;
0=Stop. When this bit is set to 1, bus master operation starts. The controller
transfers data between the ATA device and memory only while this bit is set.
Master operation can be stopped by writing a 0 to this bit. This results in all
state information being lost (i.e., master mode operation cannot be stopped and
then resumed).
If
this bit is set to 0 while bus master operation is still active (i.e., Bit 0=1
in the Bus Master IDE Status Register for that ATA channel) and the drive has
not yet finished its data transfer (bit 2=0 in the channel's Bus Master IDE
Status Register), the bus master command is aborted and data transferred from
the drive may be discarded by the
controller rather than being
written to system memory. This bit is intended to be set to 0 after the data
transfer is completed, as indicated by either bit 0 or bit 2 being set in the
ATA Channel's Bus Master IDE Status Register.
Bus
Master IDE Active (BMIDEA)—RO. ICH
sets this bit to 1 when bit 0 in the BMICx Register is set to 1. The
controller sets this bit to 0 when the last transfer for a region is performed
(where EOT for that region is set in the region descriptor). The
controller also clears this bit to 0 when bit 0 of the BMICx Register is set to
0. When this bit is read as a zero, all data transferred from the drive during
the previous bus master command is visible in system memory, unless the bus
master command was aborted.
As for
the Queued DMA question, I don't think too many folks use this in a
production environment today, so you could be on your own (as
stability goes).
I
don't think you can check the status of a queued command, rather you send
the command and either immediately transfer data or get a release for the
current command. When you do get a service command, you then get
the idea that the device is ready to transfer data for this command.
So basically, I don't believe there is a way to get status for a
queued request after it is released and before the device requests
service.
The
host should count commands if it wants to keep track of how many commands are
outstanding. And for queue depth reported in IdDrive data, this would be
vendor specific, so you should expect any value between 1 and
32.
TTFN, MKE.
Dear T13,
Can you help me with the following questions:
Bus Master IDE rev 1.0
- When the start bit is cleared and
ACTIVE bit in the Bus Master IDE status register is set -
What is the correct behavior of the DMA? Let's assume
that a command using UDMA protocol is ongoing:
Abort
the ATA command? How? Perform burst termination? OR
Waits till command completion?
Queued DMA commands
- Are there any working solutions with these
commands? Can I rely on it's stability?
- Can the host check the status of
the queued commands within the device?
Does the device
provide an indication when it's queue is full? or
Must
the host controller count the commands getting in/out from the device's queue?
- The queue depth supported by the device is indicated in word 75 of
the IDENTIFY DEVICE response.
What is the possible
values? anything goes in a range of 1 to 32? or only a power of two
(1,2,4,8,16,32)?
Thanks in advance,
Yaniv Shapira
Tel: 972-8-9247555/1318
Email:
[EMAIL PROTECTED]
Galileo Technology Ltd. - A
Marvell company
