On Fri, Jul 14, 2000 at 08:46:40AM +0200, Wilko Bulte wrote:
That theory is not correct, I have seen multiple Alpha machines reporting
buffer underruns as well. No ATA disk in sight there..
I get the same thing on AS4000/AS4100 machines running Tru64. I'm
inclined to believe it's a design flaw
...
As far as I can tell the fxp driver doesn't even use the tx_fifo in the
825xxx chips :-)
The 82557-9 have a 2KB internal buffer for transmits. They don't start
transmitting until a programmed threshold is reached - this is to insure
that PCI bus latency doesn't result in the
On Friday, 14th July 2000, "Rodney W. Grimes" wrote:
I suspect an interaction between the ATA driver and VIA chipsets,
because other than the network, that's all that is operating when I see
the underruns. And my Celeron with a ZX chipset is immune.
I've seen them on just about everything,
On Friday, 14th July 2000, "Rodney W. Grimes" wrote:
I suspect an interaction between the ATA driver and VIA chipsets,
because other than the network, that's all that is operating when I see
the underruns. And my Celeron with a ZX chipset is immune.
I've seen them on just about
On Sun, 16 Jul 2000 11:41:37 -0700 (PDT), "Rodney W. Grimes"
[EMAIL PROTECTED] said:
Ohh... and a finally note, DEC blew the chip design by only including
a 160byte threshold point given that PCI 2.0 spec says it should have
been 500bytes!!
It wouldn't be the first thing DEC had screwed up
On Sun, 16 Jul 2000 11:41:37 -0700 (PDT), "Rodney W. Grimes"
[EMAIL PROTECTED] said:
Ohh... and a finally note, DEC blew the chip design by only including
a 160byte threshold point given that PCI 2.0 spec says it should have
been 500bytes!!
It wouldn't be the first thing DEC had
On Sun, 16 Jul 2000 11:41:37 -0700 (PDT), "Rodney W. Grimes"
[EMAIL PROTECTED] said:
Ohh... and a finally note, DEC blew the chip design by only including
a 160byte threshold point given that PCI 2.0 spec says it should have
been 500bytes!!
It wouldn't be the first thing DEC had
On Sun, 16 Jul 2000 11:41:37 -0700 (PDT), "Rodney W. Grimes"
[EMAIL PROTECTED] said:
Ohh... and a finally note, DEC blew the chip design by only including
a 160byte threshold point given that PCI 2.0 spec says it should have
been 500bytes!!
It wouldn't be the first thing DEC had
On Fri, Jul 14, 2000 at 12:51:14PM +1000, Stephen McKay wrote:
On Thursday, 13th July 2000, "Rodney W. Grimes" wrote:
On Thu, 13 Jul 2000, Stephen McKay wrote:
Does anyone here actually measure these latencies? I know for a fact
that nothing I've ever done would or could be affected by
That theory is not correct, I have seen multiple Alpha machines reporting
buffer underruns as well. No ATA disk in sight there..
This has been a reported feature of the tulip chip and alphas (de driver
usually) forever forever forever.
It's not a bug, per se, IMO.
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Does anyone here actually measure these latencies? I know for a fact
that nothing I've ever done would or could be affected by extra latencies
that are as small as the ones we are discussing. Does anybody at all
depend on the
On Monday, 10th July 2000, Stefan Esser wrote:
On 2000-07-09 20:52 +1000, Stephen McKay [EMAIL PROTECTED] wrote:
On Saturday, 8th July 2000, Stefan Esser wrote:
Oh, there are renegotiations after each overrun ???
The code at the point that an underrun is detected is:
printf("dc%d: TX
On Thu, 13 Jul 2000, Stephen McKay wrote:
Guess it will show up if you measure latencies (or your application is
doing lots of RPCs). But as soon as there is a cheap 100baseT switch in
the path to the destination, there will be store-and-forward at work ;-)
Does anyone here actually measure
On Thu, 13 Jul 2000, Stephen McKay wrote:
Guess it will show up if you measure latencies (or your application is
doing lots of RPCs). But as soon as there is a cheap 100baseT switch in
the path to the destination, there will be store-and-forward at work ;-)
Does anyone here actually
On Thursday, 13th July 2000, "Rodney W. Grimes" wrote:
On Thu, 13 Jul 2000, Stephen McKay wrote:
Does anyone here actually measure these latencies? I know for a fact
that nothing I've ever done would or could be affected by extra latencies
that are as small as the ones we are discussing.
On Fri, 14 Jul 2000, Stephen McKay wrote:
place. I suspect an interaction between the ATA driver and VIA chipsets,
because other than the network, that's all that is operating when I see
the underruns. And my Celeron with a ZX chipset is immune.
I've noticed this on a VIA chipset machine.
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