Re: [Freedreno] [PATCH 3/3] drm/msm: gpu Add new gpu register read/write functions

On 11/23/2016 11:46 AM, Rob Clark wrote: > On Wed, Nov 23, 2016 at 2:34 PM, Stephen Boyd <sb...@codeaurora.org> wrote: >> On 11/22/2016 07:47 AM, Jordan Crouse wrote: >>> Add some new functions to manipulate GPU registers. gpu_read64 and >>> gpu_write64 can read/w

Re: [Freedreno] [PATCH] arm64: dts: Add Adreno GPU and GPU smmu definitions

On 12/02/2016 07:30 AM, Jordan Crouse wrote: > Add an initial node for the Adreno GPU and it's companion > SMMU. The GPU node is mostly complete except for a bare > bones power table that will be filled out more completely > later. > > Signed-off-by: Jordan Crouse > ---

Re: [Freedreno] [PATCH v5 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting spa...@codeaurora.org (2018-05-03 02:41:29) > On 2018-05-02 22:31, Stephen Boyd wrote: > > Quoting Sandeep Panda (2018-05-01 21:32:00) > >> diff --git > >> a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > >> b/Documentation/d

Re: [Freedreno] [PATCH v5 1/4] drm/bridge: add support for sn65dsi86 bridge driver

Quoting Sean Paul (2018-05-02 12:03:16) > On Wed, May 02, 2018 at 10:01:59AM +0530, Sandeep Panda wrote: > > > + struct drm_display_mode curr_mode; > > + struct mutex lock; > > + unsigned int ctrl_ref_count; > > +}; > > + > > +static const struct regmap_range

Re: [Freedreno] [PATCH v6 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting Sandeep Panda (2018-05-14 22:52:42) > diff --git > a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > new file mode 100644 > index 000..b82bb56 > --- /dev/null > +++

Re: [Freedreno] [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver

Quoting Sandeep Panda (2018-06-04 22:40:15) > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > new file mode 100644 > index 000..add6e0f > --- /dev/null > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -0,0 +1,666 @@ > +//

Re: [Freedreno] [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting Rob Herring (2018-06-05 08:20:50) > > + > > +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing > > + > > +- gpio-controller: Marks the device has a GPIO controller. > > +- #gpio-cells: Should be two. The first cell is the pin number and > > + the

Re: [Freedreno] [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting spa...@codeaurora.org (2018-06-05 21:50:16) > On 2018-06-05 20:50, Rob Herring wrote: > > On Tue, Jun 05, 2018 at 11:10:16AM +0530, Sandeep Panda wrote: > >> Document the bindings used for the sn65dsi86 DSI to eDP bridge. [...] > >> and > >> + the second cell is used to

Re: [Freedreno] [PATCH v9 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting Rob Herring (2018-06-13 08:03:53) > On Wed, Jun 13, 2018 at 5:08 AM, Sandeep Panda wrote: > > +Optional properties: > > +- interrupts: Specifier for the SN65DSI86 interrupt line. > > + > > +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing > > + > > +-

Re: [Freedreno] [PATCH v5 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting Sandeep Panda (2018-05-01 21:32:00) > diff --git > a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > new file mode 100644 > index 000..0d042ce > --- /dev/null > +++

Re: [Freedreno] [PATCH 01/33] clk_ops: change round_rate() to return unsigned long

On 12/31, Bryan O'Donoghue wrote: > On 30/12/17 16:36, Mikko Perttunen wrote: > >FWIW, we had this problem some years ago with the Tegra CPU clock > >- then it was determined that a simpler solution was to have the > >determine_rate callback support unsigned long rates - so clock > >drivers that

Re: [Freedreno] [PATCH 01/33] clk_ops: change round_rate() to return unsigned long

On 01/02, Bryan O'Donoghue wrote: > On 02/01/18 19:01, Stephen Boyd wrote: > >On 12/31, Bryan O'Donoghue wrote: > >>On 30/12/17 16:36, Mikko Perttunen wrote: > >>>FWIW, we had this problem some years ago with the Tegra CPU clock > >>>- then it was dete

Re: [Freedreno] [PATCH v12 3/5] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting Sandeep Panda (2018-06-21 05:32:07) > diff --git > a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > new file mode 100644 > index ..c8b8f018356f > --- /dev/null > +++

Re: [Freedreno] [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

Quoting Jordan Crouse (2018-08-08 15:47:01) > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi > b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index cdaabeb3c995..9fb90bb4ea1f 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -323,5 +323,126 @@ >

[Freedreno] [PATCH] drm/msm/disp/dpu: Use proper define for drm_encoder_init() 'encoder_type'

DRM_MODE_ENCODER_DSI (integer 6) instead of DRM_MODE_CONNECTOR_DSI here, or we'll go out of bounds of the encoder array. Pass the right thing and everything is fine. Cc: Jeykumar Sankaran Cc: Jordan Crouse Cc: Sean Paul Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: St

Re: [Freedreno] [PATCH v14 2/2] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

> - Remove is-pluggable dt entry since this will not be needed anymore (Sean > Paul). > > Changes in v3: > - Remove irq-gpio dt entry and instead populate is an interrupt >property (Rob Herring). > > Changes in v4: > - Add link to bridge chip datasheet (Stephen Boyd) > - A

Re: [Freedreno] [PATCH 2/2] arm64: dts: sdm845: Support GPU/GMU

(I wrote an email that seems to have been lost) Quoting Jordan Crouse (2018-03-09 08:03:55) > On Fri, Mar 09, 2018 at 09:13:32AM +0530, Viresh Kumar wrote: > > On 08-03-18, 13:14, Jordan Crouse wrote: > > > It seems to me that performance_state has a direct relationship with genpd > > > which is

Re: [Freedreno] [PATCH 2/2] arm64: dts: sdm845: Support GPU/GMU

On Sun, Mar 11, 2018 at 10:52 PM, Viresh Kumar wrote: > On 09-03-18, 09:03, Jordan Crouse wrote: >> I don't think we are understanding each other. The GMU is a separate >> microcontroller. It is given a magic number (actually a combination of magic >> numbers) that it

Re: [Freedreno] [[RFC]DPU PATCH 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

Quoting Sandeep Panda (2018-04-19 10:56:06) > Document the bindings used for the sn65dsi86 DSI to eDP bridge. > > Changes in v1: > - Rephrase the dt-binding descriptions to be more inline with existing >bindings (Andrzej Hajda). > - Add missing dt-binding that are parsed by corresponding

Re: [Freedreno] [DPU PATCH 3/3] drm/msm/dp: add support for DP PLL driver

This patch is too big. Please split it up more. I have far too many review comments on it so it will help if you keep splitting the patch up into smaller parts that can be more easily reviewed and fixed. Quoting Chandan Uddaraju (2018-10-10 10:15:59) > diff --git

Re: [Freedreno] [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT

Quoting Matthias Kaehlcke (2018-11-02 14:45:34) > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm > *pll_10nm) > char clk_name[32], parent[32], vco_name[32]; > char parent2[32], parent3[32], parent4[32]; > struct clk_init_data vco_init = { > -

Re: [Freedreno] [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY

Quoting Matthias Kaehlcke (2018-11-02 14:45:33) > Allow the 10nm PHY driver to get the ref clock from the DT. > > Signed-off-by: Matthias Kaehlcke > --- > Documentation/devicetree/bindings/display/msm/dsi.txt | 4 > 1 file changed, 4 insertions(+) > > diff --git

Re: [Freedreno] [PATCH] drm/msm: Set dma maximum segment size for mdss

lock+0x214/0x608 > [ 12.269693] hardirqs last disabled at (67260): [] > do_debug_exception+0x5c/0x178 > [ 12.278820] softirqs last enabled at (67256): [] > __do_softirq+0x4d4/0x520 > [ 12.287510] softirqs last disabled at (67249): [] > irq_exit+0xa8/0x100 > [

Re: [Freedreno] [DPU PATCH 1/3] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845

Quoting Chandan Uddaraju (2018-10-10 10:15:57) > diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt > b/Documentation/devicetree/bindings/display/msm/dp.txt > new file mode 100644 > index 000..0155266 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dp.txt

Re: [Freedreno] [PATCH 1/2] dt-bindings: msm/dsi: Add ref clock for 10nm PHY

Quoting Matthias Kaehlcke (2018-11-14 14:42:52) > On Tue, Nov 06, 2018 at 03:09:40PM -0800, Stephen Boyd wrote: > > Quoting Matthias Kaehlcke (2018-11-02 14:45:33) > > > Allow the 10nm PHY driver to get the ref clock from the DT. > > > > > &

Re: [Freedreno] [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT

Quoting Matthias Kaehlcke (2018-11-14 14:24:43) > On Tue, Nov 06, 2018 at 03:11:48PM -0800, Stephen Boyd wrote: > > Quoting Matthias Kaehlcke (2018-11-02 14:45:34) > > > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm > > > *pll_10nm) > > &g

Re: [Freedreno] [PATCH v5 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT

wed-by: Douglas Anderson > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [PATCH v5 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

gt; Reviewed-by: Douglas Anderson > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-12-19 14:22:22) > On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote: > > Quoting Matthias Kaehlcke (2018-12-04 14:42:30) > > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c > > > b/drivers/gpu/drm/msm/dsi/pll

Re: [Freedreno] [PATCH v3 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs

Quoting Matthias Kaehlcke (2018-11-30 16:52:47) > Allow the PHY drivers to get the ref clock from the DT. > > Signed-off-by: Matthias Kaehlcke > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedeskt

Re: [Freedreno] [PATCH v3 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs

Quoting Matthias Kaehlcke (2018-11-30 16:52:53) > Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously > hardcoded in the PLL 'driver' for the 10nm PHY. > > Signed-off-by: Matthias Kaehlcke > Reviewed-by: Douglas Anderson > --- Reviewe

Re: [Freedreno] [PATCH v3 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY

Quoting Matthias Kaehlcke (2018-11-30 16:52:54) > Add 'xo_board' as ref clock for the DSI PHY, it was previously > hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Why is driver in quotes? > > Signed-off-by: Matthias Kaehlcke Reviewed-by:

Re: [Freedreno] [PATCH v3 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-12-04 09:35:49) > On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote: > > Quoting Matthias Kaehlcke (2018-11-30 16:52:48) > > > + > > > /* custom byte clock divider */ > > > struct clk_bytediv *byte

Re: [Freedreno] [PATCH v3 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-11-30 16:52:48) > Get the ref clock of the PHY from the device tree instead of > hardcoding its name and rate. Use default values if the ref > clock is not specified. > > Signed-off-by: Matthias Kaehlcke > --- > Changes in v3: > - use default name and rate if the

Re: [Freedreno] [PATCH v3 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-11-30 16:52:49) > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c > index 26e3a01a99c2b..4a84c69ca0b2b 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c > +++

Re: [Freedreno] [PATCH v3 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY

Quoting Matthias Kaehlcke (2018-11-30 16:52:52) > Add 'xo_board' as ref clock for the DSI PHYs, it was previously > hardcoded in the PLL 'driver' for the 28nm PHY. > > Signed-off-by: Matthias Kaehlcke > Reviewed-by: Douglas Anderson > --- Reviewe

Re: [Freedreno] [PATCH v4 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-12-04 14:42:28) > Get the ref clock of the PHY from the device tree instead of > hardcoding its name and rate. > > Signed-off-by: Matthias Kaehlcke > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing

Re: [Freedreno] [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-12-04 14:42:29) > Get the ref clock of the PHY from the device tree instead of > hardcoding its name and rate. > > Signed-off-by: Matthias Kaehlcke > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing

Re: [Freedreno] [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-12-04 14:42:30) > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c > index 71fe60e5f01f1..032bf3e8614bd 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c > +++

Re: [Freedreno] [PATCH v4 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT

Quoting Matthias Kaehlcke (2018-12-04 14:42:31) > Get the ref clock of the PHY from the device tree instead of > hardcoding its name and rate. > > Note: This change could break old out-of-tree DTS files that > use the 10nm PHY > > Signed-off-by: Matthias Kaehlcke > Reviewed-by: Douglas Anderson

Re: [Freedreno] [PATCH v18 1/5] iommu/arm-smmu: Add pm_runtime/sleep ops

Quoting Vivek Gautam (2018-12-02 22:43:38) > On Fri, Nov 30, 2018 at 11:45 PM Will Deacon wrote: > > > > On Thu, Nov 29, 2018 at 08:25:20PM +0530, Vivek Gautam wrote: > > > clk_bulk_get_all() seems like going only the OF way. > > > Is there another way here to have something common between ACPI >

Re: [Freedreno] [PATCH 4/4] drm/msm/gpu: Attach to the GPU GX power domain

Quoting Jordan Crouse (2018-11-21 07:00:06) > On Tue, Nov 20, 2018 at 11:54:46PM -0800, Stephen Boyd wrote: > > Quoting Jordan Crouse (2018-11-19 15:47:06) > > > @@ -1203,6 +1236,12 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, > > > struct device_node *node) > &g

Re: [Freedreno] [PATCH 4/4] drm/msm/gpu: Attach to the GPU GX power domain

Quoting Jordan Crouse (2018-11-19 15:47:06) > 99.999% of the time during normal operation the GMU is responsible > for power and clock control on the GX domain and the CPU remains > blissfully unaware. However, there is one situation where the CPU > needs to get involved: > > The power sequencing

Re: [Freedreno] [PATCH 1/4] drm/msm/a6xx: Remove unwanted regulator code

Quoting Jordan Crouse (2018-11-19 15:47:03) > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 546599a7ab05..51493f409358 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -646,9 +646,6 @@

Re: [Freedreno] [RFC 0/4] msm: clk: Define a special power domain for SDM845 GX

Quoting Jordan Crouse (2018-11-19 15:47:02) > The GPU GX domain on SDM845 is nominally managed by the GMU microcontroller > but there are certain circumstances when the CPU needs to be sure that the > GX headswitch is off. > > This RFC series adds a special modification for the GX power domain >

Re: [Freedreno] [PATCH v18 1/5] iommu/arm-smmu: Add pm_runtime/sleep ops

Quoting Vivek Gautam (2018-11-27 02:11:41) > @@ -1966,6 +1970,23 @@ static const struct of_device_id arm_smmu_of_match[] = > { > }; > MODULE_DEVICE_TABLE(of, arm_smmu_of_match); > > +static void arm_smmu_fill_clk_data(struct arm_smmu_device *smmu, > + const

[Freedreno] [PATCH] drm/msm/dpu: Convert to a chained irq chip

an Crouse Cc: Jayant Shekhar Cc: Rajesh Yadav Cc: Jeykumar Sankaran Signed-off-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 36 ++-- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/

Re: [Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

Quoting Rajendra Nayak (2019-01-03 00:45:53) > > On 12/29/2018 6:59 AM, Stephen Boyd wrote: > >> So I am guessing the conclusion is to use a fallback "operating-points-v2" > >> compatible*only* when we do have opp-hz along with qcom,level (as in the > >

Re: [Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

Quoting Rajendra Nayak (2018-12-20 20:52:34) > > On 12/21/2018 2:59 AM, Stephen Boyd wrote: > > Quoting Rob Herring (2018-12-19 15:47:25) > >> On Wed, Dec 19, 2018 at 4:40 PM Doug Anderson > >> wrote: > >>> On Wed, Dec 19, 2018 at 12:40 PM Doug And

Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: Use provided drm_minor to initialize debugfs

Quoting Sean Paul (2019-05-24 10:32:18) > From: Sean Paul > > Instead of reaching into dev->primary for debugfs_root, use the minor > passed into debugfs_init. > > This avoids creating the debug directory under /sys/kernel/debug/ and > instead creates the directory under the correct node in >

Re: [Freedreno] [PATCH v2] drivers: qcom: Add BCM vote macro to header

Quoting Jordan Crouse (2019-08-13 11:47:17) > On Wed, Aug 07, 2019 at 04:42:31PM -0700, Stephen Boyd wrote: > > Quoting Jordan Crouse (2019-08-05 13:33:46) > > > The macro to generate a Bus Controller Manager (BCM) TCS command is used > > > by the interconnect driver bu

Re: [Freedreno] [PATCH v2] drivers: qcom: Add BCM vote macro to header

Quoting Bjorn Andersson (2019-08-19 09:52:55) > On Wed 07 Aug 16:42 PDT 2019, Stephen Boyd wrote: > > > Quoting Jordan Crouse (2019-08-05 13:33:46) > > > The macro to generate a Bus Controller Manager (BCM) TCS command is used > > > by the interconnect driver

Re: [PATCH 2/7] dt-bindings: arm-smmu: Add Adreno GPU variant

Quoting Jordan Crouse (2019-08-20 12:06:27) > Add a compatible string to identify SMMUs that are attached > to Adreno GPU devices that wish to support split pagetables. > > Signed-off-by: Jordan Crouse > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.txt | 7 +++ > 1 file

Re: [PATCH v2] drivers: qcom: Add BCM vote macro to header

pecific file and into the header. > > Signed-off-by: Jordan Crouse > --- Acked-by: Stephen Boyd Unless this is supposed to be applied by me? BTW, I wonder why we need an rpm clk driver much at all nowadays, except maybe for the XO clk state. The big user, from what I can tell, is th

Re: [Freedreno] [PATCH] drm/msm: stop abusing dma_map/unmap for cache

1 : f000 x0 : >Call trace: > __iommu_dma_unmap+0xb8/0xc0 > iommu_dma_unmap_sg+0x98/0xb8 > put_pages+0x5c/0xf0 [msm] > msm_gem_free_work+0x10c/0x150 [msm] > process_one_work+0x1e0/0x330 > worker_thread+0x40/0x438 >

Re: [Freedreno] [PATCH] drm/msm: Use generic bulk clock function

Quoting Jordan Crouse (2019-07-25 09:53:55) > Remove the homebrewed bulk clock get function and replace it with > devm_clk_bulk_get_all(). > > Signed-off-by: Jordan Crouse > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing

Re: [Freedreno] [v2] msm: disp: dpu1: add support to access hw irqs regs depending on revision

Quoting Shubhashree Dhar (2019-11-13 21:56:16) > Current code assumes that all the irqs registers offsets can be > accessed in all the hw revisions; this is not the case for some > targets that should not access some of the irq registers. What happens if we read the irq registers that we "should

Re: [Freedreno] [PATCH v1 1/2] drm/panel: add support for rm69299 visionox panel driver

Quoting Harigovindan P (2019-11-14 02:16:27) > diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c > b/drivers/gpu/drm/panel/panel-visionox-rm69299.c > new file mode 100644 > index 000..faf6d05 > --- /dev/null > +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c > @@ -0,0 +1,478 @@

Re: [Freedreno] [PATCH v1 0/2] Add suppport for rm69299 Visionox panel driver and add DSI config to support DSI version

Quoting Harigovindan P (2019-11-14 02:16:26) > Current patchset adds support for rm69299 visionox panel driver used in MSM > reference platforms > and also adds DSI config that supports the respective DSI version. > > The visionox panel driver supports a resolution of 1080x2248 with 4 lanes and

Re: [Freedreno] [PATCH] drm/msm/dpu: ignore NULL clocks

Quoting Rob Clark (2019-11-14 10:51:50) > From: Rob Clark > > This isn't an error. Also the clk APIs handle the NULL case, so we can > just delete the check. > > Signed-off-by: Rob Clark > Tested-by: Matthias Kaehlcke > ---

Re: [Freedreno] [PATCH v1] msm:disp:dpu1: add support for display for SC7180 target

Quoting Kalyan Thota (2019-11-18 02:47:43) > Add display hw catalog changes for SC7180 target. > > Changes in v1: > > 1) Configure register offsets and capabilities for the > display hw blocks. > > This patch has dependency on the below series > > https://patchwork.kernel.org/patch/11243111/ >

[Freedreno] [PATCH] drm/msm/dpu: Mark various data tables as const

These structures look like a bunch of data tables that aren't going to change after boot. Let's move them to the const RO section of memory so that they can't be modified at runtime on modern machines. Signed-off-by: Stephen Boyd --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 30

Re: [Freedreno] [PATCH RFC v2 5/5] ARM: dts: qcom: msm8974-hammerhead: add support for external display

Quoting Brian Masney (2019-10-06 18:45:09) > diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts > b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts > index b607c9ff9e12..380a805cd1f0 100644 > --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts > +++

Re: [Freedreno] [PATCH RFC v2 4/5] ARM: dts: qcom: msm8974: add HDMI nodes

Quoting Brian Masney (2019-10-06 18:45:08) > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi > b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 7fc23e422cc5..af02eace14e2 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > @@ -1335,6 +1342,77 @@ >

Re: [Freedreno] [PATCH RFC v2 4/5] ARM: dts: qcom: msm8974: add HDMI nodes

Quoting Brian Masney (2019-10-08 23:05:20) > On Tue, Oct 08, 2019 at 07:21:30PM -0700, Stephen Boyd wrote: > > Quoting Brian Masney (2019-10-06 18:45:08) > > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi > > > b/arch/arm/boot/dts/qcom-msm8974.dtsi > > &

Re: [Freedreno] [PATCH v2 1/3] dt-bindings: power: Convert Generic Power Domain bindings to json-schema

Quoting Krzysztof Kozlowski (2019-10-02 09:06:30) > Convert Generic Power Domain bindings to DT schema format using > json-schema. The consumer bindings are split to separate file. > > Signed-off-by: Krzysztof Kozlowski > > --- Acke

Re: [Freedreno] [PATCH 1/4] drm/msm/dpu: Remove unused function arguments

Quoting Drew Davenport (2020-02-19 09:42:24) > Several functions arguments in the resource manager are unused, so > remove them. > > Signed-off-by: Drew Davenport > --- Reviewed-by: Stephen Boyd > > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 37 ++

Re: [Freedreno] [PATCH 2/4] drm/msm/dpu: Refactor rm iterator

Quoting Drew Davenport (2020-02-19 09:42:25) > Make iterator implementation private, and add function to > query resources assigned to an encoder. > > Signed-off-by: Drew Davenport > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >

Re: [Freedreno] [v1] arm64: dts: sc7180: add display dt nodes

Quoting Harigovindan P (2020-01-21 07:52:08) > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi > b/arch/arm64/boot/dts/qcom/sc7180.dtsi > old mode 100644 > new mode 100755 > index 8011c5f..963f5c1 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@

Re: [Freedreno] [PATCH v2] of_device: removed #include that caused a recursion in included headers

Quoting Hadar Gat (2020-04-16 02:49:03) > Both of_platform.h and of_device.h were included each other. > In of_device.h, removed unneeded #include to of_platform.h > and added include to of_platform.h in the files that needs it. > > Signed-off-by: Hadar Gat > --- Acked-by: S

Re: [Freedreno] [DPU PATCH v5 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon

Quoting Tanmay Shah (2020-03-31 17:30:27) > diff --git a/Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml > b/Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml > new file mode 100644 > index 000..761a01d > --- /dev/null > +++

Re: [Freedreno] [DPU PATCH v5 2/5] drm: add constant N value in helper file

Quoting Tanmay Shah (2020-03-31 17:30:28) > From: Chandan Uddaraju > > The constant N value (0x8000) is used by multiple DP There's one driver using it, not multiple. > drivers. Define this value in header file and use this > in the existing i915 display driver. > > Signed-off-by: Chandan

Re: [Freedreno] [DPU PATCH v5 4/5] drm/msm/dp: add support for DP PLL driver

Quoting Tanmay Shah (2020-03-31 17:30:30) > diff --git a/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c > b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c > new file mode 100644 > index 000..aa845d0 > --- /dev/null > +++ b/drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c > @@ -0,0 +1,401 @@ > +//

Re: [Freedreno] [v1] drm/bridge: ensure bridge suspend happens during PM sleep

igovindan P > --- Besides the subject: Reviewed-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [DPU PATCH v4 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon

Quoting Vara Reddy (2020-03-04 16:10:24) > From: Chandan Uddaraju > > Add bindings for Snapdragon DisplayPort and > display-port PLL driver. > > Changes in V2: > Provide details about sel-gpio > > Changes in V4: > Provide details about max dp lanes > Change the commit text > > Signed-off-by:

Re: [Freedreno] [v2] arm64: dts: sc7180: modify assigned clocks for sc7180 target

Subject could be "sc7180: update DPU assigned clocks" Quoting Krishna Manikandan (2020-03-16 04:02:42) > Add DISP_CC_MDSS_ROT_CLK and DISP_CC_MDSS_AHB_CLK > in the assigned clocks list for sc7180 target. Why? > > Signed-off-by: Krishna Manikandan Does this need a Fixes: tag? > --- >

Re: [Freedreno] [DPU PATCH v4 4/5] drm/msm/dp: add support for DP PLL driver

Quoting Vara Reddy (2020-03-04 16:10:27) > From: Chandan Uddaraju > > Add the needed DP PLL specific files to support > display port interface on msm targets. > > The DP driver calls the DP PLL driver registration. > The DP driver sets the link and pixel clock sources. > > Changes in v2: > --

Re: [Freedreno] [PATCH v5] drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets

Quoting Kuogee Hsieh (2020-09-04 12:54:39) > add event thread to execute events serially from event queue. Also > timeout mode is supported which allow an event be deferred to be > executed at later time. Both link and phy compliant tests had been > done successfully. > > Changes in v2: > - Fix

[Freedreno] [PATCH 2/2] drm/msm: Drop debug print in _dpu_crtc_setup_lm_bounds()

Paul Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 74

[Freedreno] [PATCH 1/2] drm/msm: Avoid div-by-zero in dpu_crtc_atomic_check()

Cc: Jordan Crouse Cc: Sean Paul Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/driver

[Freedreno] [PATCH 0/2] A couple drm/msm fixes

Two small fixes for an UBSAN warning and to make debugging a little easier. Stephen Boyd (2): drm/msm: Avoid div-by-zero in dpu_crtc_atomic_check() drm/msm: Drop debug print in _dpu_crtc_setup_lm_bounds() drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 10 +- 1 file changed, 5 insertions

Re: [Freedreno] [PATCH v3] drm/msm/dp: fixes wrong connection state caused by failure of link train

also replace ST_SUSPEND_PENDING with ST_DISPLAY_OFF. > > Changes in V2: > -- Add more information to commit message. > > Changes in V3: > -- change base > > Signed-off-by: Kuogee Hsieh > --- Any Fixes tag? Tested-by: Stephen Boyd _

Re: [Freedreno] [PATCH v4] drm/msm/dp: return correct connection status after suspend

ses link training failed > > Signed-off-by: Kuogee Hsieh > --- Can we add some sort of Fixes tag? Maybe the beginning of this DP driver support? Tested-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [PATCH] drm/msm/dp: fixes wrong connection state caused by failure of link train

Quoting khs...@codeaurora.org (2020-10-05 11:02:10) > >> + dp_del_event(dp_display, EV_DISCONNECT_PENDING_TIMEOUT); > >> + > >> dp_display_disable(dp_display, 0); > >> > >> rc = dp_display_unprepare(dp); > >> if (rc) > >> DRM_ERROR("DP display

Re: [Freedreno] [PATCH v2] drm/msm/dp: add opp_table corner voting support base on dp_ink_clk rate

Quoting Rajendra Nayak (2020-10-06 00:31:41) > > On 10/4/2020 3:56 AM, Kuogee Hsieh wrote: > > Set link rate by using OPP set rate api so that CX level will be set > > accordingly based on the link rate. > > > > Changes in v2: > > -- remove dev from dp_ctrl_put() parameters > > -- address review

Re: [Freedreno] [PATCH v6] arm64: dts: qcom: sc7180: Add Display Port dt node

Quoting Tanmay Shah (2020-08-17 15:53:00) > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi > b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 31b9217bb5bf..bf2f2bb1aa79 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -2440,6 +2447,71 @@

Re: [Freedreno] [PATCH v2] arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node

Quoting Tanmay Shah (2020-08-17 15:59:12) > This node defines alternate DP HPD functionality of GPIO. > > Signed-off-by: Tanmay Shah > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi >

Re: [Freedreno] [PATCH v1] arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node

Quoting Tanmay Shah (2020-08-17 15:45:27) > This node defines alternate DP HPD functionality of GPIO. > > Signed-off-by: Tanmay Shah > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 14 ++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi >

Re: [Freedreno] [PATCH v3] arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node

Quoting Tanmay Shah (2020-08-17 20:36:57) > This node defines alternate DP HPD functionality of GPIO. > > Signed-off-by: Tanmay Shah > --- Reviewed-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedeskt

Re: [Freedreno] [PATCH v3] drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets

Quoting Kuogee Hsieh (2020-08-18 14:15:46) > add event thread to execute events serially from event queue. Also > timeout mode is supported which allow an event be deferred to be > executed at later time. Both link and phy compliant tests had been > done successfully. > > Changes in v2: > - Fix

Re: [Freedreno] [PATCH] drm/msm: enable vblank during atomic commits

ned-off-by: Rob Clark > --- Tested-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [PATCH] drm/msm/dp: add voltage corners voting support base on dp link rate

Quoting Kuogee Hsieh (2020-09-29 10:10:26) > Set link rate by using OPP set rate api so that CX level will be set > accordingly base on the link rate. s/base/based/ > > Signed-off-by: Kuogee Hsieh > --- > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c > b/drivers/gpu/drm/msm/dp/dp_ctrl.c >

Re: [Freedreno] [PATCH] drm/msm/dp: fix incorrect function prototype of dp_debug_get()

nel test robot > Signed-off-by: Abhinav Kumar > --- Reviewed-by: Stephen Boyd Will the compliance testing parts be moved out of debugfs at some point? Just curious what the plan is there. ___ Freedreno mailing list Freedreno@lists.freedesktop

Re: [Freedreno] [PATCH v2] drm/msm/dp: fix incorrect function prototype of dp_debug_get()

2: > - add prototype for msm_dp_debugfs_init() > > Fixes: f913454aae8e ("drm/msm/dp: move debugfs node to > /sys/kernel/debug/dri/*/") > Reported-by: kernel test robot > Signed-off-by: Abhinav Kumar > --- Reviewed-by: Stephen Boyd _

Re: [Freedreno] [PATCH] drm/msm/dp: DisplayPort PHY compliance tests fixup

est link status process > > Signed-off-by: Tanmay Shah > --- Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Reviewed-by: Stephen Boyd ___ Freedreno mailing list Freedreno@lists.freedesktop.org htt

[Freedreno] [PATCH] drm/msm/dp: Sleep properly in dp_hpd_handler kthread

("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Signed-off-by: Stephen Boyd --- Based on msm-next-dp of https://gitlab.freedesktop.org/drm/msm.git drivers/gpu/drm/msm/dp/dp_display.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/

[Freedreno] [PATCH] drm/msm/dpu: Add newline to printks

Printk messages need newlines. Add it here. Cc: Abhinav Kumar Cc: Jeykumar Sankaran Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Freedreno] [PATCH v2] drm/msm/dp: return correct connection status after suspend

Quoting Kuogee Hsieh (2020-09-26 13:34:54) > At dp_pm_resume, reinitialize both dp host controller and hpd block dp_pm_resume() > so that hpd connection can be detected at realtime by reading hpd state > status register. Also hpd plug interrupt can be generated accordingly. Can you describe

Re: [Freedreno] [PATCH] drm/msm/dp: fixes wrong connection state caused by failure of link train

Quoting Kuogee Hsieh (2020-10-02 15:09:19) > Connection state is set incorrectly happen at either failure of link train > or cable plugged in while suspended. This patch fixes these problems. > This patch also replace ST_SUSPEND_PENDING with ST_DISPLAY_OFF. > > Signed-off-by: Kuogee Hsieh Any

Re: [Freedreno] [v1] drm/msm: add shutdown support for display platform_driver

Quoting Krishna Manikandan (2020-05-28 01:38:23) > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c > index e4b750b..7a8953f 100644 > --- a/drivers/gpu/drm/msm/msm_drv.c > +++ b/drivers/gpu/drm/msm/msm_drv.c > @@ -1322,6 +1322,18 @@ static int msm_pdev_remove(struct

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