On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon
christophe.l...@linaro.org wrote:
On 27 February 2014 14:58, Ramana Radhakrishnan ramra...@arm.com wrote:
Hi
I noticed that for T32 we don't allow any old register for DImode values.
The restriction of an even register is true only for ARM
On Fri, Mar 28, 2014 at 3:50 PM, Alan Lawrence alan.lawre...@arm.com wrote:
Final patch in series, adds new tests of the ARM TRN Intrinsics, that also
check
the execution results, reusing the test bodies introduced into AArch64 in
the
first patch. (These tests subsume the autogenerated ones
On Wed, Apr 23, 2014 at 2:06 PM, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon
christophe.l...@linaro.org wrote:
On 27 February 2014 14:58, Ramana Radhakrishnan ramra...@arm.com wrote:
Hi
I noticed that for T32 we don't allow any old
On Tue, Apr 22, 2014 at 7:26 AM, Zhenqiang Chen
zhenqiang.c...@linaro.org wrote:
Hi,
ARM trunk build fail from @209484, since it requires the argument of
GET_MODE_SIZE to be enum machine_mode.
gcc/gcc/config/arm/arm.c:21433:13: error: invalid conversion from
'int' to 'machine_mode'
On Wed, Apr 2, 2014 at 12:04 PM, Jiong Wang jiong.w...@arm.com wrote:
On 25/03/14 15:44, Richard Earnshaw wrote:
On 24/03/14 11:26, Jiong Wang wrote:
This patch enables tail call optimization for long call on arm.
Previously we have too strict check on arm_function_ok_for_sibcall and
be
distro configuration - testing came back clean.
Applied to trunk.
regards
Ramana
2014-04-10 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR debug/60655
* config/arm/arm.c (TARGET_CONST_NOT_OK_FOR_DEBUG_P): Define
(arm_const_not_ok_for_debug_p): Reject MINUS
4.9 changes for ARM / AArch64. Sorry it's taken me a while to get this
out but better late than never :)
Ok ?
Ramana
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.Index: htdocs/gcc-4.9/changes.html
===
RCS file: /cvs/gcc
On Tue, Apr 8, 2014 at 6:28 PM, Steve Ellcey sell...@mips.com wrote:
On Tue, 2014-04-08 at 10:10 +0200, Dominique Dhumieres wrote:
richi asked for a testcase for 60731, and since we didn't already
have support for tests using dlopen, I had to add it.
Does this approach make sense?
r209187
,
Merzlyakov Alexey
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
As subject says.
Applied as obvious.
Ramana
2014-04-07 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* gcc.target/arm/pr60657.c: Fix missing curly brace.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.Index: gcc/testsuite/ChangeLog
Sorry about the delayed review. I seem to have missed this earlier.
On Tue, Mar 25, 2014 at 12:21 PM, Eric Botcazou ebotca...@adacore.com wrote:
Hi,
because of popular demand we switched the Ada compiler to ZCX, i.e. table-
driven EH scheme, on ARM/Linux, only to discover that GCC doesn't
On Thu, Apr 3, 2014 at 9:22 PM, Jeff Law l...@redhat.com wrote:
As noted in the PR, there are a few insns in the ARM backend which use
const_int_operand as a predicate, but which have constraints like I or
M.
With the predicate accepting all constants, it's possible for a pass such as
On Thu, Mar 27, 2014 at 11:25 AM, Ramana Radhakrishnan ramra...@arm.com wrote:
Hi,
This is a partial fix for PR60655 where dwarf2out.c rejects NOT of a
value in const_ok_for_output_1. There is still a problem with the testcase
on armhf where we get operations of the form, const (minus
My first reaction is to wonder why this is this not a bug in the
shorten phase.
I don't think that code ever expected an alignment directive to be emitted
by ASM_OUTPUT_CASE_END :(
Fair point and it looks like this support came in when the support for
Thumb2 was added eons ago.
This
On Fri, Apr 4, 2014 at 1:35 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
In PR 60743 it is noted that the genautomata computation has increased a lot
in both size and time due to my recently added a53 scheduling additions.
This patch attempts to mitigate that by reducing the large
On Thu, Apr 3, 2014 at 2:27 PM, Charles Baylis
charles.bay...@linaro.org wrote:
Hi
This bug causes the compiler to create a Thumb-2 TBB instruction with
a jump table containing an out of range value in a .byte field:
whatever.s:148: Error: value of 256 too large for field of 1 bytes at 100
/gcc.target/arm/pr60650.c
...
+ asm (1\t.long );
This asm looks quite bogus, and with
asm ();
it ICEs the same way, can it be changed?
+ __builtin_unreachable ();
+}
+}
Jakub
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.diff --git a/gcc/testsuite
and verified that the correct multilibs are now chosen.
Applied to trunk as nearly obvious.
regards,
Ramana
2014-03-28 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/t-aprofile (MULTILIB_MATCHES): Correct A12 rule.
Index: gcc/config/arm/t-aprofile
On Tue, Mar 25, 2014 at 3:51 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This two-patch series adds scheduling information for the ARMv8-A Crypto
instructions on the Cortex-A53.
This first patch does some preliminary restructuring to allow the arm and
aarch64 backends to share
On Fri, Mar 28, 2014 at 5:18 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 28/03/14 14:18, Ramana Radhakrishnan wrote:
On Tue, Mar 25, 2014 at 3:51 PM, Kyrill Tkachov kyrylo.tkac...@arm.com
wrote:
Hi all,
This two-patch series adds scheduling information for the ARMv8-A Crypto
On Wed, Mar 19, 2014 at 9:55 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
In order to properly cost the rev16 instruction we need a new field in the
cost tables.
This patch adds that and specifies its value for the existing cost tables.
Since rev16 is used to implement the BSWAP
On Wed, Mar 19, 2014 at 9:56 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is the arm equivalent of patch [2/3] in the series that adds combine
patterns for the bitwise operations leading to a rev16 instruction.
It reuses the functions that were put in aarch-common.c to
On Wed, Mar 19, 2014 at 9:55 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch adds a recogniser for the bitmask,shift,orr sequence of
instructions that can be used to reverse the bytes in 16-bit halfwords (for
the sequence itself look at the testcase included in the patch).
On Tue, Mar 25, 2014 at 3:52 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
In ARMv8-A there's a general expectation that AESE/AESMC and AESD/AESIMC
sequences of the form:
AESE Vn, _
AESMC Vn, Vn
will issue both instructions in a single cycle on super-scalar
implementations. It
...@redhat.com
Ramana Radhakrishnan ramana.radhakrish...@arm.com
* dwarf2out.c (const_ok_for_output_1): Reject expressions containing a
NOT.
gcc/testsuite
DATE Ramana Radhakrishnan ramana.radhakrish...@arm.com
* gcc.c-torture/compile/pr60655-1.c: New test.
commit
gcc/
* config/arm/predicates.md (call_insn_operand): Add long_call check.
* config/arm/arm.md (sibcall, sibcall_value): Force the address to reg for
long_call.
* config/aarch64/aarch64.c (arm_function_ok_for_sibcall): Remove long_call
restriction.
config/arm/arm.c :)
The ARM parts
MEMORY_MOVE_COST is in the default target hook implementation for
TARGET_MEMORY_MOVE_COST :)
Ok for stage4 ? Just rebuilt the compiler (cc1 and cc1plus), built a few
large enough .i files that I had lying around saw no difference in code
generated as expected.
regards,
Ramana
DATE Ramana Radhakrishnan
On Fri, Mar 14, 2014 at 4:05 AM, Andrew Pinski pins...@gmail.com wrote:
On Wed, Feb 5, 2014 at 2:29 AM, Venkataramanan Kumar
venkataramanan.ku...@linaro.org wrote:
Hi Marcus,
+ ldr\\t%x2, %1\;str\\t%x2, %0\;mov\t%x2,0
+ [(set_attr length 12)])
This pattern emits an opaque sequence of
On Fri, Mar 7, 2014 at 10:24 AM, Christian Bruel christian.br...@st.com wrote:
Hi Ramana,
Thanks for your comments,
Please respin using plus_constant instead of gen_addsi3.
Here is my feeling about this:
I experimented on using plus_constant instead of gen_addsi3. But there
are cases
On Tue, Jan 28, 2014 at 3:37 AM, Zhenqiang Chen
zhenqiang.c...@linaro.org wrote:
On 28 January 2014 01:07, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Thu, Jan 16, 2014 at 5:44 AM, Zhenqiang Chen
zhenqiang.c...@linaro.org wrote:
Thanks for comments.
http://gcc.gnu.org/bugzilla
On Mon, Feb 24, 2014 at 9:11 AM, Christian Bruel christian.br...@st.com wrote:
This patch improves the one sent previously,
(http://gcc.gnu.org/ml/gcc-patches/2014-02/msg01159.html), to fix a few
more failures in the testsuite that could arise with shrink-wrap and
-fexceptions.
To recall,
On Wed, Mar 5, 2014 at 9:12 AM, Jakub Jelinek ja...@redhat.com wrote:
Hi!
arm_legitimize_address may be called with a TLS symbol referenced, even when
x is not itself a SYMBOL_REF. Most often it is something like:
(const:SI (plus:SI (symbol_ref:SI tlsvar) (const_int NNN)))
but generally it
-none-elf on a model with no regressions.
Ok for stage1 ?
regards
Ramana
DATE Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.diff --git a/gcc/config/aarch64/aarch64.c b/gcc
On Fri, Feb 28, 2014 at 2:42 AM, Joey Ye joey...@arm.com wrote:
Ping. OK for trunk and 4.8?
Ok if no regressions.
Ramana
-Original Message-
From: Joey Ye [mailto:joey...@arm.com]
Sent: 21 February 2014 19:32
To: gcc-patches@gcc.gnu.org
Subject: [patch] [arm] Fix PR60169 - thumb1
On Fri, Feb 28, 2014 at 7:16 AM, Joey Ye joey...@arm.com wrote:
This patch is a mirror copy from approved patch in glibc:
http://sourceware.org/ml/libc-alpha/2014-02/msg00741.html
OK to trunk, 4.8 and 4.7?
OK everywhere.
Ramana
ChangeLog.libgcc:
* config/arm/sfp-machine.h
(in this case we can only have atomic access to 8byte objects on 8 byte
aligned addresses).
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 2f06e42..aad420c 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -245,12
and a generally improved register allocation strategy.
Queued for stage1 after suitable testing including a bootstrap and
regression test in Thumb2 found no issues.
regards
Ramana
DATE Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/arm.c (arm_hard_regno_mode_ok): Loosen
On 02/26/14 01:54, Terry Guo wrote:
Hi There,
As the assembler directive .code 16 equals .thumb, this small patch is
going to redefine the ASM_APP_OFF in a cleaner way. Tested with GCC
regression test and no regressions. Is it OK to current trunk or shall we
wait until the release-branch mode
On Wed, Feb 19, 2014 at 11:19 PM, Andrew Pinski pins...@gmail.com wrote:
On Wed, Feb 19, 2014 at 3:17 PM, Renato Golin renato.go...@linaro.org wrote:
On 19 February 2014 11:58, Richard Sandiford
rsand...@linux.vnet.ibm.com wrote:
I agree that having an unrecognised asm shouldn't be a hard
On Wed, Feb 19, 2014 at 11:26 PM, Renato Golin renato.go...@linaro.org wrote:
On 19 February 2014 23:19, Andrew Pinski pins...@gmail.com wrote:
With the unified assembly format, you should not need those
.arm/.thumb and in fact emitting them can make things even worse.
If only we could get
Or, if ARM supports unaligned loads/stores using special instructions,
perhaps you should also benchmark the alternative of not realigning, but
instead making sure those unaligned instructions are used for the shadow
memory loads/stores in the asan prologue/epilogue.
I have tried to use
On Tue, Feb 18, 2014 at 9:09 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
The following patch-set contains the pipeline-independent changes to gcc
to support the APM XGene-1 and contains various enhancements derived from
real-world applications and benchmarks running on
-02-12 James Greenhalgh james.greenha...@arm.com
* config/arm/aarch-common-protos.h
(alu_cost_table): Fix spelling of extend.
* config/arm/arm.c (arm_new_rtx_costs): Fix spelling of extend.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
.
(cortexa15_extra_costs): Likewise.
(v7m_extra_costs): Likewise.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
On Mon, Feb 10, 2014 at 11:01 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patchlet adds the part numbers for the Cortex-A53 and A57 cores so that
they can be detected when parsing /proc/cpuinfo on AArch32 Linux systems.
This will allow the -mcpu=native machinery to detect
On Mon, Feb 3, 2014 at 3:56 PM, Renlin Li renlin...@arm.com wrote:
Hi all,
This patch will ensure testsuite/gcc.target/arm/fixed_float_conversion.c is
checked only when -mfpu=vfp3 -mfloat-abi=softfp is applicable for the
target.
Accordingly, two procs (check_effective_target_arm_vfp3_ok and
On Mon, Feb 3, 2014 at 11:39 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch updates the thumb2_movhi_insn pattern for the -mrestrict-it
rules. I had somehow missed it when doing the -mrestrict-it work last year,
and it is possible to generate a deprecated IT block form in
On 02/06/14 18:25, David Howells wrote:
Is it worth considering a move towards using C11 atomics and barriers and
compiler intrinsics inside the kernel? The compiler _ought_ to be able to do
these.
It sounds interesting to me, if we can make it work properly and
reliably. + gcc@gcc.gnu.org
On Thu, Jan 30, 2014 at 8:38 PM, Jakub Jelinek ja...@redhat.com wrote:
Hi!
For -Os, apparently ARM backend sometimes decides to push (up to 8?) dummy
registers to stack in addition to the registers that actually need to be
saved, in order to avoid extra instruction to adjust stack pointer.
On Thu, Jan 30, 2014 at 1:45 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch adds the rtx costs table for Cortex-A57 and sets its issue rate
properly in the arm backend.
Tested on arm-none-eabi on a model.
Ok for trunk?
In my view this is OK - this is just a tuning
On Tue, Feb 4, 2014 at 2:12 AM, Michael Hudson-Doyle
michael.hud...@linaro.org wrote:
Ping? I'm attaching a marginally cleaner version of the test. I've had
a look at integrating this into aapcs64.exp but got defeated in the
end. If go-torture-execute took a list of sources as
override appropriate parts of this option.
Ok with those changes.
Thanks,
Ramana
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
Ramana wrote:
Attached patch fixes this. Is this OK for trunk?
How has it been tested ?
I was hoping Linaro people could run their magical cbuild on it...
Ok if no regressions.
regards
Ramana
-Y
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
(arm_builtin_support_vector_misalignment): Likewise.
+
+2014-02-03 Yury Gribov tetra2...@gmail.com
+Kugan Vivekanandarajah kug...@linaro.org
+
+ * gcc.target/arm/vect-noalign.c: New file.
+
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
/ftest-armv7a-thumb.c: Change aramv7-a to armv7-a.
--
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.
On Mon, Feb 3, 2014 at 3:14 PM, Yury Gribov y.gri...@samsung.com wrote:
Additionally I'm not really sure
why there is an additional load from the constant pool here - what is
the constant in this case ?
Given it is atmost a 16 bit constant
surely that should be loaded with a single mov(w)
On Thu, Jan 23, 2014 at 3:16 PM, Yury Gribov y.gri...@samsung.com wrote:
Hi,
Julian Brown has proposed patch
(http://gcc.gnu.org/ml/gcc-patches/2013-06/msg01191.html) for the dreadful
push_minipool_fix error (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49423)
in June but it didn't seem to
On Fri, Jan 24, 2014 at 5:16 PM, Ian Bolton ian.bol...@arm.com wrote:
Hi there!
An existing optimisation for Thumb-2 converts t32 encodings to
t16 encodings to reduce codesize, at the expense of causing
redundant flag setting for ADD, AND, etc. This redundant flag
setting can have negative
On Fri, Dec 20, 2013 at 6:50 PM, Renlin Li renlin...@arm.com wrote:
Hi all,
This patch will add armv7ve support to gcc. Armv7ve is basically a armv7-a
architecture profile with Virtualization Extensions. Additional test cases
are also added.
With this patch and to keep backward
January 2014 19:56, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
Please also create a bugzilla entry for this and use the pr number here.
Ramana
Sent from Samsung Mobile
Original message
From: Zhenqiang Chen zhenqiang.c...@linaro.org
Date:
To: gcc-patches
On 21/01/14 10:52, James Greenhalgh wrote:
+ names passed from the commend line will be in ARGV, we want
s/commend/command.
Otherwise OK if no regressions.
Thanks,
Ramana
On Mon, Dec 30, 2013 at 3:23 AM, Yangfei (Felix) felix.y...@huawei.com wrote:
Thanks for the reply. I found it in GCC-4.8.
The gcc version I look at is GCC-4.7. Seems this pattern is not there for
this version.
That will be because this was added in time for GCC 4.8. If you need
to find such
On Wed, Dec 18, 2013 at 1:46 PM, Yvan Roux yvan.r...@linaro.org wrote:
Hi,
this patch from Vladimir fixes an ICE when compiling newlib in Thumb1.
It returns NO_REGS in THUMB_SECONDARY_OUTPUT_RELOAD_CLASS, the same
way we did for THUMB_SECONDARY_INPUT_RELOAD_CLASS.
This is OK if there are no
On 06/12/13 17:19, Kyrill Tkachov wrote:
Hi all,
Following the implementation of the Crypto intrinsics I posted earlier this
week, this patch implements the vceq_p64 and vtst_p64 intrinsics that operate on
the new poly64_t type. They do not have a regular form and can thus not be
autogenerated
On 18/12/13 11:46, Kyrill Tkachov wrote:
Hi all,
This patch adds the recently introduced cores to the t-aprofile multilib
machinery. The values added are cortex-a15.cortex-a7, cortex-a12, cortex-a57 and
cortex-a57.cortex-a53.
Tested arm-none-eabi on qemu and model.
Ok for trunk?
Ok.
Ramana
On Fri, Dec 6, 2013 at 5:35 PM, Tejas Belagod tbela...@arm.com wrote:
Hi,
The attached patch adds crypto types for instruction classificiation.
Tested on aarch64-none-elf. OK for trunk?
Ok but please work with Kyryll to make sure only one version of this
gets in, obviously.
Ramana
On Tue, Dec 3, 2013 at 1:46 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Ping?
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02351.html
Thanks,
Kyrill
Ok if no objections in 24 hours.
Ramana
On 26/11/13 09:44, Kyrill Tkachov wrote:
Ping?
Thanks,
Kyrill
On 19/11/13 17:04,
Yvan,
On Wed, Dec 11, 2013 at 10:35 AM, Yvan Roux yvan.r...@linaro.org wrote:
Hi Vladimir,
I've some regressions on ARM after this SP elimination patch, and they
are execution failures. Here is the list:
Pragmatically, I think it's time we turned LRA on by default now that
we are in stage3
On Mon, Jul 1, 2013 at 5:31 PM, Paulo Matos pma...@broadcom.com wrote:
Hi,
Near the start of schedule_block, find_modifiable_mems is called if
DONT_BREAK_DEPENDENCIES is not enabled for this scheduling pass. It seems on
c6x backend currently uses this.
However, it's quite strange that this
On Tue, Dec 10, 2013 at 9:44 PM, Maxim Kuvyrkov ma...@kugelworks.com wrote:
On 11/12/2013, at 5:17 am, Ramana Radhakrishnan ramana@googlemail.com
wrote:
On Mon, Jul 1, 2013 at 5:31 PM, Paulo Matos pma...@broadcom.com wrote:
Hi,
Near the start of schedule_block, find_modifiable_mems
On Wed, Dec 11, 2013 at 12:02 AM, Maxim Kuvyrkov ma...@kugelworks.com wrote:
On 11/12/2013, at 11:14 am, Ramana Radhakrishnan ramana@googlemail.com
wrote:
On Tue, Dec 10, 2013 at 9:44 PM, Maxim Kuvyrkov ma...@kugelworks.com wrote:
On 11/12/2013, at 5:17 am, Ramana Radhakrishnan ramana
On Tue, Dec 10, 2013 at 9:24 AM, Zhenqiang Chen zhenqiang.c...@arm.com wrote:
Ping?
This is definitely a bug. The LIB1ASMFUNCS defined in t-bpabi should not be
overridden by t-arm.
OK for 4.8 and trunk
This looks correct. Ok if no regressions for both 4.8 and trunk.
regards
Ramana
Sorry about the slow response. Been on holiday.
On 20/11/13 16:27, Renlin Li wrote:
Hi all,
This patch will make the arm back-end use vcvt for float to fixed point
conversions when applicable.
Test on arm-none-linux-gnueabi has been done on the model.
Okay for trunk?
+ (define_insn
On 04/12/13 16:05, Ian Bolton wrote:
Hi,
Currently, on ARM, you have to either call abort() or raise(SIGTRAP)
to achieve a handy crash.
This patch allows you to instead call __builtin_trap() which is much
more efficient at falling over because it becomes just a single
instruction that will
On Thu, Nov 21, 2013 at 5:09 PM, Martin Jambor mjam...@suse.cz wrote:
Hi,
the patch below enables IRA live-range splitting that later
facilitates shrink-wrapping also work on ppc64. The difference is
that while on x86_64 it was enough to look for single sets from a hard
register to a pseudo
On 11/11/13 11:11, Eric Botcazou wrote:
Hi,
this is something I forgot to submit right after submitting
http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01906.html
We want to use the standard t-elf fragment on VxWorks as well.
Tested on ARM/VxWorks, OK for the mainline?
Ok, please apply.
On 11/11/13 13:48, Kyrill Tkachov wrote:
Hi all,
My patch last Friday introduced a warning about reaching the end of a non-void
function which breaks bootstrap. On second thought, instead of breaking at the
end of the comparisons handling, we should just return instead.
Tested arm-none-eabi on
ChangeLog:
2013-11-01 Julian Brown jul...@codesourcery.com
Joey Ye joey...@arm.com
* config/arm/arm.c (arm_cortex_m_branch_cost): New.
(arm_v7m_tune): New.
(arm_*_tune): Add comments for Sched adj cost.
List all names here please rather than a regexp.
*
On 11/06/13 09:45, James Greenhalgh wrote:
Hi,
This patch is a respin of the aarch-common improvements to use a generic
search to find SETs and the variety of shifts, rather than relying on the
hope that we will find something well formed.
I've bootstrapped the patch on a chromebook with
On 11/08/13 13:34, Kyrill Tkachov wrote:
Hi all,
In arm_new_rtx_costs we need a break; statement after handling the comparisons
cases. Otherwise we fall through and compute garbage. This small patch adds
that.
Tested arm-none-eabi on qemu.
Ok for trunk?
Ok - thanks.
Ramana
On Wed, Oct 30, 2013 at 3:03 PM, Vladimir Makarov vmaka...@redhat.com wrote:
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58784
LRA has an old check of legitimate addresses. It was written before a newer
address decomposition code which makes more correct checks of
On Wed, Oct 30, 2013 at 3:03 PM, Vladimir Makarov vmaka...@redhat.com wrote:
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58784
LRA has an old check of legitimate addresses. It was written before a newer
address decomposition code which makes more correct checks of
- tested that the testcase works just fine.
Applied to trunk and will backport to the 4.8 branch in a day or so
after the auto-testers have had a chance to play with this.
regards
Ramana
2013-10-30 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/58854
* config/arm
Mans,
Can you please follow the guidelines as in
http://gcc.gnu.org/contribute.html ? Notably what's missing in your
submission here is
1. A changelog entry - well I'll create one for you . (see below)
2. A note on how this was tested and what impact this has on any
testcase that you have.
3. A
On Thu, Oct 31, 2013 at 12:29 AM, Cong Hou co...@google.com wrote:
On Tue, Oct 29, 2013 at 4:49 PM, Ramana Radhakrishnan
ramana@googlemail.com wrote:
Cong,
Please don't do the following.
+++ b/gcc/testsuite/gcc.dg/vect/
vect-reduc-sad.c
@@ -0,0 +1,54 @@
+/* { dg-require-effective
On 10/24/13 00:04, Kugan wrote:
Hi,
arm testcases neon-vcond-ltgt.c and neon-vcond-unordered.c fails in
Linaro 4.8 branch. It is not reproducable with trunk but it can happen.
Both neon-vcond-ltgt.c and neon-vcond-unordered.c scans for vbsl
instruction, with other vector instructions. However,
On 10/24/13 00:04, Kugan wrote:
Hi,
arm testcases neon-vcond-ltgt.c and neon-vcond-unordered.c fails in
Linaro 4.8 branch. It is not reproducable with trunk but it can happen.
Both neon-vcond-ltgt.c and neon-vcond-unordered.c scans for vbsl
instruction, with other vector instructions. However,
You are better off CCing the maintainers for such reviews. Let me do
that for you. I cannot approve or reject this patch but I have a few
comments as below.
On 10/29/13 09:22, Hurugalawadi, Naveen wrote:
diff -uprN '-x*.orig' mainline-orig/gcc/config/aarch64/aarch64.md
On 10/09/13 23:16, Christophe Lyon wrote:
Hi,
This patch is a first small sample of dejagnu-ization of my ARM Neon
intrinsics tests.
Thanks for attempting this and apologies for the slow response - I've
been busy with a few other things internally.
It's derived from my previous work at
On 10/29/13 12:15, Kyrill Tkachov wrote:
Hi all,
This patch adds the new rtx costs for the Cortex-A7 core as well as a new tuning
structure to contain it.
Tested arm-none-eabi on qemu and no benchmark regressions.
Ok for trunk?
Ok.
Ramana
Cong,
Please don't do the following.
+++ b/gcc/testsuite/gcc.dg/vect/
vect-reduc-sad.c
@@ -0,0 +1,54 @@
+/* { dg-require-effective-target sse2 { target { i?86-*-* x86_64-*-* } } } */
you are adding a test to gcc.dg/vect - It's a common directory
containing tests that need to run on multiple
...@arm.com
Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/t-aprofile: New file.
* config.gcc: Handle --with-multilib-list option.diff --git a/gcc/config.gcc b/gcc/config.gcc
index 605efc0..75ce74a 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3437,6 +3437,43 @@ case ${target
Can someone comment / approve it quickly so that we get AArch32 and AArch64
linux cross-builds back up ?
Ok.
Applied for Dehao as r203269 . Tests on arm came back ok.
Ramana
Thanks,
Richard.
regards
Ramana
Honza
Dehao
Honza
gcc/ChangeLog:
2013-10-03 Renlin Li renlin...@arm.com
* config/arm/arm-cores.def (cortex-a53): Use cortex tunning.
s/tunning/tuning.
Ok with that change.
Ramana
On 10/04/13 22:23, Jan Hubicka wrote:
On Fri, Oct 4, 2013 at 11:54 AM, Jan Hubicka hubi...@ucw.cz wrote:
I looked at this problem. Bug updated
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58619
This is a bug when updating block during tree-inline. Basically, it is
legal for *n to be NULL. E.g.
On 10/02/13 23:49, Rong Xu wrote:
Here is the new patch. Honaz: Could you take a look?
Thanks,
-Rong
On Wed, Oct 2, 2013 at 2:31 PM, Jan Hubicka hubi...@ucw.cz wrote:
Thanks for the suggestion. This is much cleaner than to use binary parameter.
Just want to make sure I understand it
On 10/01/13 08:42, Kugan wrote:
Hi,
I am attaching a patch that reverts Split shift di patterns (r197527) as
it introduced PR58578. I am also attaching a patch to add a testcase
based on this failiures.
No regression on qemu for arm-none-eabi and new testcase now passes.
Is this OK?
Thanks,
On 09/24/13 09:27, Yvan Roux wrote:
Hi,
this patch fix the scan-assembler pattern of
gcc.target/arm/atomic-comp-swap-release-acquire.c, which didn't
allowed aliases register and failed when enabling LRA where 'ip' is
used in the ldaex instruction.
Ok -
The changelog could just read :
And my main question is it possible to rely on this fact when
compiling with gcc and different levels of optimizations?
No it is not , the compiler (especially trunk) is free to use LR as a
temporary after epilogue has been generated at higher optimization
levels.
Is it
possible to generate
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