Re: [PATCH] RISC-V: Reorganize and rename combine patterns in autovec-opt.md

Committed, thanks Juzhe and Robin. On 2023/9/20 15:14, Robin Dapp wrote: Hi Lehua, this LGTM. Regards Robin -- Best, Lehua

[PATCH 1/3] [og13] OpenMP: Call cuMemcpy2D/cuMemcpy3D for nvptx for omp_target_memcpy_rect

From: Tobias Burnus This is a version of Tobias's mainline patch of the same name, merged to og13 and with the followup patch "libgomp: cuda.h and omp_target_memcpy_rect cleanup" folded in. A couple of merge conflicts have also been resolved, mostly regarding "gomp_update". Tobias's original

[PATCH 3/3] [og13] OpenMP: Support accelerated 2D/3D memory copies for AMD GCN

This patch adds support for 2D/3D memory copies for omp_target_memcpy_rect and "target update", using AMD extensions to the HSA API. This follows Tobias's similar patch for NVPTX (already present on mainline and higher up this patch series for og13). Support is also added for 1-dimensional

Re: [PATCH] RISC-V: Reorganize and rename combine patterns in autovec-opt.md

Hi Lehua, this LGTM. Regards Robin

[PATCH] middle-end: use MAX_FIXED_MODE_SIZE instead of precidion of TImode/DImode

Hi! On Tue, Sep 19, 2023 at 05:50:59PM +0100, Richard Sandiford wrote: > How about using MAX_FIXED_MODE_SIZE for things like this? Seems like a good idea. The following patch does that. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2023-09-20 Jakub Jelinek *

Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

Hi Lehua, I think this is better but still a bit weird :D Allowing constants and forcing them into registers unconditionally is slightly dubious as well, though. One thing that always sticks out is - how is 0 special? Wouldn't we want other constants as well? For reductions I think the

[Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS]

This bug is exposed when we support VLS integer conversion patterns. FAIL: c-c++-common/torture/pr53505.c execution. This is because incorrect vsetvl elimination by Phase 4: 10318: 0d207057vsetvli zero,zero,e32,m4,ta,ma 1031c: 5e003e57vmv.v.i

Re: [PATCH][_GLIBCXX_INLINE_VERSION] Fix

On Wed, 20 Sept 2023 at 05:51, François Dumont via Libstdc++ wrote: > > libstdc++: Remove std::constract_violation from versioned namespace Spelling mistake in contract_violation, and it's not std::contract_violation, it's std::experimental::contract_violation > > GCC expects this type to be in

[pushed] Darwin: Move checking of the 'shared' driver spec.

Tested on x86_64-darwin21, pushed to trunk, thanks Iain --- 8< --- This avoids a bunch of irrelevant diagnostics if the user passes '-shared' to gnatmake. Currently, we push '-dynamiclib' back onto the command line (since that is the Darwin spelling of 'shared') but this is not handled by

[PATCH 0/3] [og13] OpenMP: Accelerated 2D/3D host<->target memory copies

This series consists of support for accelerated 2D/3D memory copies for omp_target_memcpy_rect and "target update" directives, using underlying API-provided routines (CUDA for nVidia, or via an AMD-specific extension for HSA). One of the patches (by Tobias) is already on mainline, so this is a

[PATCH 2/3] [og13] OpenMP, NVPTX: memcpy[23]D bias correction

This patch works around behaviour of the 2D and 3D memcpy operations in the CUDA driver runtime. Particularly in Fortran, the "base pointer" of an array (used for either source or destination of a host/device copy) may lie outside of data that is actually stored on the device. The fix is to make

Re: [PATCH] RISC-V: Fixed ICE caused by missing operand

Committed, thanks Juzhe. On 2023/9/20 14:03, juzhe.zhong wrote: LGTM Replied Message FromLehua Ding Date09/20/2023 13:39 To gcc-patches@gcc.gnu.org Cc juzhe.zh...@rivai.ai ,

Re: [PATCH] RISC-V: Reorganize and rename combine patterns in autovec-opt.md

LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-20 15:03 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Reorganize and rename combine patterns in autovec-opt.md This patch reorganize and rename the combine patterns

[PATCH 2/2] tree-optimization/111489 - raise --param uninit-max-chain-len to 8

This raises --param uninit-max-chain-len to avoid a bogus diagnostic for the large testcase in PR111489. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/111489 * params.opt (-param uninit-max-chain-len=): Raise default to 8. *

[PATCH 1/2] tree-optimization/111489 - turn uninit limits to params

The following turns MAX_NUM_CHAINS and MAX_CHAIN_LEN to params which allows to experiment with raising them. For the testcase in PR111489 raising MAX_CHAIN_LEN from 5 to 8 avoids the bogus diagnostics at -O2, at -O3 we need a MAX_CHAIN_LEN of 6. Bootstrapped and tested on

Re: RFC: Introduce -fhardened to enable security-related flags

I'd like to provide some data-points on hardening-related flags, as I've spent some time with Sam documenting their usage across various distributions here[1]. I also attached the relevant file to this email for archiving purposes. tl'dr: the suggested flag selection for `-fhardened` is not only

[committed] openmp: Add omp::decl attribute support [PR111392]

Hi! This patch adds support for (so far C++) omp::decl attribute. For declare simd and declare variant directives it is essentially another spelling of omp::decl, except per discussions it is not allowed inside of omp::sequence attribute. For threadprivate, declare target, allocate and later

[PATCH] RISC-V: Reorganize and rename combine patterns in autovec-opt.md

This patch reorganize and rename the combine patterns in autovec-opt.md by category. There shouldn't be any functional changes. The current classification includes the following categories: - Combine op + vmerge to cond_op - Combine binop + trunc to narrow_binop - Combine extend + binop to

[Patch, fortran] PR68155 - ICE on initializing character array in type (len_lhs <> len_rhs)

Hi All, This is a straightforward patch that is adequately explained by the ChangeLog. Regtests fine - OK for trunk? Cheers Paul Fortran: Pad mismatched charlens in component initializers [PR68155] 2023-09-20 Paul Thomas gcc/fortran PR fortran/68155 * decl.cc (fix_initializer_charlen):

[PATCH V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

V2 Change: Use new method to simple move const 0 to vector. This patch support combining cond extend and reduce_sum to cond widen reduce_sum like combine the following three insns: (set (reg:RVVM2HI 149) (const_vector:RVVM2HI repeat [ (const_int 0) ])) (set

[PATCH, rs6000] Enable vector compare for 16-byte memory equality compare [PR111449]

Hi, This patch enables vector compare for 16-byte memory equality compare. The 16-byte memory equality compare can be efficiently implemented by instruction "vcmpequb." It reduces one branch and one compare compared with two 8-byte compare sequence. 16-byte vector compare is not enabled on

Re: [RFC] GCC Security policy

This is a great initiative I think. See reference to AdaCore's security email below (among Debian, Red Hat, SUSE) On Mon, Aug 7, 2023 at 7:30 PM David Edelsohn via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > FOSS Best Practices recommends that projects have an official Security > policy

Re: [PATCH] middle-end: use MAX_FIXED_MODE_SIZE instead of precidion of TImode/DImode

On Wed, 20 Sep 2023, Jakub Jelinek wrote: > Hi! > > On Tue, Sep 19, 2023 at 05:50:59PM +0100, Richard Sandiford wrote: > > How about using MAX_FIXED_MODE_SIZE for things like this? > > Seems like a good idea. > > The following patch does that. > > Bootstrapped/regtested on x86_64-linux and

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Robin, I have posted a V2 patch to implement the method I mentioned. I wonder if that makes it a little easier to understand? V2 patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630985.html On 2023/9/20 12:02, Lehua Ding wrote: On 2023/9/20 6:02, Robin Dapp wrote: Hi

Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

> So, IMHO, a complicate pattern which combine initial 0 value + extension + > reduction + vmerge may be more reasonable. If that works I would also prefer that. Regards Robin

Re: [PATCH] Add a GCC Security policy

On Wed, Sep 20, 2023 at 07:50:43AM -0400, Siddhesh Poyarekar wrote: > +Support libraries such as libiberty, libcc1 libvtv and libcpp have Missing comma before libvtv. But more importantly, libvtv is not support library like libiberty, libcpp, it is more like the sanitizer libraries runtime

Re: [PATCH] Add a GCC Security policy

On Wed, Sep 20, 2023 at 07:58:04AM -0400, Siddhesh Poyarekar wrote: > On 2023-09-20 07:55, Jakub Jelinek wrote: > > On Wed, Sep 20, 2023 at 07:50:43AM -0400, Siddhesh Poyarekar wrote: > > > +Support libraries such as libiberty, libcc1 libvtv and libcpp have > > > > Missing comma before

[PATCH 2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases

This patch makes cond autovec testcase checks more restrict. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Assert of the number of vmerge. * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto. *

[PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

This patch adds combine cond_len_op and vec_cond to cond_len_op like cond_op. gcc/ChangeLog: * gimple-match.h (gimple_match_op::gimple_match_op): Add interfaces for more arguments. (gimple_match_op::set_op): Add interfaces for more arguments. * match.pd: Add

Re: [Patch] OpenMP: Add ME support for 'omp allocate' stack variables

On Mon, Sep 18, 2023 at 02:22:50PM +0200, Tobias Burnus wrote: > The attached patch now actually adds GOMP_alloc/free calls for 'omp allocate'. > > Besides the addition of the calls and the value expression, it also had to > deal with > (implicit) mapping/privatization - such that

[PATCH] Add a GCC Security policy

Define a security process and exclusions to security issues for GCC and all components it ships. Signed-off-by: Siddhesh Poyarekar --- Sending as a proper patch since there have been no further comments on the RFC. I toyed with the idea of making the distinction of "exploitable vulnerability"

[PATCH] OpenMP: Support accelerated 2D/3D memory copies for AMD GCN

This patch adds support for 2D/3D memory copies for omp_target_memcpy_rect and "target update", using AMD extensions to the HSA API. I've just committed a version of this patch to the og13 branch, but this is the mainline version. Support is also added for 1-dimensional strided accesses: these

Re: [PATCH] RISC-V: Support simplifying x/(-1) to neg for vector.

On 9/19/23 21:36, yanzhang.w...@intel.com wrote: From: Yanzhang Wang gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): support simplifying vector int not only scalar int. gcc/testsuite/ChangeLog: *

[PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar reduction.

Hi, as described in PR111401 we currently emit a COND and a PLUS expression for conditional reductions. This makes it difficult to combine both into a masked reduction statement later. This patch improves that by directly emitting a COND_ADD during ifcvt and adjusting some vectorizer code to

[PATCH] c++: missing SFINAE in grok_array_decl [PR111493]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This fixes some missed SFINAE in grok_array_decl when checking a C++23 multidimensional subscript operator expression. Note the existing pedwarn code paths are a backward compability fallback for treating

Re: [PATCH] Add a GCC Security policy

On 2023-09-20 07:55, Jakub Jelinek wrote: On Wed, Sep 20, 2023 at 07:50:43AM -0400, Siddhesh Poyarekar wrote: +Support libraries such as libiberty, libcc1 libvtv and libcpp have Missing comma before libvtv. But more importantly, libvtv is not support library like libiberty, libcpp, it is

[Committed] RISC-V: Support VLS floating-point extend/truncate

Regression passed. Committed. gcc/ChangeLog: * config/riscv/vector-iterators.md: Extend VLS floating-point. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Adapt test. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Ditto. *

Ping * 2: [V3][PATCH 1/3] Provide counted_by attribute to flexible array member field (PR108896)

Hi, I’d like to ping this patch set one more time. Thanks Qing > On Aug 25, 2023, at 11:24 AM, Qing Zhao wrote: > > Provide a new counted_by attribute to flexible array member field. > > 'counted_by (COUNT)' > The 'counted_by' attribute may be attached to the flexible array >

[PATCH] AArch64: Fix strict-align cpymem/setmem [PR103100]

The cpymemdi/setmemdi implementation doesn't fully support strict alignment. Block the expansion if the alignment is less than 16 with STRICT_ALIGNMENT. Clean up the condition when to use MOPS. Passes regress/bootstrap, OK for commit? gcc/ChangeLog/ PR target/103100 *

RE: [PATCH] RISC-V: Support simplifying x/(-1) to neg for vector.

Committed, thanks Jeff. Pan -Original Message- From: Jeff Law Sent: Wednesday, September 20, 2023 9:39 PM To: Wang, Yanzhang ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 Subject: Re: [PATCH] RISC-V: Support simplifying x/(-1) to neg for vector.

Re: [PATCH][RFC] middle-end/106811 - document GENERIC/GIMPLE undefined behavior

On Fri, 15 Sep 2023, Richard Biener via Gcc-patches wrote: > +@itemize @bullet > +@item > +When the result of negation, addition, subtraction or division of two signed > +integers or signed integer vectors not subject to @option{-fwrapv} cannot be > +represented in the type. It would be a bit

Re: [PATCH] c++: missing SFINAE in grok_array_decl [PR111493]

On Wed, 20 Sep 2023, Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > trunk? ... and perhaps 13? > > -- >8 -- > > This fixes some missed SFINAE in grok_array_decl when checking a C++23 > multidimensional subscript operator expression. > > Note

[PATCH 2/3] build: Add libgrust as compilation modules

From: Pierre-Emmanuel Patry Define the libgrust directory as a host compilation module as well as for targets. ChangeLog: * Makefile.def: Add libgrust as host & target module. * configure.ac: Add libgrust to host tools list. gcc/rust/ChangeLog: * config-lang.in: Add

[PATCH 1/3] librust: Add libproc_macro and build system

From: Pierre-Emmanuel Patry This patch series adds the build system changes to allow the Rust frontend to develop and distribute its own libraries. The first library we have been working on is the `proc_macro` library, comprised of a C++ library as well as a user-facing Rust library. Follow up

Re: [PATCH] Add a GCC Security policy

On 2023-09-20 08:29, Jakub Jelinek wrote: I just noticed (ENOCOFFEE) that the line (after removing libvtv) is: Support libraries such as libiberty, libcc1 and libcpp have been developed separately to share code with other tools such as binutils and gdb. Does that address your

Re: [PATCH] Add a GCC Security policy

On 2023-09-20 07:58, Siddhesh Poyarekar wrote: On 2023-09-20 07:55, Jakub Jelinek wrote: On Wed, Sep 20, 2023 at 07:50:43AM -0400, Siddhesh Poyarekar wrote: +    Support libraries such as libiberty, libcc1 libvtv and libcpp have Missing comma before libvtv.  But more importantly, libvtv is

Re: [PATCH] Add a GCC Security policy

On Wed, Sep 20, 2023 at 08:23:32AM -0400, Siddhesh Poyarekar wrote: > On 2023-09-20 07:58, Siddhesh Poyarekar wrote: > > On 2023-09-20 07:55, Jakub Jelinek wrote: > > > On Wed, Sep 20, 2023 at 07:50:43AM -0400, Siddhesh Poyarekar wrote: > > > > +    Support libraries such as libiberty, libcc1

PING *2: [V3][PATCH 2/3] Use the counted_by atribute info in builtin object size [PR108896]

Hi, I’d like to ping this patch set one more time. Thanks Qing > On Aug 25, 2023, at 11:24 AM, Qing Zhao wrote: > > Use the counted_by atribute info in builtin object size to compute the > subobject size for flexible array members. > > gcc/ChangeLog: > > PR C/108896 > *

Re: [PATCH][RFC] middle-end/106811 - document GENERIC/GIMPLE undefined behavior

On Wed, 20 Sep 2023, Richard Sandiford wrote: > Thanks for doing this. Question below... > > Richard Biener via Gcc-patches writes: > > The following attempts to provide a set of conditions GENERIC/GIMPLE > > considers invoking undefined behavior, leaning on the C standards > > Annex J, as to

PING * 2: [V3][PATCH 3/3] Use the counted_by attribute information in bound sanitizer[PR108896]

Hi, I’d like to ping this patch set one more time. Thanks Qing > On Aug 25, 2023, at 11:24 AM, Qing Zhao wrote: > > Use the counted_by attribute information in bound sanitizer. > > gcc/c-family/ChangeLog: > > PR C/108896 > * c-ubsan.cc (ubsan_instrument_bounds): Use counted_by

Re: [PATCH] Testsuite, DWARF2: adjust regexp to match darwin output

ping**2 > Hi, > > This was a painful one to fix, because I hate regexps, especially when they > are quoted. On darwin, we have this failure: > >FAIL: gcc.dg/debug/dwarf2/inline4.c scan-assembler > DW_TAG_inlined_subroutine[^(]*([^)]*)[^(]*(DIE >

Re: [PATCH][RFC] middle-end/106811 - document GENERIC/GIMPLE undefined behavior

Thanks for doing this. Question below... Richard Biener via Gcc-patches writes: > The following attempts to provide a set of conditions GENERIC/GIMPLE > considers invoking undefined behavior, leaning on the C standards > Annex J, as to provide portability guidance to language frontend >

PING * 2: [V3][PATCH 0/3] New attribute "counted_by" to annotate bounds for C99 FAM(PR108896)

Hi, I’d like to ping this patch set one more time! Thanks. Qing > On Aug 25, 2023, at 11:24 AM, Qing Zhao wrote: > > This is the 3rd version of the patch, per our discussion based on the > review comments for the 1st and 2nd version, the major changes in this > version are: > > ***Against

Re: [PATCH] c++: improve class NTTP object pretty printing [PR111471]

On Tue, 19 Sep 2023, Patrick Palka wrote: > On Tue, 19 Sep 2023, Jason Merrill wrote: > > > On 9/19/23 12:40, Patrick Palka wrote: > > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? > > > > OK for trunk. What's your argument for backporting? > > Thanks. I don't feel

Re: [PATCH v8 0/4] P1689R5 support

On Tue, Sep 19, 2023 at 17:33:34 -0400, Jason Merrill wrote: > Pushed, thanks! Thanks! Is there a process I can use to backport this to GCC 13? --Ben

Re: [PATCH] AArch64: Fix strict-align cpymem/setmem [PR103100]

On 20/09/2023 14:50, Wilco Dijkstra wrote: > > The cpymemdi/setmemdi implementation doesn't fully support strict alignment. > Block the expansion if the alignment is less than 16 with STRICT_ALIGNMENT. > Clean up the condition when to use MOPS. > > Passes regress/bootstrap, OK for commit? >

[PATCH] RISC-V: Remove math.h import to resolve missing stubs failures

Resolves some of the missing stubs failures: fatal error: gnu/stubs-lp64d.h: No such file or directory compilation terminated. 2023-09-20 Juzhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Remove unneeded math.h import. Tested-by: Patrick O'Neill

[Committed V4] internal-fn: Support undefined rtx for uninitialized SSA_NAME[PR110751]

According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 As Richard and Richi suggested, we recognize uninitialized SSA_NAME and convert it into SCRATCH rtx if the target predicate allows SCRATCH. It can help to reduce redundant data move instructions of targets like RISC-V.

[PATCH] [frange] Remove special casing from unordered operators.

In coming up with testcases for the unordered folders, I realized that we were already handling them correctly, even in the absence of my work in this area lately. All of the unordered fold_range() methods try to fold with the ordered variants first, and if they return TRUE, we are guaranteed to

Re: [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS]

Does it also happened on gcc 13 branch? If so plz backport :) Juzhe-Zhong 於 2023年9月20日 週三 11:09 寫道： > This bug is exposed when we support VLS integer conversion patterns. > > FAIL: c-c++-common/torture/pr53505.c execution. > > This is because incorrect vsetvl elimination by Phase 4: > >

Re: [Committed V4] internal-fn: Support undefined rtx for uninitialized SSA_NAME[PR110751]

On Wed, 20 Sep 2023 07:58:49 PDT (-0700), juzhe.zh...@rivai.ai wrote: According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 As Richard and Richi suggested, we recognize uninitialized SSA_NAME and convert it into SCRATCH rtx if the target predicate allows SCRATCH. It can help to

[PATCH v2] AArch64: Fix memmove operand corruption [PR111121]

A MOPS memmove may corrupt registers since there is no copy of the input operands to temporary registers. Fix this by calling aarch64_expand_cpymem_mops. Passes regress/bootstrap, OK for commit? gcc/ChangeLog/ PR target/21 * config/aarch64/aarch64.md

Re: [PATCH] c, c++, v3: Accept __builtin_classify_type (typename)

On Wed, 20 Sep 2023, Jakub Jelinek wrote: > On Mon, Sep 18, 2023 at 09:25:19PM +, Joseph Myers wrote: > > > I'd like to ping this patch. > > > The C++ FE part has been approved by Jason already with a minor change > > > I've made in my copy. > > > Are the remaining parts ok for trunk? > > >

Re: [PATCH V3] internal-fn: Support undefined rtx for uninitialized SSA_NAME

Juzhe-Zhong writes: > According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 > > As Richard and Richi suggested, we recognize uninitialized SSA_NAME and > convert it > into SCRATCH rtx if the target predicate allows SCRATCH. > > It can help to reduce redundant data move

Re: [PATCH][RFC] middle-end/106811 - document GENERIC/GIMPLE undefined behavior

Richard Biener writes: > On Wed, 20 Sep 2023, Richard Sandiford wrote: > >> Thanks for doing this. Question below... >> >> Richard Biener via Gcc-patches writes: >> > The following attempts to provide a set of conditions GENERIC/GIMPLE >> > considers invoking undefined behavior, leaning on the

Re: [PATCH] c++: missing SFINAE in grok_array_decl [PR111493]

On Wed, 20 Sep 2023, Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > trunk? > > -- >8 -- > > This fixes some missed SFINAE in grok_array_decl when checking a C++23 > multidimensional subscript operator expression. > > Note the existing pedwarn

Re: [PATCH] RISC-V: Fixed ICE caused by missing operand

LGTM Replied Message FromLehua DingDate09/20/2023 13:39 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,kito.ch...@gmail.com,rdapp@gmail.com,pal...@rivosinc.com,jeffreya...@gmail.com,lehua.d...@rivai.aiSubject[PATCH] RISC-V: Fixed ICE caused by missing operand

Re: [PATCH] debug/111409 - don't generate COMDAT macro sections for split DWARF

On Tue, Sep 19, 2023 at 11:02 PM Omar Sandoval wrote: > > On Tue, Sep 19, 2023 at 02:56:36PM +0200, Richard Biener wrote: > > On Thu, Sep 14, 2023 at 8:42 AM Omar Sandoval wrote: > > > > > > Split DWARF files aren't processed by the linker, so DW_MACRO_import > > > offsets aren't relocated and

[PATCH] c, c++, v3: Accept __builtin_classify_type (typename)

On Mon, Sep 18, 2023 at 09:25:19PM +, Joseph Myers wrote: > > I'd like to ping this patch. > > The C++ FE part has been approved by Jason already with a minor change > > I've made in my copy. > > Are the remaining parts ok for trunk? > > In the C front-end changes, since you end up discarding

Re: Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

I think both approaches look weird to me. Lehua is adding an const 0 move pattern which is only used by widen reduction is not ideal. Also, I don't like changing abs/vcond_mask predicate. So, IMHO, a complicate pattern which combine initial 0 value + extension + reduction + vmerge may be more

Re: [PATCH] c++: missing SFINAE in grok_array_decl [PR111493]

On 9/20/23 11:03, Patrick Palka wrote: On Wed, 20 Sep 2023, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This fixes some missed SFINAE in grok_array_decl when checking a C++23 multidimensional subscript operator expression.

[PATCH] c++: constraint rewriting during ttp coercion [PR111485]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk and perhaps backports? -- >8 -- In order to compare the constraints of a ttp with that of its argument, we rewrite the ttp's constraints in terms of the argument template's template parameters. The substitution to

Re: [PATCH] [frange] Remove special casing from unordered operators.

On 9/20/23 11:12, Aldy Hernandez wrote: In coming up with testcases for the unordered folders, I realized that we were already handling them correctly, even in the absence of my work in this area lately. All of the unordered fold_range() methods try to fold with the ordered variants first,

Re: [PATCH] c++: constraint rewriting during ttp coercion [PR111485]

On 9/20/23 13:10, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk and perhaps backports? OK for trunk and 13. -- >8 -- In order to compare the constraints of a ttp with that of its argument, we rewrite the ttp's constraints in terms of the

Re: [PATCH v2 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 9/19/23 20:30, waffl3x wrote: Thank you, this is great! Thanks! One legal hurdle to start with: our DCO policy (https://gcc.gnu.org/dco.html) requires real names in the sign-off, not pseudonyms. If you would prefer to contribute under this pseudonym, I encourage you to file a copyright

Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns

>> On a more general note, are we expecting #include to cause a >> testcase to fail? Well, actually I am not familiar with this stuff. We include match.h is because we need it. For example, CEIL/FLOOR,...etc. I don't know how to avoid those bogus failures. juzhe.zh...@rivai.ai From: Patrick

Re: Re: [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS]

Yes. We could wait for a more few days to backport. juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-09-21 00:41 To: Juzhe-Zhong CC: GCC Patches; Kito Cheng; Jeff Law; Robin Dapp Subject: Re: [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] Does it also happened on gcc 13 branch? If

[PATCH] LoongArch: Optimizations of vector construction.

gcc/ChangeLog: * config/loongarch/lasx.md (lasx_vecinit_merge_): New pattern for vector construction. (vec_set_internal): Ditto. (lasx_xvinsgr2vr__internal): Ditto. (lasx_xvilvl__internal): Ditto. * config/loongarch/loongarch.cc

[Committed] RISC-V: Support VLS INT <-> FP conversions

Support INT <-> FP VLS auto-vectorization patterns. Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. * config/riscv/vector-iterators.md: Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: *

[PATCH] MATCH: Simplify `(A ==/!= B) &/| (((cast)A) CMP C)`

This patch adds support to the pattern for `(A == B) &/| (A CMP C)` where the second A could be casted to a different type. Some were handled correctly if using seperate `if` statements but not if combined with BIT_AND/BIT_IOR. In the case of pr111456-1.c, the testcase would pass if

[PATCH] LoongArch: Optimizations of vector construction.

Change-Id: I327f68ab482b94073974e672c71d25c98b35a080 gcc/ChangeLog: * config/loongarch/lasx.md (lasx_vecinit_merge_): New pattern for vector construction. (vec_set_internal): Ditto. (lasx_xvinsgr2vr__internal): Ditto. (lasx_xvilvl__internal): Ditto.

[PATCH] check undefine_p for one more vr

Hi, The root cause of PR111355 and PR111482 is missing to check if vr0 is undefined_p before call vr0.lower_bound. In the pattern "(X + C) / N", (if (INTEGRAL_TYPE_P (type) && get_range_query (cfun)->range_of_expr (vr0, @0)) (if (...) (plus (op @0 @2) {

Re: [Patch, fortran] PR68155 - ICE on initializing character array in type (len_lhs <> len_rhs)

Hi Paul, On 9/20/23 09:03, Paul Richard Thomas wrote: Hi All, This is a straightforward patch that is adequately explained by the ChangeLog. Regtests fine - OK for trunk? this looks good to me. OK for trunk. As it is an almost obvious fix for sort of wrong code, I'd consider it

[COMMITTED] Tweak ssa_cache::merge_range API.

Merge_range use to return TRUE if there was already a range in the cache.   This patches change the meaning of the return value such that it returns TRUE if the range in the cache changes..  ie, it either set a range where there wasn't one before, or updates an existing range when the old one

Re: [PATCH] AArch64: Fix strict-align cpymem/setmem [PR103100]

Hi Richard, > * config/aarch64/aarch64.md (cpymemdi): Remove pattern condition. > Shouldn't this be a separate patch?  It's not immediately obvious that this > is a necessary part of this change. You mean this? @@ -1627,7 +1627,7 @@ (define_expand "cpymemdi" (match_operand:BLK 1

Re: [PATCH] RISC-V: Remove math.h import to resolve missing stubs failures

LGTM Patrick O'Neill 於 2023年9月20日 週三 18:07 寫道： > Resolves some of the missing stubs failures: > fatal error: gnu/stubs-lp64d.h: No such file or directory > compilation terminated. > > 2023-09-20 Juzhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/def.h:

[Committed] RISC-V: Remove math.h import to resolve missing stubs failures

Committed. Thanks! On 9/20/23 10:19, Kito Cheng wrote: LGTM Patrick O'Neill 於 2023年9月20日 週三 18:07 寫道： Resolves some of the missing stubs failures: fatal error: gnu/stubs-lp64d.h: No such file or directory compilation terminated. 2023-09-20 Juzhe Zhong

Re: [PATCH][_GLIBCXX_INLINE_VERSION] Fix

libstdc++: [_GLIBCXX_INLINE_VERSION] Add handle_contract_violation symbol alias libstdc++-v3/ChangeLog:     * src/experimental/contract.cc     [_GLIBCXX_INLINE_VERSION](handle_contract_violation): Provide symbol alias     without version namespace decoration for gcc. Here is what I'm

Re: [Committed] RISC-V: Support VLS unary floating-point patterns

Juzhe, On a more general note, are we expecting #include to cause a testcase to fail? My motivation is to make the testsuite less noisy when checking for regressions. For example, a patch like this one:

Re: [PATCH] aarch64: Ensure const and sign correctness

Pekka Seppänen writes: > Be const and sign correct by using a matching CIE augmentation type. > Use a builtin instead of relying being included. > > libgcc/ChangeLog: > > * config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): > Use const unsigned type and a builtin.

Re: [PATCH v2] c++: Catch indirect change of active union member in constexpr [PR101631]

On 9/19/23 20:55, Nathaniel Shead wrote: On Tue, Sep 19, 2023 at 05:25:20PM -0400, Jason Merrill wrote: On 9/1/23 08:22, Nathaniel Shead wrote: On Wed, Aug 30, 2023 at 04:28:18PM -0400, Jason Merrill wrote: On 8/29/23 09:35, Nathaniel Shead wrote: This is an attempt to improve the constexpr

Re: Ping: [PATCH] testsuite: Add test for already-fixed issue with _Pragma expansion [PR90400]

Lewis Hyatt via Gcc-patches writes: > Hello- > > May I please ping this one? It's adding a testcase prior to closing > the PR. Thanks! > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628488.html OK, thanks. (Not really my area, but someone would probably have objected by now if they

Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]

Thanks a lot. LGTM. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-09-21 11:12 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450] From: xuli When stride == element width, vlsse should be

Re: [PATCH] RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names

LGTM juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-21 11:44 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names This little rename

[PATCH] RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names

This little rename vector_gs_scale_operand_16/32 to more generic names const_1_or_2/4_operand. So it's a little better understood when offered for use elsewhere. gcc/ChangeLog: * config/riscv/predicates.md (const_1_or_2_operand): Rename. (const_1_or_4_operand): Ditto.

Re: [PATCH] RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names

Committed, thanks Juzhe. On 2023/9/21 11:45, juzhe.zh...@rivai.ai wrote: LGTM juzhe.zh...@rivai.ai *From:* Lehua Ding *Date:* 2023-09-21 11:44 *To:* gcc-patches

Re: [PATCH 1/2] using overflow_free_p to simplify pattern

Hi, Richard Biener writes: > On Tue, 19 Sep 2023, Jiufu Guo wrote: > >> Hi, >> >> In r14-3582, an "overflow_free_p" interface is added. >> The pattern of "(t * 2) / 2" in match.pd can be simplified >> by using this interface. >> >> Bootstrap & regtest pass on ppc64{,le} and x86_64. >> Is

Re: [PATCH] check undefine_p for one more vr

Hi, Richard Biener writes: >> Am 21.09.2023 um 05:10 schrieb Jiufu Guo : >> >> Hi, >> >> The root cause of PR111355 and PR111482 is missing to check if vr0 >> is undefined_p before call vr0.lower_bound. >> >> In the pattern "(X + C) / N", >> >>(if (INTEGRAL_TYPE_P (type) >> &&

[PATCH V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

V3 Change: Back to the original method. This patch support combining cond extend and reduce_sum to cond widen reduce_sum like combine the following three insns: (set (reg:RVVM2HI 149) (if_then_else:RVVM2HI (unspec:RVVMF8BI [ (const_vector:RVVMF8BI repeat [

Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum

Hi Robin and Juzhe, I changed to use the most original method, please see V3 as below: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631076.html On 2023/9/20 17:51, Robin Dapp wrote: So, IMHO, a complicate pattern which combine initial 0 value + extension + reduction + vmerge may

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