Hi Kito
Thanks for the suggestion. Sorry for late response due to stuck in the rest rvv
test files auto generation.
I have similar discuss with juzhe for this approach, and take Patch v2's way
due to the below concern.
1. The vector.md Is quite complicated already, the maintenance may be out
On Linux/x86_64,
03cebd304955a6b9c5607e09312d77f1307cc98e is the first bad commit
commit 03cebd304955a6b9c5607e09312d77f1307cc98e
Author: Jason Merrill
Date: Tue Apr 18 21:32:07 2023 -0400
c++: fix 'unsigned typedef-name' extension [PR108099]
caused
FAIL:
On 3/29/23 19:28, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns): Adapt
PASS.
This doesn't provide any useful information as far as I can tell.
Perhaps something like:
Erase AVL from instructions with the
On 3/27/23 19:01, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
{
vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
for (int i = 0; i < n; i++){
v = __riscv_vor_vx_i8mf4 (v, 101, 32);
v =
On 3/27/23 00:59, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
PR 108270
Fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
On 3/14/23 15:52, Michael Collison wrote:
While working on autovectorizing for the RISCV port I encountered an issue
where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
where GET_MODE_NUNITS is
On 3/23/23 19:53, Feng Wang wrote:
This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
[ ... ]
I've opened BZ109592 to track this problem.
jeff
On 3/23/23 19:53, Feng Wang wrote:
This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
int sextb32(int x)
{ return (x << 24) >> 24; }
The rtl expression is as follows,
(insn 6 3 7 2 (set (reg:SI 138)
(ashift:SI (subreg/s/u:SI
Any guidance on the next steps for this patch?
I believe that we answered all open questions, but may have missed something.
With trunk open for new development, we would like to revise and land this…
Thanks,
Philipp.
On Mon, 20 Mar 2023 at 15:02, Manolis Tsamis wrote:
>
> On Fri, Mar 17, 2023
On Fri, Apr 21, 2023 at 10:43:44PM +0200, Mikael Morin wrote:
> Hello,
>
> > --- gcc/gimple-range-op.cc.jj 2023-04-21 17:09:48.250367999 +0200
> > +++ gcc/gimple-range-op.cc 2023-04-21 18:37:26.048325391 +0200
> > @@ -439,20 +436,38 @@ public:
> > r.set_varying (type);
> > return
Hello,
--- gcc/gimple-range-op.cc.jj 2023-04-21 17:09:48.250367999 +0200
+++ gcc/gimple-range-op.cc 2023-04-21 18:37:26.048325391 +0200
@@ -439,20 +436,38 @@ public:
r.set_varying (type);
return true;
}
+
// Results outside of [-1.0, +1.0] are impossible.
On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
Current expansion of vmsge will make RA produce redundant vmv1r.v.
testcase:
void f1 (void * in, void *out, int32_t x)
{
vbool32_t mask = *(vbool32_t*)in;
asm volatile ("":::"memory");
vint32m1_t v =
On 3/16/23 03:39, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fix bug of vmsbc
OK. Please install on the trunk.
jeff
On 3/15/23 06:24, Christoph Muellner wrote:
From: Christoph Müllner
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for
On 3/13/23 02:28, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
For DEST EEW < SOURCE EEW, we can partial overlap register
according to RVV ISA.
gcc/ChangeLog:
* config/riscv/vector.md: Fix RA constraint.
gcc/testsuite/ChangeLog:
*
We cant represent ADDR_EXPR in ranges, so when we are processing
builtin_unreachable() we should not be removing comparisons that utilize
ADDR_EXPR during the early phases, or we lose some important information.
It was just an oversight that we think its a comparison to a
representable
On 3/13/23 03:05, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
According to RVV ISA:
14. Vector Reduction Operations
"The destination vector register can overlap the source operands, including the mask
register."
gcc/ChangeLog:
* config/riscv/vector.md: Refine RA constraint.
On 3/13/23 18:38, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fine tune vmadc/vmsbc RA constraint.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/narrow_constraint-13.c: New test.
*
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Swedish team of translators. The file is available at:
https://translationproject.org/latest/gcc/sv.po
(This file,
On 2/10/23 15:41, Philipp Tomsich wrote:
The vendor-defined XVentanaCondOps extension adds two instructions
with semantics identical to Zicond.
This plugs the 2 new instruction in using the canonical RTX, which
also matches the combiner-input for noce_try_store_flag_mask and
On 2/10/23 15:41, Philipp Tomsich wrote:
This adds the xventanacondops extension to the option parsing and as a
default for the ventana-vt1 core:
gcc/Changelog:
* common/config/riscv/riscv-common.cc: Recognize
"xventanacondops" as part of an architecture string.
*
On 2/10/23 15:41, Philipp Tomsich wrote:
While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can
trigger conversion into efficient branchless sequences
- with Zbs (bexti + neg + and)
- with Zicond (andi + czero.nez)
the inverted/negated case results in
andi a5,a0,1024
Jakub Jelinek writes:
> Doesn't fix any regression, so not ok for 13.1 and I wouldn't bother
> for 13.2 either.
Okay, but it can affect --enable-languages=all in a slim edge case.
Why not 13.2? It seems sufficiently simple.
Thanks, have a lovely night!
--
Arsen Arsenović
signature.asc
On 2/10/23 15:41, Philipp Tomsich wrote:
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what
r11-10018-g33914983cf3734c2f8079963ba49fcc117499ef3 fixed PR105312 and added
a test case for target/arm but the duplicate PR105573 has a test case for
target/sparc that was uncommitted until now.
2023-04-21 Sam James
PR tree-optimization/105312
PR target/105573
*
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
In the comments for PR108099 Jakub provided some testcases that demonstrated
that even before the regression noted in the patch we were getting the
semantics of this extension wrong: in the unsigned case we weren't producing
the
On 2/10/23 15:41, Philipp Tomsich wrote:
When if-conversion in noce_try_store_flag_mask starts the sequence off
with an order-operator, our patterns for czero.eqz/nez will receive
the result of the order-operator as a register argument; consequently,
they can't know that the result will be
On Fri, Apr 21, 2023 at 08:27:22PM +0200, Arsen Arsenović wrote:
> Hi Gaius,
>
> Gaius Mulley writes:
>
> > yes certainly this is fine. lgtm. Thanks for spotting and the patch
>
> Sure. Will push to master and wait for a RM to weigh in on 13.
Doesn't fix any regression, so not ok for 13.1
On Thu, Apr 20, 2023 at 02:59:35PM +0200, Jakub Jelinek via Gcc-patches wrote:
> Thanks for working on this. Though expectedly here we are running
> again into the discussions we had in November about math properties of the
> functions vs. numeric properties in their implementations, how big
On 4/21/23 13:07, Patrick Palka wrote:
On Sun, 4 Dec 2022, Patrick Palka wrote:
The functions strip_array_types, is_typedef_decl, typedef_variant_p,
cp_type_quals and cp_expr_location are used throughout the C++ frontend
including in some fairly hot parts (e.g. in the tsubst routines and
On 4/19/23 20:46, liuhongt via Gcc-patches wrote:
1547 /* If this insn loads a parameter from its stack slot, then it
1548 represents a savings, rather than a cost, if the parameter is
1549 stored in memory. Record this fact.
1550
1551 Similarly if we're loading other constants
On 1/16/23 18:12, Peter Foley wrote:
There's no reason to create this file if none of the serial configure
options are passed.
v2: Use test instead of [ to avoid running afoul of autoconf quoting.
ChangeLog:
* configure: Regenerate.
* configure.ac: Only create serdep.tmp if
Hi Gaius,
Gaius Mulley writes:
> yes certainly this is fine. lgtm. Thanks for spotting and the patch
Sure. Will push to master and wait for a RM to weigh in on 13.
Thanks!
--
Arsen Arsenović
signature.asc
Description: PGP signature
This test expected if-conversion to happen for a sequence which appears
to always cost more than a branchy sequence. This was exposed by a
recent change to the if-converter to add checking in a path where it was
missing.
So I've just adjusted the test to assume it should never if-convert
Arsen Arsenović writes:
> $(P) seems to have been a workaround for some old, proprietary make
> implementations that we no longer support. It was removed in
> r0-31149-gb8dad04b688e9c.
>
> gcc/m2/ChangeLog:
>
> * Make-lang.in: Remove references to $(P).
> * Make-maintainer.in:
Hi all,
Motivated by https://reviews.llvm.org/D148249, we can expand to a single
instruction
for the SMIN (x, 0) and SMAX (x, 0) cases using the combined AND/BIC and ASR
operations.
Given that we already have well-fitting TARGET_CSSC patterns and expanders for
the min/max codes
in the backend
Hi all,
A user has requested that we support the -mtp= option in aarch64 GCC for
changing
the TPIDR register to read for TLS accesses. I'm not a big fan of the option
name,
but we already support it in the arm port and Clang supports it for AArch64
already [1],
where it accepts the 'el0',
Hi all,
I finally got around to trying out the define_subst approach for PR
target/99195.
The problem we have is that many Advanced SIMD instructions have 64-bit vector
variants that
clear the top half of the 128-bit Q register. This would allow the compiler to
avoid generating
explicit
$(P) seems to have been a workaround for some old, proprietary make
implementations that we no longer support. It was removed in
r0-31149-gb8dad04b688e9c.
gcc/m2/ChangeLog:
* Make-lang.in: Remove references to $(P).
* Make-maintainer.in: Ditto.
---
Hi,
We spotted that the m2
Tamar Christina writes:
> Hi All,
>
> This patch adds support for a compact syntax for specifying constraints in
> instruction patterns. Credit for the idea goes to Richard Earnshaw.
>
> I am sending up this RFC to get feedback for it's inclusion in GCC 14.
> With this new syntax we want a clean
On Sun, 4 Dec 2022, Patrick Palka wrote:
> The functions strip_array_types, is_typedef_decl, typedef_variant_p,
> cp_type_quals and cp_expr_location are used throughout the C++ frontend
> including in some fairly hot parts (e.g. in the tsubst routines and
> cp_walk_subtree) and they're small
On Mon, 5 Dec 2022, Jason Merrill wrote:
> On 12/5/22 06:09, Prathamesh Kulkarni wrote:
> > On Mon, 5 Dec 2022 at 09:51, Patrick Palka via Gcc-patches
> > wrote:
> > >
> > > These functions currently repeatedly dereference tp during the subtree
> > > walk, dereferences which the compiler can't
Prathamesh Kulkarni writes:
> On Wed, 19 Apr 2023 at 16:17, Richard Biener
> wrote:
>>
>> On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni
>> wrote:
>> >
>> > On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni
>> > wrote:
>> > >
>> > > On Tue, 11 Apr 2023 at 14:17, Richard Biener
>> > >
On 4/19/23 00:05, Richard Biener wrote:
On Tue, Apr 18, 2023 at 10:51 PM Vineet Gupta wrote:
when debugging expmed.[ch] for PR/108987 saw that some of the cost arrays have
less than ideal layout as follows:
x_shift*cost[0..63][speed][modes]
We would want speed to be first index since a
On 4/21/23 09:03, Kito Cheng wrote:
You need use git+ssh protocol, I use this way to manage that:
git remote add upstream-write git+ssh://@gcc.gnu.org/git/gcc.git
git push upstream-write master
Thx Kito. That worked. I'll try to update the wiki.
-Vineet
On Sat, Apr 22, 2023 at 12:00 AM
You need use git+ssh protocol, I use this way to manage that:
git remote add upstream-write git+ssh://@gcc.gnu.org/git/gcc.git
git push upstream-write master
On Sat, Apr 22, 2023 at 12:00 AM Vineet Gupta wrote:
>
>
> On 4/21/23 02:30, Richard Sandiford wrote:
> > No approval is needed when
On 4/21/23 02:30, Richard Sandiford wrote:
No approval is needed when adding oneself to write-after-approval.
The fact that one's able to make the change is proof enough.
Thx Richard.
Noob question: I tried to commit/push but failed.
| $ git remote show upstream
| * remote upstream
|
"Victor L. Do Nascimento" writes:
> The backend pattern for storing a pair of identical values in 32 and
> 64-bit modes with the machine instruction STP was missing, and
> multiple instructions were needed to reproduce this behavior as a
> result of failed RTL pattern match in the combine pass.
>
On Fri, 21 Apr 2023 at 21:00, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi Richard,
> > Based on your suggestions in the other thread, the patch uses force_reg
> > to avoid creating pseudo if value is already in a register.
> > Bootstrap+test passes on aarch64-linux-gnu.
> >
> Hi,
> Ondrej Kubanek implemented profiling of loop histograms which sould be useful
> to improve
> i.e. quality of loop peeling of verctorization. However it turns out that
> most of histograms
> are lost on the way from profiling to loop peeling pass (about 90%). One
> common case is the
>
Prathamesh Kulkarni writes:
> Hi Richard,
> Based on your suggestions in the other thread, the patch uses force_reg
> to avoid creating pseudo if value is already in a register.
> Bootstrap+test passes on aarch64-linux-gnu.
> OK to commit ?
>
> Thanks,
> Prathamesh
>
> [aarch64] Use force_reg
install.texi needs some updates for GCC 13 and trunk:
* We used a mixture of Solaris 2 and Solaris references. Since Solaris
1/SunOS 4 is ancient history by now, consistently use Solaris
everywhere. Likewise, explicit references to Solaris 11 can go in
many places since Solaris 11.3 and
Hello All:
This patch is the new version of patch-3 to improve ree pass for rs6000 target.
Bootstrapped and regtested on power64-linux-gnu.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target
For rs6000 target we see redundant zero and sign
extension and done
Hi Richard,
Based on your suggestions in the other thread, the patch uses force_reg
to avoid creating pseudo if value is already in a register.
Bootstrap+test passes on aarch64-linux-gnu.
OK to commit ?
Thanks,
Prathamesh
[aarch64] Use force_reg instead of copy_to_mode_reg.
Use force_reg instead
On Fri, 21 Apr 2023 at 14:47, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi,
> > I tested the interleave+zip1 for vector init patch and it segfaulted
> > during bootstrap while trying to build
> > libgfortran/generated/matmul_i2.c.
> > Rebuilding with --enable-checking=rtl
Tested powerpc64le-linux. Pushed to gcc-12.
-- >8 --
The std::try_facet and std::use_facet functions were optimized in
r13-3888-gb3ac43a3c05744 to avoid redundant checking for all facets that
are required to always be present in every locale.
This performs a simpler version of the optimization
x86 was converted to TARGET_LEGITIMATE_ADDRESS_P long ago. Remove
remnants of the conversion. Also, cleanup the remaining macros a bit
by introducing INDEX_REGNO_P macro.
No functional change.
gcc/ChangeLog:
2023-04-21 Uroš Bizjak
* config/i386/i386.h (REG_OK_FOR_INDEX_P,
> > + if (!TARGET_SSE2)
> > +{
> > + if (c_dialect_cxx ()
> > + && cxx_dialect > cxx20)
>
> Formatting, both conditions are short, so just put them on one line.
Changed.
> But for the C++23 macros, more importantly I think we really should
> also in ix86_target_macros_internal add
> But for the C++23 macros, more importantly I think we really should
> also in ix86_target_macros_internal add
> if (c_dialect_cxx ()
> && cxx_dialect > cxx20
> && (isa_flag & OPTION_MASK_ISA_SSE2))
> {
> def_or_undef (parse_in, "__STDCPP_FLOAT16_T__");
>
There are quite some cases which want to access the control stmt
ending a basic-block. Since there cannot be debug stmts after
such stmt there's no point in using last_stmt which skips debug
stmts and can be a compile-time hog for larger testcases.
This is a first batch of changes, a second is
The following adds safe_is_a, an is_a check handling nullptr
gracefully.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* is-a.h (safe_is_a): New.
---
gcc/is-a.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/gcc/is-a.h b/gcc/is-a.h
index
This allows STL style iterator dereference. It's the same
as gsi_stmt () or .phi ().
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* gimple-iterator.h (gimple_stmt_iterator::operator*): Add.
(gphi_iterator::operator*): Likewise.
---
gcc/gimple-iterator.h | 4
Hi,
Ondrej Kubanek implemented profiling of loop histograms which sould be useful
to improve
i.e. quality of loop peeling of verctorization. However it turns out that most
of histograms
are lost on the way from profiling to loop peeling pass (about 90%). One
common case is the
following
Hi Pan:
One idea come to my mind, maybe we should add a new
define_insn_and_split pattern instead of change @pred_mov
On Fri, Apr 21, 2023 at 7:17 PM Li, Pan2 via Gcc-patches
wrote:
>
> Thanks kito, will try to reproduce this issue and keep you posted.
>
> Pan
>
> -Original Message-
>
Hello All:
This patch enable REE pass by default at O2 and above.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: Enable REE pass by default
Add ree pass as a default pass for rs6000 target for
O2 and above.
2023-04-21 Ajit
On Fri, 21 Apr 2023, Jakub Jelinek wrote:
> Hi!
>
> The following testcase ICEs on x86, foo function since my r14-22
> improvement, but bar already since r13-4122. The problem is the same,
> in the if expression related_vector_mode is called and that starts with
> gcc_assert (VECTOR_MODE_P
Hi,
This fixes another problem Michal noticed while working on incrmeental
WHOPR. The Fibonacci heap can change its behaviour quite significantly
for no good reasons when multiple edges with same key occurs. This is
quite common for small functions.
This patch stabilizes the order by adding
Hi!
The following testcase ICEs on x86, foo function since my r14-22
improvement, but bar already since r13-4122. The problem is the same,
in the if expression related_vector_mode is called and that starts with
gcc_assert (VECTOR_MODE_P (vector_mode));
but nothing in the fneg/fadd match.pd
Hi,
Michal Jires implemented quite well working prototype of cache for WPA which
makes
it to re-use partitions from from earlier build when package is rebulit with
smaller
changes. It should be useful to improve edit/compile/debug cycles when one is
forced to debug with LTO enabled but
The following relaxes the assert in vectorizable_live_operation
where we catch currently unhandled cases to also allow an
intermediate copy as it happens here but also relax the assert
to checking only.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
PR
Hi,
while working on incremental WHOPR with Michal Jires, we noticed that
there is code hashing LABEL_DECL_UID in lto-streamer-out which would
break the hash table, since label decls are not streamed and gets
re-initialized later.
The whole conditional is dead since LABEL_DECLs are not merged
This adjusts the remaining three RPO computes in DF. The DF_FORWARD
problems should use a RPO on the forward graph, the DF_BACKWARD
problems should use a RPO on the inverted graph.
Conveniently now inverted_rev_post_order_compute computes a RPO.
We still use post_order_compute and reverse its
The following changes the inverted_post_order_compute API back to
a plain C array interface and computing a reverse post order since
that's what's always required. It will make massaging DF to use
the correct iteration orders easier. Elsewhere it requires turning
backward iteration over the
This changes DF to use RPO on the forward graph for DF_FORWARD
problems. While that naturally maps to pre_and_rev_postorder_compute
we use the existing (wrong) CFG order for DF_BACKWARD problems
computed by post_order_compute since that provides the required
side-effect of deleting unreachable
On 2023-04-21 02:52, Jakub Jelinek wrote:
On Thu, Apr 20, 2023 at 09:14:10PM -0400, Siddhesh Poyarekar wrote:
On 2023-04-20 13:57, Siddhesh Poyarekar wrote:
For bounds that aren't representable, one could get error bounds from
libm-test-ulps data in glibc, although I reckon those won't be
Thanks kito, will try to reproduce this issue and keep you posted.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, April 21, 2023 6:17 PM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng
; Wang, Yanzhang
Subject: Re: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1,
On Fri, Apr 21, 2023 at 10:54:51AM +0100, Richard Sandiford wrote:
> > I'm guessing the keyword here is 'trait' which I'm guessing is different
> > from a omp declare simd directive, which is why it's not required to
> > have a simdlen clause in an omp declare simd (see Jakub's comment).
>
>
I got a bunch of new fails including ICE for gcc testsuite, and some
cases are hanging there, could you take a look?
$ riscv64-unknown-linux-gnu-gcc
gcc.target/riscv/rvv/vsetvl/avl_single-92.c -O2 -march=rv32gcv
-mabi=ilp32
during RTL pass: expand
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without save-restore,
less stack memory can be reserved. This patch decouples stack allocation for
rv32e w/o save-restore and makes riscv_compute_frame_info more
"Andre Vieira (lists)" writes:
> On 20/04/2023 17:13, Richard Sandiford wrote:
>> "Andre Vieira (lists)" writes:
>>> On 20/04/2023 15:51, Richard Sandiford wrote:
"Andre Vieira (lists)" writes:
> Hi all,
>
> This is a series of patches/RFCs to implement support in GCC to be
Thanks, committed to trunk.
On Fri, Apr 21, 2023 at 5:19 PM wrote:
>
> From: Juzhe-Zhong
>
> Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
>
> Consider the following testcase:
> void f (void * restrict in, void * restrict out, int l, int n, int m)
> {
> for (int i = 0; i <
On 20/04/2023 17:13, Richard Sandiford wrote:
"Andre Vieira (lists)" writes:
On 20/04/2023 15:51, Richard Sandiford wrote:
"Andre Vieira (lists)" writes:
Hi all,
This is a series of patches/RFCs to implement support in GCC to be able
to target AArch64's libmvec functions that will
Kindly ping for the PATCH v2. Just FYI there will be some underlying
investigation based on this PATCH like VMSEQ.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 19, 2023 7:27 PM
To: 'Kito Cheng' ; 'juzhe.zh...@rivai.ai'
Cc: 'gcc-patches' ; 'Kito.cheng'
; Wang,
Palmer Dabbelt writes:
> On Thu, 20 Apr 2023 09:55:23 PDT (-0700), Vineet Gupta wrote:
>> ChangeLog:
>>
>> * MAINTAINERS (Write After Approval): Add myself.
>>
>> (Ref: <680c7bbe-5d6e-07cd-8468-247afc65e...@gmail.com>)
>>
>> Signed-off-by: Vineet Gupta
>> ---
>> MAINTAINERS | 1 +
>> 1
From: Juzhe-Zhong
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0; k < n; k++)
{
Prathamesh Kulkarni writes:
> Hi,
> I tested the interleave+zip1 for vector init patch and it segfaulted
> during bootstrap while trying to build
> libgfortran/generated/matmul_i2.c.
> Rebuilding with --enable-checking=rtl showed out of bounds access in
> aarch64_unzip_vector_init in following
From: Juzhe-Zhong
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0; k < n; k++)
{
Gerald Pfeifer writes:
> On Thu, 20 Apr 2023, Arsen Arsenović wrote:
>>> I understand, just am wondering whether and why the : is required? I
>>> don't think we are using this construct anywhere else?
>> Without them, this would happen:
>>
>> ~$ "${foo:=foo}"
>> bash: foo: command not
Hi Robin:
OK, Feel free to commit that to trunk.
and don't forgot to mention this:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109582
On Fri, Apr 21, 2023 at 3:45 PM Robin Dapp via Gcc-patches
wrote:
>
> > ../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute
> > `type'
From: Juzhe-Zhong
PR 108270
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0; k
From: Juzhe-Zhong
PR 108270
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0; k
The following fixes the initial order the LCM dataflow routines process
BBs. For a forward problem you want reverse postorder, for a backward
problem you want reverse postorder on the inverted graph.
The LCM iteration has very many other issues but this allows to
turn inverted_post_order_compute
> ../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute
> `type'
> make[3]: *** [Makefile:2528: s-attrtab] Error 1
>
>From 582c428258ce17ffac8ef1b96b4072f3d510480f Mon Sep 17 00:00:00 2001
From: Robin Dapp
Date: Fri, 21 Apr 2023 09:38:06 +0200
Subject: [PATCH] riscv: Fix
../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute
`type'
make[3]: *** [Makefile:2528: s-attrtab] Error 1
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
Pushed to r14-130.
在 2023/4/19 下午4:23, Peng Fan 写道:
The system based on musl has no '/lib64', so change it.
https://wiki.musl-libc.org/guidelines-for-distributions.html,
"Multilib/multi-arch" section of this introduces it.
gcc/
* config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER:
On Wed, 12 Apr 2023 at 14:29, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Thu, 6 Apr 2023 at 16:05, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > On Tue, 4 Apr 2023 at 23:35, Richard Sandiford
> >> > wrote:
> >> >> > diff --git
On Thu, 20 Apr 2023, Arsen Arsenović wrote:
>> I understand, just am wondering whether and why the : is required? I
>> don't think we are using this construct anywhere else?
> Without them, this would happen:
>
> ~$ "${foo:=foo}"
> bash: foo: command not found
> ~ 127 $ unset foo
> ~$
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New
function.
(class vlseg): New class.
(class vsseg): Ditto.
(class vlsseg): Ditto.
(class vssseg): Ditto.
(class seg_indexed_load): Ditto.
On Thu, Apr 20, 2023 at 09:14:10PM -0400, Siddhesh Poyarekar wrote:
> On 2023-04-20 13:57, Siddhesh Poyarekar wrote:
> > For bounds that aren't representable, one could get error bounds from
> > libm-test-ulps data in glibc, although I reckon those won't be
> > exhaustive. From a quick peek at
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-21 14:49
To: gcc-patches
CC: Juzhe-Zhong
Subject: [committed v2] RISC-V: Add local user vsetvl instruction elimination
[PR109547]
From: Juzhe-Zhong
This patch is to enhance optimization for auto-vectorization.
Before this patch:
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