LGTM, thanks for fixing that :)
On Tue, Sep 19, 2023 at 8:54 AM Tsukasa OI via Gcc-patches
wrote:
>
> From: Tsukasa OI
>
> riscv-builtins.cc includes riscv-cmo.def and riscv-scalar-crypto.def
> (making dependencies) but their dependencies must be explicitly defined at
> the configuration file,
I may missed that one time too, not on plane yet, but need to go bed
earlier due to my flight is in next day early morning...
On Mon, Sep 18, 2023 at 11:07 PM Palmer Dabbelt wrote:
>
> My flight to the Cauldron lands in the middle of the meeting, so I'm
> going to miss it. In theory it's all
LGTM
On Sun, Sep 17, 2023 at 10:07 AM Juzhe-Zhong wrote:
>
> This patch supports VLS reduction vectorization.
>
> It can optimize the current reduction vectorization codegen with current COST
> model.
>
> #define DEF_REDUC_PLUS(TYPE)\
> TYPE __attribute__ ((noinline,
this bugfix be backported to GCC 13 now? If so, how can I do it?
>
> On 2023/8/31 10:12, Lehua Ding wrote:
> > Committed to the trunk and backported to GCC 13 one week later.
> > Thanks Juzhe and Kito.
> >
> > On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
>
LGTM :)
On Mon, Sep 18, 2023 at 3:07 PM Juzhe-Zhong wrote:
>
> We have largely supportted VLS modes. Only move patterns of VLS modes are
> different from VLS patterns. The rest of them are the same.
>
> We always extend the current VLA patterns with VLSmodes:
>
> VI --> V_VLSI
> VF --> V_VLSF
>
I think it's not make too much sense to back port GCC14's change to
GCC 13, removing phase 6 optimization is reasonable to me, so LGTM :)
On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai
wrote:
>
> Thanks for fixing it.
> I am ok remove phase 6 optimization which has many latent bugs (in
LGTM
On Mon, Sep 18, 2023 at 11:27 AM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to add the VLS support vec_set, both INT
> and FP are included.
>
> Give sample code as below:
>
> typedef long long vl_t \
> __attribute__((vector_size(2 * sizeof (long long;
>
I guess another solution is using reg_or_subregno instead of REGNO, but
that should not catch more cases, and just more run-time check, so this
version is LGTM.
LGTM
On Fri, Sep 15, 2023 at 1:06 PM Lehua Ding wrote:
> This patch refactors expand_reduction, remove the reduction_type argument
> and add insn_flags argument to determine the passing of the operands.
> ops has also been modified to restrict it to only two cases and to remove
> operand that
I am thinking what we are doing is something like we are allowing
scalar mode within the vector register, so...not sure should we try to
implement that within the mov pattern?
I guess we need some inputs from Jeff.
e.g.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index
LGTM
On Thu, Sep 14, 2023 at 11:51 PM Lehua Ding wrote:
>
> This patch add combine pattern to combine extend and reduce sum
> to widen reduce sum. The pattern in autovec.md was adjusted as
> needed. Note that the current vectorization cannot generate reduce
> openrand which is LMUL=M8, because
LGTM too :)
On Thu, Sep 14, 2023 at 10:11 PM 钟居哲 wrote:
>
> LGTM.
> It's obvious you fixed my previous redundant codes.
> Thanks.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Lehua Ding
> Date: 2023-09-13 20:31
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
LGTM
Juzhe-Zhong 於 2023年9月14日 週四 20:44 寫道：
> This patch support mask operations (comparison and logical).
>
> This patch reduce these FAILs of "vect" testsuite:
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"
> FAIL:
Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail
:P), maybe add a testcase pr111391-zve32x.c that just include
pr111391.c and set dg option to rv64gc_zve32x
On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai
wrote:
>
> You mean try pr111391.c
> that I added with
Could you check if it work correctly for rv64gcv_zve32x? add testcase
no matter if it works or not :)
On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
wrote:
>
> Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in
> vec_extract optab ?
>
>
>
> juzhe.zh...@rivai.ai
>
>
On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of
> pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch
lgtm
On Thu, Sep 14, 2023 at 3:52 PM Juzhe-Zhong wrote:
>
> update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.
>
> This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE
>
> update v2 -> v3: Remove redundant format.
>
> PR target/111395
>
>
LGTM with a minor comment.
> @@ -4054,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const
> bb_info *bb) const
> }
>
>/* Step1: Reshape the VL/VTYPE status to make sure everything compatible.
> */
> - auto_vec pred_cfg_bbs = get_dominated_by
> (CDI_POST_DOMINATORS,
LGTM, thanks :)
On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote:
>
> This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
> to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
>
LGTM
On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote:
>
> This patch add combine patterns to combine vfsgnj.vv + vcond_mask
> to mask vfsgnj.vv. For vfsgnjx.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
> *
LGTM
On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding wrote:
>
> This patch add combine patterns to combine vnsra.w[vxi] + vcond_mask
> to a mask vnsra.w[vxi].
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md
> (*cond_vtrunc):
> New combine pattern.
> (*cond_trunc):
LGTM :)
On Wed, Sep 13, 2023 at 2:07 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> When the mode switching from NONE to CALL, we will restore the
> frm but lack some check if we have static frm insn in cfun.
>
> This patch would like to fix this by adding static frm insn check.
>
>
lgtm
On Wed, Sep 13, 2023 at 11:23 AM Juzhe-Zhong wrote:
>
> We only support and report warning for RVV types.
>
> We don't report warning for GNU vectors.
> So this testcase checking is incorrect and the FAIL is bogus.
>
> Remove it and commit it.
>
> gcc/testsuite/ChangeLog:
>
> *
LGTM
On Tue, Sep 12, 2023 at 4:58 PM Lehua Ding wrote:
>
> This patch adds all missed cond autovec testcases. For not support
> cond patterns, the following patches will be sent to fix it.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Add vrem op.
>
LGTM, thanks for implement this :)
On Tue, Sep 12, 2023 at 10:16 AM juzhe.zh...@rivai.ai
wrote:
>
> Thanks for support it.
> LGTM from my side.
> Wait for kito's more comments.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Li Xu
> Date: 2023-09-12 10:08
> To: gcc-patches
> CC: kito.cheng; palmer;
LGTM, I think llvm and GCC are inconsistent for those intrinsics API
is really unfortunate...so really appreciate making those API align :)
And did you have plan to add riscv_crypto.h after updating/fixing all builtin?
On Tue, Sep 12, 2023 at 9:29 AM Tsukasa OI via Gcc-patches
wrote:
>
> From:
Hi Feng:
This version is LGTM, but I guess I would like to ask Jeff or another
global maintainer to approve that, anyway I'll follow up this in the
next gcc sync up meeting :)
On Fri, Sep 8, 2023 at 9:28 AM Feng Wang wrote:
>
> Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
Pushed to trunk, thanks :)
On Wed, Sep 6, 2023 at 5:41 PM Fei Gao wrote:
>
> Enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective.
>
> Fei Gao (2):
> allow targets to check shrink-wrap-separate enabled or not
> [V2][RISC-V] enable muti push and pop for Zcmp when
LGTM
On Mon, Sep 11, 2023 at 5:20 PM Juzhe-Zhong wrote:
>
> I just finished V2 version of LMUL cost model.
> Turns out we don't these redundant functions.
>
> Remove them.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (get_all_predecessors): Remove.
> (get_all_successors):
> @@ -545,7 +563,7 @@ struct move_def : public build_base
> /* According to rvv-intrinsic-doc, it does not add "_m" suffix
> for vop_m C++ overloaded API. */
> -if (overloaded_p && instance.pred == PRED_TYPE_m)
> +if (overloaded_p)
Just make sure it's the right change?
>
LGTM, and I guess you will remove get_all_predecessors once LMUL cost
model can use dominator info as well?
On Mon, Sep 11, 2023 at 11:34 AM Juzhe-Zhong wrote:
>
> I found that it's more reasonable to use existing dominance analysis.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc
OK, but could you split this patch into two patches? pre-approved for both.
On Mon, Sep 11, 2023 at 10:36 AM juzhe.zh...@rivai.ai
wrote:
>
> >> Should we also add loads and stores as well?
> >> and just make sure this is also necessary for the fix and not sneaky,
> >> right?
>
> No, we don't
> diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
> index d208b418e5f..6f48f7d6232 100644
> --- a/gcc/config/riscv/autovec-vls.md
> +++ b/gcc/config/riscv/autovec-vls.md
> @@ -148,6 +148,14 @@
>[(set_attr "type" "vmov")
> (set_attr "mode" "")])
>
>
LGTM
Juzhe-Zhong 於 2023年9月10日 週日 07:58 寫道：
> To make the dump FILE not too big, add TDF_DETAILS.
>
> This patch fix these following FAILs in
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311
>
> FAIL: gcc.c-torture/unsorted/dump-noaddr.c.*r.vsetvl, -O3
> -fomit-frame-pointer -funroll-loops
LGTM
Christoph Muellner 於 2023年9月8日 週五，14:00寫道：
> From: Christoph Müllner
>
> Recently three SPEC CPU 2017 benchmarks broke when using xtheadbb:
> * 500.perlbench_r
> * 525.x264_r
> * 557.xz_r
>
> Tracing the issue down revealed, that we emit a 'th.ext xN,xN,15,0'
> for a extendqi insn, which
LGTM
Juzhe-Zhong 於 2023年9月8日 週五 16:20 寫道：
> This patch fixes over 100+ bogus FAILs due to experimental vector ABI
> warning.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_pass_in_vector_p): Only allow RVV
> type.
>
> ---
> gcc/config/riscv/riscv.cc | 2 +-
> 1 file changed, 1
LGTM
Christoph Muellner 於 2023年9月8日 週五 14:16 寫道：
> From: Christoph Müllner
>
> The mode attribute of an extension pattern is usually set to the target
> type.
> Let's follow this convention consistently for xtheadbb.
>
> Signed-off-by: Christoph Müllner
>
> gcc/ChangeLog:
>
> *
LGTM
Juzhe-Zhong 於 2023年9月8日 週五 15:52 寫道：
> This patch fixes obvious bug: TARGET_MIN_VLEN is bitsize.
>
> All these following bugs are fixed with this patch:
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (internal compiler
> error: in gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL:
LGTM
Juzhe-Zhong 於 2023年9月7日 週四 11:36 寫道：
> This patch removes the incorrect earliest poset vsetvl optimization,
> such bug was found in vect-double-reduc-5.c which is runtime(execution
> fail) and also in PR111313.
>
> For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl
>
csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to the untyped zc instructions. Creates a new
> type "csr" for these instructions for now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr"
LGTM
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to vector instructions that were added after or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
>
LGTM
Edwin Lu 於 2023年9月7日 週四 01:52 寫道：
> This patch adds types to riscv instructions that were added or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Update types
>
> Signed-off-by:
LGTM
Edwin Lu 於 2023年9月7日 週四 01:53 寫道：
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu
> ---
>
Thanks for explaining, LGTM :)
On Mon, Sep 4, 2023 at 11:39 PM Lehua Ding wrote:
>
> Hi Kito,
>
> > Can those intermediate patterns be used for intrinsic? I would prefer
> > to keep those stuff *IF* possible used for intrinsics.
>
> I think we don't need those patterns for intrinisc. First, the
Pushed to trunk with few testcase modifications, e.g. adding { target
{ riscv_vector } } to dg-run and adding -march / -mabi for compile
tests.
On Tue, Sep 5, 2023 at 4:18 PM Kito Cheng wrote:
>
> Thanks for fixing the issue! I guess I could find time tonight to do
> the final round review and
Got failed on the trunk, could you take a look?
=== gcc: Unexpected fails for rv32imafdc ilp32d medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL:
On Wed, Sep 6, 2023 at 9:47 AM Fei Gao wrote:
>
> On 2023-09-05 20:02 Kito Cheng wrote:
> >
> >> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct
> >> riscv_frame_info *frame)
> >> {
> >>if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
> >>||
I saw RVC has MASK_RVC and TARGET_RVC in options.h?
On Wed, Sep 6, 2023 at 2:39 PM Feng Wang wrote:
>
> According to the doc, take“Mask(VECTOR_ELEN_32)
> Var(riscv_vector_elen_flags)”as example,
> it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate
> MASK_VECTOR_ELEN_32
>
Reading the manual again, it seems I missed something in the manual
before, the MASK syntax already says we can specify Var to select the
variable other than target_flags, but I tried that not work when we
only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32)
Var(riscv_vector_elen_flags)" still
,
but...it causes problems once using newer qemu (with that patch).
Fangrui Song 於 2023年9月6日 週三 04:53 寫道：
> On Tue, Sep 5, 2023 at 5:14 AM Kito Cheng via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
>
>> committed, thanks :)
>>
>> On Tue, Sep 5, 2023 at 3:18 PM J
committed, thanks :)
On Tue, Sep 5, 2023 at 3:18 PM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 8/31/23 03:05, Kito Cheng wrote:
> > We only emit that on linux target before, that not problem before,
> > however Qemu has fix a bug to make qemu user mode honor PT_GNU_STACK[1],
> > that will cause
> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct riscv_frame_info
> *frame)
> {
>if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
>|| cfun->machine->interrupt_handler_p || cfun->machine->varargs_size
> != 0
> - || crtl->args.pretend_args_size != 0
Hi Feng:
Thanks for the simplification, that reduces the effort of adding a new
extension!
Functional part looks good, but I think we may document that new
syntax at gcc/gcc/doc/options.texi
On Thu, Aug 31, 2023 at 11:32 AM Feng Wang wrote:
>
> This patch rebases the change of "[PATCH] RISC-V:
Thanks for fixing the issue! I guess I could find time tonight to do
the final round review and test :P then we could land this patch this
week.
On Tue, Sep 5, 2023 at 3:45 PM Lehua Ding wrote:
>
> V5 change: Rebase and fix vsetvl testcase fail by change
> `(unspec [...] UNSPEC_CALLEE_CC)` to
Can those intermediate patterns be used for intrinsic? I would prefer
to keep those stuff *IF* possible used for intrinsics.
On Mon, Sep 4, 2023 at 7:14 PM Lehua Ding wrote:
>
> This patch keep vlmax vector pattern in simple before split1 pass which
> will allow more optimization (e.g. combine)
LGTM
On Mon, Sep 4, 2023 at 3:18 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to add FP16 support for the VRGATHEREI16
> intrinsic. Aka:
>
> * __riscv_vrgatherei16_vv_f16mf4
> * __riscv_vrgatherei16_vv_f16mf4_m
>
> As well as f16mf2 to f16m8 types.
>
>
Maybe move the check logic a bit forward? My thought is the logic is
already specialized into a few catalogs, (imm, imm), (imm, reg), (reg,
reg)... and the logic you put is already in (imm, reg), but it should
really move into (reg, reg) case IMO? and move that forward we could
prevent add too
Ok
Pan Li via Gcc-patches 於 2023年9月2日 週六，16:54寫道：
> From: Pan Li
>
> This patch would like to allow the VLS mode autovec for the
> floating-point binary operation MAX/MIN.
>
> Given below code example:
>
> test (float *out, float *in1, float *in2)
> {
> for (int i = 0; i < 128; i++)
>
LGTM
On Thu, Aug 24, 2023 at 12:49 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination
>
> vfadd RTZ <- intrinisc static rounding
> vfmadd <- autovec/autovec-opt
>
> The autovec generated vfmadd should take DYN mode,
LGTM
On Thu, Aug 24, 2023 at 3:13 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfmsub <- autovec/autovec-opt
>
> The autovec generated vfmsub should take DYN mode,
LGTM, Awesome!! It seems a sign of the next big move for RISC-V vectorization!
On Thu, Aug 31, 2023 at 8:36 PM Robin Dapp wrote:
>
> OK. As it doesn't do anything and we'll be needing it anyway no harm
> in adding it.
>
> Regards
> Robin
Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...
On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding wrote:
>
> Because functions which follow vector calling convention variant has
> callee-saved vector reigsters but functions which follow
Ok, I just went through the patchlist and found this patch seems
not committed yet, anyway I will mark this as commit now :)
On Thu, Aug 31, 2023 at 5:14 PM Tsukasa OI via Gcc-patches
wrote:
>
> On 2023/08/31 18:10, Kito Cheng wrote:
> > Hi Tsukasa:
> >
> > I guess you might did something wrong
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
>
> This patch change the vsetvl policy to default policy
> (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
> fixed policy. Any policy is now returned, allowing change to agnostic
> or undisturbed. In the future,
Hi Tsukasa:
I guess you might did something wrong during commit this patch and
"RISC-V: Add stub support for existing extensions"
https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
On Tue, Aug 29, 2023 at 4:55 PM Tsukasa OI via Gcc-patches
wrote:
>
> On
We only emit that on linux target before, that not problem before,
however Qemu has fix a bug to make qemu user mode honor PT_GNU_STACK[1],
that will cause problem when we test baremetal with qemu.
So the straightforward is enable that as well for non-linux toolchian,
the price is that will
Thanks for the cleanup, the new interface is really much simpler than before!
Only few minor comment, you can go ahead to commit that after address
those comment.
(OK, I don't want to review whole patch again, it's really huge change :P
>
> - void set_rounding_mode (enum
OK for gcc 13 branch too, the general rule for backport is to wait one
week on trunk to make sure the fix is stable.
On Thu, Aug 31, 2023 at 8:08 AM juzhe.zh...@rivai.ai
wrote:
>
> Ok for trunk. But not sure whether it's ok for GCC-13.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Lehua Ding
> Date:
Pass regression without introducing any new fail, push to trunk :)
On Tue, Aug 29, 2023 at 4:39 PM Fei Gao wrote:
>
> Fei Gao (3):
> [RISC-V] support cm.push cm.pop cm.popret in zcmp
> [RISC-V] support cm.popretz in zcmp
> [RISC-V] support cm.mva01s cm.mvsa01 in zcmp
>
>
I would prefer NOT to expose those --param on user manual since
generally those options are used for internal only, we should add -m
option and enable `--param=riscv-autovec-preference=scalable` by
default once we think it's stable enough.
On Wed, Aug 30, 2023 at 1:04 PM Palmer Dabbelt wrote:
>
Lgtm
Juzhe-Zhong 於 2023年8月30日 週三，10:22寫道：
> Fix ICE in "vect" testsuite:
>
> FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record,
> at df-scan.cc:2958)
> FAIL: gcc.dg/vect/pr64495.c (test for excess errors
>
> After this patch, all current found VSETVL PASS related bugs in
> +/* To support misalign data movement, we should use
> + minimum element alignment load/store. */
> +unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (mode));
> +poly_int64 nunits = GET_MODE_NUNITS (mode) * size;
> +machine_mode mode = riscv_vector::get_vector_mode
LGTM, thanks :)
On Tue, Aug 29, 2023 at 6:50 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be one ICE when build vect-multitypes-5.c similar as below:
>
> riscv64-unknown-elf-gcc -O3 \
> -march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \
> -fdiagnostics-plain-output -flto
Hi Tatsuyuki:
Thanks your TLS desc implementation, it's looks already in good shape
now! just few minor comment :)
> @@ -121,6 +121,14 @@
> (T1_REGNUM 6)
> (S0_REGNUM 8)
> (S1_REGNUM 9)
> + (A0_REGNUM 10)
> +
LGTM, did you have commit access for GCC repo? you should obtain it if
you don't have it yet, I think you are already an important member of
the RISC-V GNU toolchain community :)
https://gcc.gnu.org/gitwrite.html#authenticated , and you can add me
to the cc list as your sponsor.
On Tue, Aug
Assuming prev is vsetvli instruction is kind of a strong assumption,
but it is guarded with gcc_assert, so it is a reasonable fix to me,
LGTM :)
On Tue, Aug 29, 2023 at 10:37 AM Juzhe-Zhong wrote:
>
> Fix bunch of ICE in "vect" testsuite:
> FAIL: gcc.dg/vect/vect-alias-check-16.c (internal
> 1. flag_shrink_wrap_separate seems better than flag_shrink_wrap.
(flag_)shrink_wrap_separate seems a sub optimization of
(flag_)shrink_wrap, so I am fine if flag_shrink_wrap_separate is
enough.
> 2. to pass the zcmp testcases, i will add fno-shrink-wrap-separate option.
OK
LGTM from my side, but I would like to wait Robin is ok too
Juzhe-Zhong 於 2023年8月28日 週一，19:43寫道：
> XPASS: gcc.dg/vect/no-scevccp-outer-12.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
> XPASS: gcc.dg/vect/no-scevccp-outer-16.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
>
LGTM
Juzhe-Zhong 於 2023年8月28日 週一 19:40 寫道：
> This patch fix unitialized probability in GIMPLE IR code tests:
> FAIL: gcc.dg/vect/slp-reduc-10a.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10a.c (test for excess
LGTM, that's much clearer than v1 to me :)
On Mon, Aug 28, 2023 at 5:54 PM Juzhe-Zhong wrote:
>
> This patch is fixing these bunch of ICE in "vect" testsuite:
> FAIL: gcc.dg/vect/no-scevccp-outer-2.c (internal compiler error: in
> anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
I would prefer to decouple the shrink-wrap part by checking
flag_shrink_wrap, I mean let disable zcmp code gen if flag_shrink_wrap
is true for now, and a follow up patch series with shrink-wrap.[cc|h]
changes?
On Mon, Aug 28, 2023 at 3:48 PM Fei Gao wrote:
>
> The first is a helper patch to
What about that? I guess I don't really know how to determine if a
block is EMPTY?
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 682f795c8e1..784ab184c72 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3282,6
Is it possible to skip that at the topper level like that?
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 682f795c8e1..654d25de593 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3269,7 +3269,7 @@
> @@ -11100,6 +11101,15 @@ proc check_vect_support_and_set_flags { } {
> }
> } elseif [istarget amdgcn-*-*] {
> set dg-do-what-default run
> +} elseif [istarget riscv64-*-*] {
> + if [check_effective_target_riscv_vector_hw] {
> + lappend
lgtm
On Fri, Aug 25, 2023 at 9:49 AM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfnmadd <- autovec/autovec-opt
>
> The autovec generated vfnmadd should take DYN
>
>- Phase 3 - Backward && forward demanded info propagation and fusion
> across
> blocks.
>
Need update comment here.
>- Phase 6 - Propagate AVL between vsetvl instructions.
Need update comment here too.
> +/* Return true if the current VSETVL is dominated by preceding
LGTM
On Thu, Aug 24, 2023 at 5:35 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfnmsub <- autovec/autovec-opt
>
> The autovec generated vfnmsub should take DYN
LGTM
Pan Li via Gcc-patches 於 2023年8月22日 週二 12:20 寫道：
> From: Pan Li
>
> Update in v2:
>
> * Added gcc_assert for vx format in binop.
> * Passed riscv/rvv.exp test.
>
> Original Log:
>
> As suggested by kito, we will add new frm_opt_type template arg
> to the op class, to avoid the duplicated
LGTM
Pan Li via Gcc-patches 於 2023年8月24日 週四 15:41 寫道：
> From: Pan Li
>
> Fix below typo for the pattern comment.
>
> vfmsac => vfnmsac
> vfmsub => vfnmsub
>
> Signed-off-by: Pan Li
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Fix typo.
> ---
> gcc/config/riscv/autovec.md | 6
It's really great improvement, it's drop some state like HARD_EMPTY
and DIRTY_WITH_KILLED_AVL which make this algorithm more easy to
understand!
also this also fundamentally improved the phase 3, although one
concern is the time complexity might be come more higher order,
(and it's already high
I think I could do some details review tomorrow on the plane, I am free
from the meeting hell tomorrow :p
Robin Dapp via Gcc-patches 於 2023年8月21日 週一 23:24
寫道：
> Hi Juzhe,
>
> thanks, this is a reasonable approach and improves readability noticeably.
> LGTM but I'd like to wait for other
Just one nit from me: plz add assertion to OP_TYPE_vx to make sure NO
FRM_OP == HAS_FRM there
On Mon, Aug 21, 2023 at 11:04 PM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 8/17/23 20:53, Pan Li via Gcc-patches wrote:
> > From: Pan Li
> >
> > As suggested by kito, we will add new frm_opt_type
lgtm
On Thu, Aug 17, 2023 at 2:23 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFREDOSUM.VS as the below samples.
>
> * __riscv_vfredosum_vs_f32m1_f32m1_rm
> * __riscv_vfredosum_vs_f32m1_f32m1_rm_m
>
> Signed-off-by: Pan
ok
On Thu, Aug 17, 2023 at 3:26 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFWREDOSUM.VS as the below samples
>
> * __riscv_vfwredosum_vs_f32m1_f64m1_rm
> * __riscv_vfwredosum_vs_f32m1_f64m1_rm_m
>
> Signed-off-by: Pan
LGTM, thanks :)
On Thu, Aug 17, 2023 at 1:59 PM Juzhe-Zhong wrote:
>
> void foo(_Float16 y, int64_t *i64p)
> {
> vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
> vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
> vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
> asm volatile ("# use %0 %1" : :
Lgtm
Pan Li via Gcc-patches 於 2023年8月17日 週四，11:09寫道：
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFREDUSUM.VS as the below samples.
>
> * __riscv_vfredusum_vs_f32m1_f32m1_rm
> * __riscv_vfredusum_vs_f32m1_f32m1_rm_m
>
> Signed-off-by: Pan Li
>
>
Lgtm
Pan Li via Gcc-patches 於 2023年8月17日 週四，10:19寫道：
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFNCVT.F.{X|XU|F}.W as the below samples.
>
> * __riscv_vfncvt_f_x_w_f32m1_rm
> * __riscv_vfncvt_f_x_w_f32m1_rm_m
> * __riscv_vfncvt_f_xu_w_f32m1_rm
> *
LGTM
On Thu, Aug 17, 2023 at 9:23 AM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFNCVT.XU.F.W as the below samples.
>
> * __riscv_vfncvt_xu_f_w_u16mf2_rm
> * __riscv_vfncvt_xu_f_w_u16mf2_rm_m
>
> Signed-off-by: Pan Li
>
>
ok
On Wed, Aug 16, 2023 at 4:10 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to support the rounding mode API for the
> VFWCVT.X.F.V as the below samples.
>
> * __riscv_vfwcvt_xu_f_v_u64m2_rm
> * __riscv_vfwcvt_xu_f_v_u64m2_rm_m
>
> Signed-off-by: Pan Li
>
>
ok
On Wed, Aug 16, 2023 at 5:44 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> In some build option combination, the default value may result in
> below error. This patch would like to fix it by passing a explict
> argument.
>
> riscv-vector-builtins-bases.cc:2495:24: error: invalid use
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