On Feb. 25, 2015, 4:26 a.m., Steve Reinhardt wrote:
src/sim/sim_events.hh, line 77
http://reviews.gem5.org/r/2665/diff/2/?file=43797#file43797line77
seems like it would be safer just to say:
if (scheduled())
deschedule();
then if some
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(Updated March 4, 2015, 12:56 a.m.)
Review request for Default.
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(Updated March 4, 2015, 1:04 a.m.)
Review request for Default.
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(Updated March 3, 2015, 11:43 p.m.)
Review request for Default.
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(Updated March 4, 2015, 12:47 a.m.)
Review request for Default.
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(Updated March 4, 2015, 1:07 a.m.)
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On Feb. 25, 2015, 4:32 p.m., Steve Reinhardt wrote:
Took me longer to review this just because I'm not sure what to think of
it. It's not pretty, but I don't have better ideas, so it's hard to object.
One thing that bothers me is that, while it's noble to try and generalize
On Feb. 25, 2015, 4:26 a.m., Steve Reinhardt wrote:
src/sim/sim_events.hh, line 77
http://reviews.gem5.org/r/2665/diff/2/?file=43797#file43797line77
seems like it would be safer just to say:
if (scheduled())
deschedule();
then if some
On Feb. 25, 2015, 1:55 a.m., Nathan Binkert wrote:
Not to be difficult, but is it possible for Sandia to just use the standard
gem5 license (which is basically the same thing you've already got)? And
if yes, can we just include it in the main tree instead of ext?
I've reached out to
On Feb. 25, 2015, 4:32 p.m., Steve Reinhardt wrote:
Took me longer to review this just because I'm not sure what to think of
it. It's not pretty, but I don't have better ideas, so it's hard to object.
One thing that bothers me is that, while it's noble to try and generalize
On Feb. 25, 2015, 4:26 a.m., Steve Reinhardt wrote:
src/sim/sim_events.hh, line 77
http://reviews.gem5.org/r/2665/diff/2/?file=43797#file43797line77
seems like it would be safer just to say:
if (scheduled())
deschedule();
then if some
On Feb. 24, 2015, 5:29 p.m., Steve Reinhardt wrote:
Just curious: what's the motivation for including this code with gem5 and
not with SST? I'm not necessarily opposed, just wondering whether you
considered putting this code in the SST distribution instead.
Yes, both ways were
On Feb. 24, 2015, 5:17 p.m., Steve Reinhardt wrote:
I like the idea of having a single global limit event, with a function to
access it so clients can check whether that's what was hit.
However I don't think the GlobalSimLoopExitEvent should be a singleton, as
there are a bunch of
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(Updated Feb. 25, 2015, 1:22 a.m.)
Review request for Default.
Changes
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(Updated Feb. 25, 2015, 1:16 a.m.)
Review request for Default.
Repository: gem5
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(Updated Feb. 25, 2015, 1:16 a.m.)
Review request for Default.
Repository: gem5
On Feb. 24, 2015, 10:24 p.m., Steve Reinhardt wrote:
ext/sst/ExtMaster.cc, line 43
http://reviews.gem5.org/r/2667/diff/1/?file=43756#file43756line43
Why is the ARM license repeated in every file, but the (shorter) Sandia
license is just included by reference? Seems inconsistent.
On Feb. 24, 2015, 5:17 p.m., Steve Reinhardt wrote:
I like the idea of having a single global limit event, with a function to
access it so clients can check whether that's what was hit.
However I don't think the GlobalSimLoopExitEvent should be a singleton, as
there are a bunch of
On Feb. 24, 2015, 5:48 p.m., Steve Reinhardt wrote:
To be honest, if you've got three lines worth of options you have to type
anyway (and thus end up embedding the command in another script), then the
value of this seems pretty marginal to me.
This is a reasonable complaint. Over
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Description
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Changeset
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Review request for Default.
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Description
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Changeset
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Review request for Default.
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Changeset
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Changeset
changeset 71c40e5c8bd4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=71c40e5c8bd4
description:
config: add --root-device machine parameter
In case /dev/sda1 is not actually the boot partition for an image,
we can override it on the command line or
changeset 3bfbaefa3844 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3bfbaefa3844
description:
sim: prioritize async events; prevent starvation
If a time quantum event is the only one in the queue, async
events (Ctrl-C, I/O, etc.) will never be
changeset d95e81d44e36 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d95e81d44e36
description:
base: add an accessor and operators ==,!= to address ranges
diffstat:
src/base/addr_range.hh | 21 +
1 files changed, 21 insertions(+), 0
changeset a0dab21e422f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a0dab21e422f
description:
sim: fix reference counting of PythonEvent
When gem5 is a slave to another simulator and the Python is only used
to initialize the configuration (and not
changeset b7bc5b1084a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b7bc5b1084a4
description:
arm: Add stats to table walker
This patch adds table walker stats for:
- Walk events
- Instruction vs Data
- Page size histogram
-
changeset 7982e539d003 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7982e539d003
description:
mem: Hide WriteInvalidate requests from prefetchers
Without this tweak, a prefetcher will happily prefetch data that will
promptly be invalidated and
changeset d1e1e851 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1e1e851
description:
mem: Support WriteInvalidate (again)
This patch takes a clean-slate approach to providing WriteInvalidate
(write streaming, full cache line writes without
changeset c04dc66e4316 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c04dc66e4316
description:
mem: Remove WriteInvalidate support
Prepare for a different implementation following in the next patch
diffstat:
src/mem/cache/base.hh |1 -
changeset f2f1dbfd505e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f2f1dbfd505e
description:
mem: have WriteInvalidate obsolete MSHRs
Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and
changeset 94d58056729f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=94d58056729f
description:
mem: don't inhibit WriteInv's or defer snoops on their MSHRs
WriteInvalidate semantics depend on the unconditional writeback
or they won't complete.
changeset dc49b13b6f79 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dc49b13b6f79
description:
scons: create dummy target to have SWIG generate C++ classes
scons build/arch/swig
diffstat:
src/SConscript | 19 +--
1 files changed, 17
changeset 1e2cf7b3e9d4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e2cf7b3e9d4
description:
scons: Add --without-tcmalloc build option
Disabling tcmalloc is required for valgrind's memcheck to work properly;
this option makes it easier to create
changeset 1f12c11d89b6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1f12c11d89b6
description:
mem: Provide better diagnostic for unconnected port
When _masterPort is null, a message to that effect is
more helpful than a segfault.
diffstat:
changeset 85274f24c37a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=85274f24c37a
description:
dev: Output invalid access size in IsaFake panic
diffstat:
src/dev/isa_fake.cc | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r
changeset fa66d9c5e180 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fa66d9c5e180
description:
tests: automatically kill regressions that take too long
When GNU coreutils 'timeout' is available, limit each regression
simulation to 4 hours.
changeset f40134eb3f85 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f40134eb3f85
description:
arm: support 16kb vm granules
diffstat:
src/arch/arm/miscregs.hh | 26 -
src/arch/arm/table_walker.cc | 125 +-
changeset 711eb0e64249 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=711eb0e64249
description:
mem: Refactor assignment of Packet types
Put the packet type swizzling (that is currently done in a lot of
places)
into a refineCommand() member
changeset 8bee5f4edb92 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8bee5f4edb92
description:
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint
version
and corresponding upgrader code
changeset 6cb378bad253 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6cb378bad253
description:
sim: bump checkpoint version for multiple event queues
This patch adds a fix for older checkpoints before support for
multiple event queues were added in
On Aug. 20, 2014, 5:39 p.m., Nilay Vaish wrote:
While I am ok with the changes made, do you think it is possible to
retain the Enum instead of using 12, 14 and 16?
I think this should be fine. I'll update patch shortly.
- Curtis
changeset a0d94ac7e004 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a0d94ac7e004
description:
ext: disable PLY debugging
Very rarely does anyone ever mess with PLY code, and when
such a need arises, the developer can reenable this flag in
changeset 6270235e0585 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6270235e0585
description:
scons: Require SWIG = 2.0.4 and remove vector typemaps
SWIG commit fd666c1 (*) made it unnecessary for gem5 to have these
typemaps to handle Vector types.
changeset badc31a41a87 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=badc31a41a87
description:
arm: cleanup ARM ISA definition
diffstat:
src/arch/arm/isa/insts/basic.isa | 34 --
src/arch/arm/isa/insts/insts.isa | 5
changeset bbfa3152bdea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bbfa3152bdea
description:
arch: remove inline specifiers on all inst constrs, all ISAs
With (upcoming) separate compilation, they are useless. Only
link-time optimization could
changeset a60405212dea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a60405212dea
description:
arm: add preliminary ISA splits for ARM arch
diffstat:
src/arch/arm/isa/insts/insts.isa | 10 +-
src/arch/arm/isa/insts/neon.isa | 22
changeset be0e1724eb39 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=be0e1724eb39
description:
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step.
changeset d717abc806aa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d717abc806aa
description:
cpu: add more instruction mix statistics
For the o3, add instruction mix (OpClass) histogram at commit (stats
also already collected at issue). For the
On May 5, 2014, 6:06 a.m., Steve Reinhardt wrote:
src/arch/isa_parser.py, line 2233
http://reviews.gem5.org/r/2247/diff/1/?file=39628#file39628line2233
I can see that this is more localized, but what about just going into
the templates and replacing '%(CPU_exec_context)s' with
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src/SConscript
http://reviews.gem5.org/r/2248/#comment4618
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