On Feb. 25, 2015, 4:26 a.m., Steve Reinhardt wrote:
src/sim/sim_events.hh, line 77
http://reviews.gem5.org/r/2665/diff/2/?file=43797#file43797line77
seems like it would be safer just to say:
if (scheduled())
deschedule();
then if some
On Feb. 10, 2015, 5:37 p.m., Stephan Diestelhorst wrote:
I have had a similar impulse, when inspecting this code. However, the
prefetch hitting a write-back in an upper cache is actually already handled
in CacheTagStore::getTimingPacket():
// Check if the prefetch hit
changeset 886d2458e0d6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=886d2458e0d6
description:
mem: Add option to force in-order insertion in PacketQueue
By default, the packet queue is ordered by the ticks of the to-be-sent
packages. With the
changeset 9ba5e70964a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9ba5e70964a4
description:
mem: Tidy up the cache debug messages
Avoid redundant inclusion of the name in the DPRINTF string.
diffstat:
src/mem/cache/base.cc | 10 +-
changeset 4ed87af2930f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4ed87af2930f
description:
dev, arm: Clean up PL011 and rewrite interrupt handling
The ARM PL011 UART model didn't clear and raise interrupts
correctly. This changeset rewrites the
changeset d1387fcd94b8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1387fcd94b8
description:
mem: Unify all cache DPRINTF address formatting
This patch changes all the DPRINTF messages in the cache to use
'%#llx' every time a packet address is
changeset 8a20e2a1562d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8a20e2a1562d
description:
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing,
changeset 4f8c1bd6fdb8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4f8c1bd6fdb8
description:
arm: Share a port for the two table walker objects
This patch changes how the MMU and table walkers are created such that
a single port is used to connect
changeset fe09d1bc6721 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fe09d1bc6721
description:
arm: Correctly access the stack pointer in GDB
We curently use INTREG_X31 instead of INTREG_SPX when accessing the
stack pointer in GDB. gem5 normally
changeset f7d17d8a854c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f7d17d8a854c
description:
arm: Fix broken page table permissions checks in remote GDB
The remote GDB interface currently doesn't check if translations are
valid before reading
changeset 3e6a3eaac71b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3e6a3eaac71b
description:
mem: Downstream components consumes new crossbar delays
This patch makes the caches and memory controllers consume the delay
that is annotated to a packet
changeset 67b3e74de9ae in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=67b3e74de9ae
description:
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the
changeset 1072b1381560 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1072b1381560
description:
mem: Fix cache MSHR conflict determination
This patch fixes a rather subtle issue in the sending of MSHR requests
in the cache, where the logic previously
changeset ced453290507 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ced453290507
description:
cpu: o3 register renaming request handling improved
Now, prior to the renaming, the instruction requests the exact amount of
registers it will need, and
changeset 4408a83f7881 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4408a83f7881
description:
arm: Remove unnecessary dependencies between AArch64 FP instructions
diffstat:
src/arch/arm/isa/templates/vfp64.isa | 15 ---
1 files changed, 0
changeset 9b71309d29f9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9b71309d29f9
description:
tests: Run regression timeout as foreground
Allow the user to send signals such as Ctrl C to the gem5 runs. Note
that this assumes coreutils = 8.13, which
changeset 245cd4691cbf in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=245cd4691cbf
description:
mem: Fix prefetchSquash + memInhibitAsserted bug
This patch resolves a bug with hardware prefetches. Before a hardware
prefetch
is sent towards the
changeset 890269a13188 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=890269a13188
description:
arm: Don't truncate 16-bit ASIDs to 8 bits
The ISA code sometimes stores 16-bit ASIDs as 8-bit unsigned integers
and has a couple of inverted checks that
changeset b1d90d88420e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b1d90d88420e
description:
mem: Add byte mask to Packet::checkFunctional
This patch changes the valid-bytes start/end to a proper byte
mask. With the changes in timing introduced in
changeset 7f67a8d786a2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7f67a8d786a2
description:
cpu: Add a PC-value to the traffic generator requests
Have the traffic generator add its masterID as the PC address to the
requests. That way, prefetchers
On Feb. 19, 2015, 10:50 p.m., Andreas Hansson wrote:
Ship It!
Could someone be kind enough to push this?
- Andreas
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2655/#review5898
Done. Thanks for the reminder.
Steve
On Mon, Mar 2, 2015 at 2:59 AM, Andreas Hansson andreas.hans...@arm.com
wrote:
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2636/
On February 10th, 2015, 5:37 p.m. UTC, *Stephan Diestelhorst* wrote:
I have
I'll push it along with my own patches.
--
Nilay
On Mon, 2 Mar 2015, Andreas Hansson via gem5-dev wrote:
On Feb. 19, 2015, 10:50 p.m., Andreas Hansson wrote:
Ship It!
Could someone be kind enough to push this?
- Andreas
---
Great. Let us know if there are still any remaining issues.
We’ve got some additional cache fixes that should be on RB before the end of
the week.
Andreas
From: Steve Reinhardt ste...@gmail.commailto:ste...@gmail.com
Date: Monday, 2 March 2015 16:47
To: Andreas Hansson
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2676/#review5925
---
Ship it!
Ship It!
- Steve Reinhardt
On Feb. 28, 2015, 2:40 p.m.,
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