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(Updated Oct. 26, 2016, 4:11 p.m.)
Review request for Default.
Changes
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(Updated Oct. 26, 2016, 4:23 p.m.)
Review request for Default.
Changes
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Review request for Default.
Repository: gem5
Description
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This patch
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(Updated Oct. 26, 2016, 4:06 p.m.)
Review request for Default.
Changes
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changeset 7d4d424c9f17 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7d4d424c9f17
description:
gpu-compute: support in-order data delivery in GM pipe
this patch adds an ordered response buffer to the GM pipeline
to ensure in-order data delivery. the
changeset c63431b7bbeb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c63431b7bbeb
description:
gpu-compute, hsail: make the PC a byte address, not an instruction index
currently the PC is incremented on an instruction granularity, and not
as an
changeset d1ad31187fa5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1ad31187fa5
description:
gpu-compute: use System cache line size in the GPU
diffstat:
src/gpu-compute/compute_unit.cc | 3 ++-
src/gpu-compute/compute_unit.hh | 3 +++
changeset 6d5fc65d64bd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6d5fc65d64bd
description:
gpu-compute: move disassemle() implementation to GPUStaticInst
diffstat:
src/arch/hsail/insts/gpu_static_inst.cc | 11 ---
changeset 80c30bd0c7d6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=80c30bd0c7d6
description:
gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF
the GPUISA class is meant to encapsulate any ISA-specific behavior -
special
register
changeset e772fdcd3809 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e772fdcd3809
description:
gpu-compute: remove inst enums and use bit flag for attributes
this patch removes the GPUStaticInst enums that were defined in GPU.py.
instead, a simple
changeset 0a65922d564d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0a65922d564d
description:
gpu-compute: add instruction mix stats for the gpu
diffstat:
src/gpu-compute/compute_unit.cc | 141
changeset c3b4d57a15c5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c3b4d57a15c5
description:
gpu-compute, hsail: call discardFetch() from the WF
because every taken branch causes fetch to be discarded, we move the
call
to the WF to avoid to have
changeset 5e7599457b97 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5e7599457b97
description:
dev: Add 'simLength' parameter in EthPacketData
Currently, all the network devices create a 16K buffer for the 'data'
field
in EthPacketData, and use
changeset c7453f485a5f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7453f485a5f
description:
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()
for HSAIL an operand's indices into the register files may be calculated
trivially, because
changeset 0bf388858d1e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0bf388858d1e
description:
ruby: Allow multiple outstanding DMA requests
DMA sequencers and protocols can currently only issue one DMA access at
a time. This patch implements the
changeset 3027d6c34fa4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3027d6c34fa4
description:
gpu-compute, arch: add some methods to the base inst classes for ISA
support
diffstat:
src/arch/hsail/insts/gpu_static_inst.hh | 1 +
changeset 9d19bb965564 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9d19bb965564
description:
ruby: make a RequestDesc class instead of std::pair
the RequestDesc was previously implemented as a std::pair, which made
the implementation overly
changeset bc1f702c25b9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bc1f702c25b9
description:
hsail, gpu-compute: remove doGm/SmReturn add completeAcc
we are removing doGmReturn from the GM pipe, and adding completeAcc()
implementations for the
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Review request for Default.
Repository: gem5
Description
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cpu: Add a
Hello all,
The SynchroTrace project [2] provides multi-threaded traces that are
synchronization-aware. I have posted to ReviewBoard a patch [1] providing the
trace replayer part of the project. The traces themselves are generated using
a separate tool; we understand that there may be concerns
changeset 725fef71f376 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=725fef71f376
description:
config: Break out base options for usage with NULL ISA
This patch breaks out the most basic configuration options into a set
of base options, to allow
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Somehow the patch is not displaying. Did you use hg postreview?
-
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Thanks for this. There are a few minor issues and style questions.
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Ship it!
Ship It!
- Andreas Hansson
On Oct. 26, 2016, 4:06 p.m.,
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Some of the files are not displaying ok. Did you post the review using
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
*
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src/mem/cache/tags/base_set_assoc.hh (line 233)
Hi,
What's the interface to the scratchpad? Are you adding new ISA extensions,
or is it a memory-mapped device. If it's a memory-mapped device, you should
be able to connect it to the CPU via the ports interface. Something like
add a crossbar between the CPU and the L1D and have the L1D only
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