Re: [gem5-dev] Review Request 3475: sim: Fix fork for multithreaded simulations

> On May 23, 2016, 9:48 a.m., Joel Hestness wrote: > > src/sim/simulate.cc, line 92 > > > > > > It might be safer to use an initial PID that will definitely not be a > > valid PID (e.g. -1) rather than 0, which is a valid

Re: [gem5-dev] Review Request 3474: cpu, x86: Allow the TLB to be warmed up before CPU switch

> On May 26, 2016, 6:16 a.m., Curtis Dunham wrote: > > src/arch/x86/tlb.cc, line 128 > > > > > > If this just (essentially) copy constructs a new TLB from the old, why > > can't the same TLB be used .. just reconnecting

Re: [gem5-dev] Test infrastructure improvements

Hi Andreas, If I haven't said it before, thanks for all the effort you've put in here updating the regressions! I'm glad to see things moving in a positive direction. For the scons changes, I think I'll just trust you that they work ;). The SConscript files are pretty much inscrutable to me. My

Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

> On May 26, 2016, 10 a.m., Radhika Jagtap wrote: > > util/tlm/tlm_elastic.py, lines 141-142 > > > > > > CPU should be connected to L1 caches instead of membus. I think it > > would be best to call the

Re: [gem5-dev] Review Request 3474: cpu, x86: Allow the TLB to be warmed up before CPU switch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3474/#review8360 --- Ship it! Looks reasonable, thanks. - Curtis Dunham On May 20, 2016,

Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

> On May 26, 2016, 10 a.m., Radhika Jagtap wrote: > > util/tlm/tlm_elastic.py, lines 141-142 > > > > > > CPU should be connected to L1 caches instead of membus. I think it > > would be best to call the

Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3477/#review8357 --- util/tlm/tlm_elastic.py (line 94)

Re: [gem5-dev] Review Request 3474: cpu, x86: Allow the TLB to be warmed up before CPU switch

> On May 26, 2016, 1:16 p.m., Curtis Dunham wrote: > > src/arch/x86/tlb.cc, line 128 > > > > > > If this just (essentially) copy constructs a new TLB from the old, why > > can't the same TLB be used .. just reconnecting

Re: [gem5-dev] Review Request 3478: misc: Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3478/#review8356 --- Ship it! I always appreciate documentation patches! If you ever get

Re: [gem5-dev] Review Request 3479: misc: fixes deprecated sc_time function for SystemC 2.3.1

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3479/#review8355 --- Ship it! Ship It! - Jason Lowe-Power On May 25, 2016, 11:03 p.m.,

Re: [gem5-dev] Review Request 3475: sim: Fix fork for multithreaded simulations

> On May 26, 2016, 2:19 p.m., Andreas Sandberg wrote: > > Thanks for looking into this! > > > > Forking a multi-threaded simulation is very scary. If I remember my POSIX > > right, the behaviour after a fork of a multi-threaded program is undefined > > (IIRC, you are supposed to call exec

Re: [gem5-dev] Review Request 3475: sim: Fix fork for multithreaded simulations

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3475/#review8349 --- Thanks for looking into this! Forking a multi-threaded simulation is

Re: [gem5-dev] Review Request 3480: ExternalMaster: add a masterId so that external ports can generate packages

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3480/#review8352 --- Ship it! Ship It! - Jason Lowe-Power On May 26, 2016, 11:38 a.m.,

Re: [gem5-dev] Review Request 3476: arm: Fix PMU register access

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3476/#review8350 --- Ship it! - Andreas Sandberg On May 23, 2016, 3:07 p.m., Fernando Endo

Re: [gem5-dev] Review Request 3474: cpu, x86: Allow the TLB to be warmed up before CPU switch

> On May 26, 2016, 1:16 p.m., Curtis Dunham wrote: > > src/arch/x86/tlb.cc, line 128 > > > > > > If this just (essentially) copy constructs a new TLB from the old, why > > can't the same TLB be used .. just reconnecting

Re: [gem5-dev] Review Request 3474: cpu, x86: Allow the TLB to be warmed up before CPU switch

> On May 26, 2016, 1:16 p.m., Curtis Dunham wrote: > > src/arch/x86/tlb.cc, line 128 > > > > > > If this just (essentially) copy constructs a new TLB from the old, why > > can't the same TLB be used .. just reconnecting

Re: [gem5-dev] Review Request 3474: cpu, x86: Allow the TLB to be warmed up before CPU switch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3474/#review8346 --- src/arch/x86/tlb.cc (line 128)

[gem5-dev] Review Request 3480: ExternalMaster: add a masterId so that external ports can generate packages

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3480/ --- Review request for Default. Repository: gem5 Description --- The Request

Re: [gem5-dev] Review Request 3473: systemc example: Fixed an ambiguous call error and a typo in the README

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3473/ --- (Updated May 26, 2016, 10:13 a.m.) Review request for Default. Changes ---

Re: [gem5-dev] Review Request 3479: misc: fixes deprecated sc_time function for SystemC 2.3.1

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3479/#review8345 --- Ship it! Ship It! - Radhika Jagtap On May 25, 2016, 11:03 p.m.,

Re: [gem5-dev] Review Request 3478: misc: Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm

> On May 26, 2016, 10:06 a.m., Radhika Jagtap wrote: > > Please change the summary to be more high level (the 3 file paths could go away) and mention the reason, ie. something like 'required to setup evnironment to compile'. - Radhika

Re: [gem5-dev] Review Request 3478: misc: Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3478/#review8343 --- Ship it! - Radhika Jagtap On May 25, 2016, 10:32 p.m., Matthias Jung

Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3477/#review8342 --- Hi Matthias, thanks for integrating the elastic trace cpu system into

Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3477/#review8341 --- util/tlm/tlm_elastic.py (line 1)

Re: [gem5-dev] Review Request 3453: o3: Clarify meaning of cachePorts variable in lsq_unit.hh

Hi everyone, This patch has been sitting on the review board for almost a month now. Nathanaël gave it the "ship it" and it was discussed a bit. Since the change is minor (and has no effect on default O3CPU configuration), do you think it is ready to be pushed, or does someone disagree with

Re: [gem5-dev] Review Request 3461: tests: Add test infrastructure as a Python module

> On May 10, 2016, 1:12 a.m., Joe Gross wrote: > > Hi Andreas, I had a couple questions/clarifications about this patch. The > > idea is that this script will run the test/test suites in an ordered > > fashion but doesn't contain any infrastructure to launch jobs in a > > distributed

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed. *