Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32694 )
Change subject: arch-riscv: Fix disassembling of all register instructions
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arch-riscv: Fix disassembling of all register in
Dear all,
In one month's time gem5 v20.1.0.0 will be released. In accordance with our
release procedures (https://gem5.googlesource.com/public/gem5
/+/refs/heads/master/CONTRIBUTING.md#releases), on September 1st we will
create our release-staging branch from the develop branch. Therefore,
anythin
Emily Brickey has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32794 )
Change subject: arch-arm: convert tlb to new style stats
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arch-arm: convert tlb to new style stats
Change-Id
Emily Brickey has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32494 )
Change subject: arch-arm: convert table_walker to new style stats
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arch-arm: convert table_walker to new style stats
Ch
Hi again,
I just want to report something that I found weird, didn't really know if it's
wanted or not, if it's me which do a bad manipulation or not.
When I run a full-system simulation with the starter_fs.py and prebuilts
binaries, I get a kernel panic. I have to change the root partition i
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32774
to review the following change.
Change subject: arch-arm: Remove setters from SoftwareStep
.
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32775
to review the following change.
Change subject: arch-arm: Rename SelfDebug member variables
Hello Richard Cooper, Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32776
to review the following change.
Change subject: arch-arm: Early checking if debug is enabled in TLB
Isaac Sánchez Barrera has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32394 )
Change subject: mem-cache,python: Allow custom TLB and events in each
prefetcher.
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mem-cache,python: Allow cu