[gem5-dev] Change in gem5/gem5[develop]: mem: implement x86 locked accesses in timing-mode classic cache

oftPFExReq; else if (req->isPrefetch()) return MemCmd::SoftPFReq; +else if (req->isLockedRMW()) +return MemCmd::LockedRMWReadReq; else return MemCmd::ReadReq; } @@ -995,6 +1004,8 @@ MemCmd::InvalidateReq;

[gem5-dev] Change in gem5/gem5[develop]: mem: implement x86 locked accesses in timing-mode classic cache

Cmd::SoftPFExReq; else if (req->isPrefetch()) return MemCmd::SoftPFReq; +else if (req->isLockedRMW()) +return MemCmd::LockedRMWReadReq; else return MemCmd::ReadReq; } @@ -995,6 +1004,8 @@

[gem5-dev] Change in gem5/gem5[develop]: scons: allow building gem5 in a nix environment

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[gem5-dev] Change in gem5/gem5[develop]: tests: Add a test for forking and switching cpus

+test_kvm_fork_run( +cpu="o3", num_cpus=1, mem_system="classic", length=constants.quick_tag +) +test_kvm_fork_run( +cpu="timing", num_cpus=4, mem_system="classic", length=constants.quick_tag +) + +test_kvm_fork_run( + cpu="timing", +

[gem5-dev] Change in gem5/gem5[develop]: python: Fix L1 data cache size in cache components

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[gem5-dev] Change in gem5/gem5[develop]: python: Fix L1 data cache size in cache components

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[gem5-dev] Change in gem5/gem5[develop]: ext: Update libelf from elftoolchain 0.7.1

/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8f86cd918ad01897c42aa479f9c64520def36830 Gerrit-Change-Number: 50927 Gerrit-PatchSet: 6 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Hoa Nguyen Gerrit

[gem5-dev] Change in gem5/gem5[develop]: ext: Update libelf from elftoolchain 0.7.1

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[gem5-dev] Change in gem5/gem5[develop]: tests: Fix gem5 resources import in parsec test

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[gem5-dev] Change in gem5/gem5[develop]: tests: Fix gem5 resources import in parsec test

Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I271cf89130f31777ef43b00e0c15cf44835977e3 Gerrit-Change-Number: 50787 Gerrit-PatchSet: 1 Gerrit-Owner: Austin Harris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev

[gem5-dev] Change in gem5/gem5[develop]: sim: Fix hang while terminating threads with fork

Gerrit-Change-Id: Ia04db2f3b1341c4d432178a37812fd882e148ec2 Gerrit-Change-Number: 50710 Gerrit-PatchSet: 2 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged

[gem5-dev] Change in gem5/gem5[develop]: sim: Fix hang while terminating threads with fork

-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia04db2f3b1341c4d432178a37812fd882e148ec2 Gerrit-Change-Number: 50710 Gerrit-PatchSet: 1 Gerrit-Owner: Austin Harris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org

[gem5-dev] Change in gem5/gem5[develop]: sim: Fix fork for multithreaded simulations

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[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm: Reinitialize threads on drainResume

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[gem5-dev] Change in gem5/gem5[develop]: tests: Add a test for forking and switching cpus

er scheduling test.") + +print("Finished KVM fast forwarding test.") + +print("Starting fork and switch processors test") +pid = m5.fork("%(parent)s/" + str(m5.curTick())) +if pid == 0: # in child +print("Switching processors in child.") +proc

[gem5-dev] Change in gem5/gem5[develop]: tests: Add a test for KVM boot then switching cpus

mulate() +exit_cause = exit_event.getCause() + +if exit_cause != "m5_exit instruction encountered": +raise Exception( +f"Expected exit after switching processors, received: {exit_cause}" +) +print("Exiting @ tick {} because {}.".format(m5.curTick(

[gem5-dev] Change in gem5/gem5[develop]: scons: Setup the m4 tool for libelf

Set: 3 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %

[gem5-dev] Change in gem5/gem5[develop]: python: Fix switchable processor event queues

rrit-Branch: develop Gerrit-Change-Id: I74ebc4aa52a44662602b9512c23c8fb8a40101d0 Gerrit-Change-Number: 50229 Gerrit-PatchSet: 3 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Review

[gem5-dev] Change in gem5/gem5[develop]: scons: Generate a compilation database

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[gem5-dev] Change in gem5/gem5[develop]: scons: Require the m4 tool in scons explicitly

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[gem5-dev] Change in gem5/gem5[develop]: scons: Ignore string truncation warnings in libelf

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[gem5-dev] Change in gem5/gem5[develop]: util,scons: Enable a nix package manager shell

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[gem5-dev] Change in gem5/gem5[develop]: tests: Add a test for KVM boot then switching cpus

se() != "m5_exit instruction encountered": +raise Exception("Expected exit instruction after boot!") + +print(f"Switching processors to {args.cpu}!") +processor.switch() +if args.ticks_switched != None: +exit_event = m5.simulate(args.ticks_switched) +else

[gem5-dev] Change in gem5/gem5[develop]: python: Fix switchable processor event queues

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[gem5-dev] Change in gem5/gem5[develop]: python: Update switchable processor to support KVM

public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie843e2b4ab6e506bb195bfcef33cead9a6273901 Gerrit-Change-Number: 50127 Gerrit-PatchSet: 3 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Pow

[gem5-dev] Change in gem5/gem5[develop]: python: Update switchable processor to support KVM

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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix fork for multithreaded simulations

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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Enable support for riscv 32-bit in SE mode.

+ argv.size()) * sizeof(Addr) + - (1 + envp.size()) * sizeof(Addr) + - sizeof(Addr) + 2 * sizeof(IntType) * auxv.size(); -stack_top &= -2*sizeof(Addr); +stack_top -= (1 + argv.size()) * addrSize + + (1 + envp.size()) * addrSize + +

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Enable support for riscv 32-bit in SE mode.

/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Gerrit-Change-Number: 15355 Gerrit-PatchSet: 5 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit

[gem5-dev] Change in gem5/gem5[master]: riscv: Get rid of ISA specific register types in Interrupts.

m5 Gerrit-Branch: master Gerrit-Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc Gerrit-Change-Number: 16122 Gerrit-PatchSet: 3 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Gabe Black Gerrit-Mes

[gem5-dev] Change in gem5/gem5[master]: riscv: Get rid of ISA specific register types in Interrupts.

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[gem5-dev] Change in gem5/gem5[master]: riscv: Get rid of ISA specific register types in Interrupts.

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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Enable support for riscv 32-bit in SE mode.

Gerrit-Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Gerrit-Change-Number: 15355 Gerrit-PatchSet: 4 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Enable support for riscv 32-bit in SE mode.

Gerrit-Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Gerrit-Change-Number: 15355 Gerrit-PatchSet: 3 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Enable support for riscv 32-bit in SE mode.

: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Gerrit-Change-Number: 15355 Gerrit-PatchSet: 2 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Enable support for riscv 32-bit in SE mode.

of(IntType) * auxv.size(); -stack_top &= -2*sizeof(Addr); +stack_top -= (1 + argv.size()) * addrSize + + (1 + envp.size()) * addrSize + + addrSize + 2 * sizeof(IntType) * auxv.size(); +stack_top &= -2*addrSize; memState->setStackSize(memState

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix the srlw and srliw instructions.

I14ccb0655819887db2306fee1188e1c83a991743 Gerrit-Change-Number: 11669 Gerrit-PatchSet: 5 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Robert Scheffel Gerrit-Reviewer: Tuan Ta Gerrit-MessageType: merged

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix the srlw and srliw instructions.

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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix the srlw and srliw instructions.

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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix the srlw and srliw instructions.

Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Gerrit-Change-Number: 11669 Gerrit-PatchSet: 2 Gerrit-Owner: Austin Harris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5

[gem5-dev] Change in gem5/gem5[master]: riscv: Fix the srlw and srliw instructions.

Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Gerrit-Change-Number: 11669 Gerrit-PatchSet: 1 Gerrit-Owner: Austin Harris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: config: Fix need to set ISA of switch cpus.

Austin Harris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/6241 ) Change subject: config: Fix need to set ISA of switch cpus. .. config: Fix need to set ISA of switch cpus. Since

[gem5-dev] Change in public/gem5[master]: config: Fix need to set ISA of switch cpus.

Austin Harris has uploaded this change for review. ( https://gem5-review.googlesource.com/6241 Change subject: config: Fix need to set ISA of switch cpus. .. config: Fix need to set ISA of switch cpus. Since

[gem5-dev] Change in public/gem5[master]: sim: Fix need to save address space info during serialization.

Austin Harris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/5901 ) Change subject: sim: Fix need to save address space info during serialization. .. sim: Fix need to save address space

[gem5-dev] Change in public/gem5[master]: sim: Fix need to save address space info during serialization.

Hello Gabe Black, Jason Lowe-Power, Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/5901 to look at the new patch set (#2). Change subject: sim: Fix need to save address space info during serialization.

[gem5-dev] Change in public/gem5[master]: sim: Fix need to save address space info during serialization.

Austin Harris has uploaded this change for review. ( https://gem5-review.googlesource.com/5901 Change subject: sim: Fix need to save address space info during serialization. .. sim: Fix need to save address space info