[gem5-dev] Change in gem5/gem5[develop]: sim: Fix Mempool overrides during checkpoint

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56969 )


Change subject: sim: Fix Mempool overrides during checkpoint
..

sim: Fix Mempool overrides during checkpoint

This patch fixes the problem during checkpoing where the mempool is not
restored, but using only the one specified in the config file as a new
execution.
In order to fix that this changes modifyies the serialize/unserialize
functions for mempools and create new funcionts on se_workload to make
sure mempools ends up in the m5.cpt.
We change as well the unserialize mempool function to update
according the checkpoint file so the execution starts with the same
free pages and free pointers.

JIRA: https://gem5.atlassian.net/browse/GEM5-1191

Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56969
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/sim/mem_pool.cc
M src/sim/process.cc
M src/sim/se_workload.cc
M src/sim/se_workload.hh
4 files changed, 46 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/mem_pool.cc b/src/sim/mem_pool.cc
index 20b6eda..d58399d 100644
--- a/src/sim/mem_pool.cc
+++ b/src/sim/mem_pool.cc
@@ -169,6 +169,7 @@
 void
 MemPools::serialize(CheckpointOut ) const
 {
+ScopedCheckpointSection sec(cp, "mempools");
 int num_pools = pools.size();
 SERIALIZE_SCALAR(num_pools);

@@ -179,6 +180,10 @@
 void
 MemPools::unserialize(CheckpointIn )
 {
+// Delete previous mem_pools
+pools.clear();
+
+ScopedCheckpointSection sec(cp, "mempools");
 int num_pools = 0;
 UNSERIALIZE_SCALAR(num_pools);

diff --git a/src/sim/process.cc b/src/sim/process.cc
index 3a631a5..97130bd 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -388,6 +388,7 @@
 memState->unserialize(cp);
 pTable->unserialize(cp);
 fds->unserialize(cp);
+
 /**
  * Checkpoints for pipes, device drivers or sockets currently
  * do not work. Need to come back and fix them at a later date.
diff --git a/src/sim/se_workload.cc b/src/sim/se_workload.cc
index d3c8570..4d2bd54 100644
--- a/src/sim/se_workload.cc
+++ b/src/sim/se_workload.cc
@@ -54,6 +54,18 @@
 }

 void
+SEWorkload::serialize(CheckpointOut ) const
+{
+memPools.serialize(cp);
+}
+
+void
+SEWorkload::unserialize(CheckpointIn )
+{
+memPools.unserialize(cp);
+}
+
+void
 SEWorkload::syscall(ThreadContext *tc)
 {
 tc->getProcessPtr()->syscall(tc);
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index 5bc597f..e212ad6 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -81,6 +81,9 @@
 panic("No workload symbol table for syscall emulation mode.");
 }

+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;
+
 void syscall(ThreadContext *tc) override;

 // For now, assume the only type of events are system calls.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
Gerrit-Change-Number: 56969
Gerrit-PatchSet: 6
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix Mempool overrides during checkpoint

[Jordi Vaquero (Gerrit) via gem5-dev]

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Gerrit-Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation ARMv8.1 RDMA

[Jordi Vaquero (Gerrit) via gem5-dev]

readDest=True, extra=rdm_check)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshElemQX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,  
byElem=True,

+   readDest=True, extra=rdm_check)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshElemScX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,  
byElem=True,

+   readDest=True, scalar=True, extra=rdm_check)
+# SQRDMLSH (vector)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshDX", "SimdMultOp",
+           ("int16_t", "int32_t"), 2, sqrdmlshCode,
+   readDest=True, extra=rdm_check)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshQX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,
+   readDest=True, extra=rdm_check)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshScX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,  
scalar=True,

+   readDest=True, extra=rdm_check)
+# SQRDMULby element)
 sqrdmulhCode = '''
 FPSCR fpscr = (FPSCR) FpscrQc;
 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2 +

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Gerrit-Branch: develop
Gerrit-Change-Id: I430e8880723f373a50079a87fd4ecc634d86
Gerrit-Change-Number: 36015
Gerrit-PatchSet: 11
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding connector post Timing access

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37416 )



Change subject: cpu: Adding connector post Timing access
..

cpu: Adding connector post Timing access

This patch adds a new connector to architecture dependent code
in completeDataAccess. This is used for address based memory
barrier to release the block after that access. The address based
barrier is implemented on architecture dependent code. Its implementation
for ARM arch can be accessed in dependent commits.

Change-Id: I8c75cd77dc6c9f9ae5e416608ce3d8ddb7b2ecf9
---
M src/arch/generic/tlb.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/timing.cc
3 files changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 59b3a01..21d80c1 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -98,6 +98,8 @@
 panic("Not implemented.\n");
 }

+virtual void handleOrdering(ThreadContext *tc, RequestPtr ) = 0;
+
 /**
  * Do post-translation physical address finalization.
  *
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index b67edc4..519e288 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -970,6 +970,7 @@
 state->outstanding--;
 assert(pkt == _packets.front());
 _port.completeDataAccess(pkt);
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),  
pkt->req);

 return true;
 }

@@ -996,6 +997,8 @@
 resp->dataStatic(_data);
 resp->senderState = _senderState;
 _port.completeDataAccess(resp);
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),
+   pkt->req);
 delete resp;
 }
 return true;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9c529b4..06212c7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1046,8 +1046,10 @@
 panic("HTM - unhandled rc %s", htmFailureToStr(htm_rc));
 }
 } else {
+SimpleThread* thread = t_info->thread;
 fault = curStaticInst->completeAcc(pkt, t_info,
  traceData);
+thread->mmu->dtb->handleOrdering(thread->getTC(), pkt->req);
 }

 // hardware transactional memory

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Gerrit-Change-Id: I8c75cd77dc6c9f9ae5e416608ce3d8ddb7b2ecf9
Gerrit-Change-Number: 37416
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Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[develop]: mem: Added a new atribute for Address based mem barrier

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37415 )



Change subject: mem: Added a new atribute for Address based mem barrier
..

mem: Added a new atribute for Address based mem barrier

This small patch adds a new attribute and the set/get functions
to implement an address based mem barrier. The details of its use an
implementation are architecture dependent and it is described in
child-commits.

Change-Id: I2bf95b0b9ba848e35b58e545db311b8f09cb9cc7
---
M src/mem/request.hh
1 file changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/mem/request.hh b/src/mem/request.hh
index 73c823b..2898a33 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -407,6 +407,9 @@

 LocalAccessor _localAccessor;

+/** Extra data used for ARM LOR subsistem to identify memory region **/
+int orderIndex = 0;
+
 /** The instruction count at the time this request is created */
 Counter _instCount = 0;

@@ -860,6 +863,18 @@
 void setAccessLatency() { accessDelta = curTick() - _time -  
translateDelta; }

 Tick getAccessLatency() const { return accessDelta; }

+void
+setOrderingIndex(int idx)
+{
+orderIndex = idx;
+}
+
+int
+getOrderingIndex()
+{
+return orderIndex;
+}
+
 /**
  * Accessor for the sequence number of instruction that creates the
  * request.

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing Arm8 LOR feature

[Jordi Vaquero (Gerrit) via gem5-dev]

}

 bool
+EnabledLOR(ThreadContext *tc)
+{
+uint64_t lorid = tc->readMiscReg(MISCREG_LORID_EL1);
+int nRegions = bits(lorid, 7, 0);
+int nRegDesc = bits(lorid, 23, 16);
+bool enabled = !(nRegions == 0 || nRegDesc == 0);
+return enabled && HaveLORExt(tc);
+
+}
+
+bool
 ELIs64(ThreadContext *tc, ExceptionLevel el)
 {
 return !ELIs32(tc, el);
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 6ec6403..e86ec81 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -152,12 +152,15 @@
 }

 bool HavePACExt(ThreadContext *tc);
+bool HaveLORExt(ThreadContext *tc);
 bool HaveVirtHostExt(ThreadContext *tc);
 bool HaveLVA(ThreadContext *tc);
 bool HaveSecureEL2Ext(ThreadContext *tc);
 bool IsSecureEL2Enabled(ThreadContext *tc);
 bool EL2Enabled(ThreadContext *tc);

+bool EnabledLOR(ThreadContext *tc);
+
 /**
  * This function checks whether selected EL provided as an argument
  * is using the AArch32 ISA. This information might be unavailable
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 59b3a01..21d80c1 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -98,6 +98,8 @@
 panic("Not implemented.\n");
 }

+virtual void handleOrdering(ThreadContext *tc, RequestPtr ) = 0;
+
 /**
  * Do post-translation physical address finalization.
  *
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index b67edc4..cf45f4a 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -970,6 +970,8 @@
 state->outstanding--;
 assert(pkt == _packets.front());
 _port.completeDataAccess(pkt);
+//LOR handle
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),  
pkt->req);

 return true;
 }

@@ -996,6 +998,8 @@
 resp->dataStatic(_data);
 resp->senderState = _senderState;
     _port.completeDataAccess(resp);
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),
+   pkt->req);
 delete resp;
 }
 return true;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9c529b4..d59d31b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1046,6 +1046,10 @@
 panic("HTM - unhandled rc %s", htmFailureToStr(htm_rc));
 }
 } else {
+SimpleThread* thread = t_info->thread;
+thread->mmu->dtb->handleOrdering(thread->getTC(), pkt->req);
+curStaticInst->completeAcc(pkt, threadInfo[curThread],
+   traceData);
 fault = curStaticInst->completeAcc(pkt, t_info,
  traceData);
 }
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 73c823b..2898a33 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -407,6 +407,9 @@

 LocalAccessor _localAccessor;

+/** Extra data used for ARM LOR subsistem to identify memory region **/
+int orderIndex = 0;
+
 /** The instruction count at the time this request is created */
 Counter _instCount = 0;

@@ -860,6 +863,18 @@
 void setAccessLatency() { accessDelta = curTick() - _time -  
translateDelta; }

 Tick getAccessLatency() const { return accessDelta; }

+void
+setOrderingIndex(int idx)
+{
+orderIndex = idx;
+}
+
+int
+getOrderingIndex()
+{
+return orderIndex;
+}
+
 /**
  * Accessor for the sequence number of instruction that creates the
  * request.

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation ARMv8.1 RDMA

[Jordi Vaquero (Gerrit) via gem5-dev]

alfNeg = maxNeg / 2;
+  if ((srcElem1 == maxNeg && srcElem2 == maxNeg) ||
+  (srcElem1 == halfNeg && srcElem2 == maxNeg) ||
+  (srcElem1 == maxNeg && srcElem2 == halfNeg)) {
+  if (destElem < 0) {
+destElem = mask(sizeof(Element) * 8 - 1);
+  } else {
+destElem = std::numeric_limits::min();
+  }
+  fpscr.qc = 1;
+  }
+  FpscrQc = fpscr;
+'''
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshElemDX", "SimdMultOp",
+   ("int16_t", "int32_t"), 2, sqrdmlshCode,  
byElem=True,

+   readDest=True)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshElemQX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,  
byElem=True,

+   readDest=True)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshElemScX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,  
byElem=True,

+   readDest=True, scalar=True)
+# SQRDMLSH (vector)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshDX", "SimdMultOp",
+   ("int16_t", "int32_t"), 2, sqrdmlshCode,
+   readDest=True)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshQX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,
+   readDest=True)
+threeEqualRegInstX("sqrdmlsh", "SqrdmlshScX", "SimdMultOp",
+   ("int16_t", "int32_t"), 4, sqrdmlshCode,  
scalar=True,

+   readDest=True)
+# SQRDMULby element)
 sqrdmulhCode = '''
 FPSCR fpscr = (FPSCR) FpscrQc;
 destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2 +
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 4d866d0..5526055 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -312,6 +312,21 @@
 }

 bool
+HaveQRDMLAHExt(ThreadContext * tc)
+{
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+bool aarch32 = (cpsr.width == 1);
+if (aarch32) {
+    uint32_t  isar5 = tc->readMiscReg(MISCREG_ID_ISAR5);
+return bits(isar5, 27, 24) == 0x1;
+
+} else {
+AA64ISAR0 id_aa64isar0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
+return id_aa64isar0.rdm;
+}
+}
+
+bool
 HavePACExt(ThreadContext *tc)
 {
 AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 636625d..5084e52 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -151,6 +151,7 @@
 return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
 }

+bool HaveQRDMLAHExt(ThreadContext * tc);
 bool HavePACExt(ThreadContext *tc);
 bool HaveVirtHostExt(ThreadContext *tc);
 bool HaveSecureEL2Ext(ThreadContext *tc);

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LPA

[Jordi Vaquero (Gerrit) via gem5-dev]

n() const
 {
-if (aarch64)
-return bits(data, 47, offsetBits());
-return bits(data, 39, offsetBits());
-}
-
-/** Return the complete physical address given a VA */
-Addr paddr(Addr va) const
-{
-int n = offsetBits();
-if (aarch64)
-return mbits(data, 47, n) | mbits(va, n - 1, 0);
-return mbits(data, 39, n) | mbits(va, n - 1, 0);
+return paddr() >> offsetBits();
 }

 /** Return the physical address of the entry */
 Addr paddr() const
 {
-if (aarch64)
-return mbits(data, 47, offsetBits());
-return mbits(data, 39, offsetBits());
+Addr addr = 0;
+if (aarch64) {
+addr = mbits(data, 47, offsetBits());
+if (physAddrRange == 52 && grainSize == Grain64KB) {
+addr |= bits(data, 15, 12) << 48;
+}
+} else {
+addr = mbits(data, 39, offsetBits());
+}
+return addr;
 }

 /** Return the address of the next page table */
 Addr nextTableAddr() const
 {
 assert(type() == Table);
-if (aarch64)
-return mbits(data, 47, grainSize);
-else
-return mbits(data, 39, 12);
+Addr table_address = 0;
+if (aarch64) {
+table_address = mbits(data, 47, grainSize);
+// Using 52bit if Armv8.2-LPA is implemented
+if (physAddrRange == 52 && grainSize == Grain64KB)
+table_address |= bits(data, 15, 12) << 48;
+} else {
+table_address = mbits(data, 39, 12);
+}
+
+return table_address;
 }

 /** Return the address of the next descriptor */
@@ -854,7 +886,7 @@
 bool haveSecurity;
 bool _haveLPAE;
 bool _haveVirtualization;
-uint8_t physAddrRange;
+uint8_t _physAddrRange;
 bool _haveLargeAsid64;

 /** Statistics */
@@ -896,6 +928,7 @@
 bool haveLPAE() const { return _haveLPAE; }
 bool haveVirtualization() const { return _haveVirtualization; }
 bool haveLargeAsid64() const { return _haveLargeAsid64; }
+uint8_t physAddrRange() const { return _physAddrRange; }
 /** Checks if all state is cleared and if so, completes drain */
 void completeDrain();
 DrainState drain() override;
@@ -962,7 +995,8 @@

 /// Returns true if the address exceeds the range permitted by the
 /// system-wide setting or by the TCR_ELx IPS/PS setting
-static bool checkAddrSizeFaultAArch64(Addr addr, int  
currPhysAddrRange);

+bool checkAddrSizeFaultAArch64(Addr addr, int pa_range);
+
 Fault processWalkAArch64();
 void processWalkWrapper();
 EventFunctionWrapper doProcessEvent;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a0f837d..700988e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -89,6 +89,7 @@
 haveLPAE = tableWalker->haveLPAE();
 haveVirtualization = tableWalker->haveVirtualization();
 haveLargeAsid64 = tableWalker->haveLargeAsid64();
+physAddrRange = tableWalker->physAddrRange();

 if (sys)
 m5opRange = sys->m5opRange();
@@ -949,7 +950,7 @@
 bool selbit = bits(vaddr, 55);
 TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
 int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1,  
currEL(tc));

-int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+int addr_sz = bits(vaddr, topbit, physAddrRange);
 if (addr_sz != 0){
 Fault f;
 if (is_fetch)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 63928cb..e46d400 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -431,6 +431,7 @@
 bool haveLPAE;
 bool haveVirtualization;
 bool haveLargeAsid64;
+uint8_t physAddrRange;

 AddrRange m5opRange;

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index bb4044a..c224a87 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1396,9 +1396,9 @@
   case 0x4:
 return 44;
   case 0x5:
-  case 0x6:
-  case 0x7:
 return 48;
+  case 0x6:
+return 52;
   default:
 panic("Invalid phys. address range encoding");
 }
@@ -1420,6 +1420,8 @@
 return 0x4;
   case 48:
 return 0x5;
+  case 52:
+return 0x6;
   default:
 panic("Invalid phys. address range");
 }

--
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Gerrit-Branch: develop
Gerrit-Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Gerrit

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LVA

[Jordi Vaquero (Gerrit) via gem5-dev]

   ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
+tsz = 64 - currState->tcr.t0sz;
+tg = GrainMap_tg0[currState->tcr.tg0];
+currState->hpd = currState->tcr.hpd;
+currState->isUncacheable = currState->tcr.irgn0 == 0;
+vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
+top_bit, tg, tsz, true);
+
+if (vaddr_fault)
 fault = true;
+break;
+  default:
+// invalid addr if top two bytes are not all 0s
+fault = true;
 }
 ps = currState->tcr.ps;
 break;
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 8f4aaef..ffb83ad 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -956,7 +956,10 @@

 Fault processWalk();
 Fault processWalkLPAE();
-static unsigned adjustTableSizeAArch64(unsigned tsz);
+
+bool checkVAddrSizeFaultAArch64(Addr addr, int top_bit,
+GrainSize granule, int tsz, bool low_range);
+
 /// Returns true if the address exceeds the range permitted by the
 /// system-wide setting or by the TCR_ELx IPS/PS setting
 static bool checkAddrSizeFaultAArch64(Addr addr, int  
currPhysAddrRange);

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 4d866d0..bb4044a 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -326,6 +326,13 @@
 return id_aa64mmfr1.vh;
 }

+bool
+HaveLVA(ThreadContext *tc)
+{
+const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
+return (bool)mm_fr2.varange;
+}
+
 ExceptionLevel
 s1TranslationRegime(ThreadContext* tc, ExceptionLevel el)
 {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 636625d..6ec6403 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -153,6 +153,7 @@

 bool HavePACExt(ThreadContext *tc);
 bool HaveVirtHostExt(ThreadContext *tc);
+bool HaveLVA(ThreadContext *tc);
 bool HaveSecureEL2Ext(ThreadContext *tc);
 bool IsSecureEL2Enabled(ThreadContext *tc);
 bool EL2Enabled(ThreadContext *tc);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
Gerrit-Change-Number: 35955
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LPA

[Jordi Vaquero (Gerrit) via gem5-dev]

-{
-int n = offsetBits();
-if (aarch64)
-return mbits(data, 47, n) | mbits(va, n - 1, 0);
-return mbits(data, 39, n) | mbits(va, n - 1, 0);
+return paddr() >> offsetBits();
 }

 /** Return the physical address of the entry */
 Addr paddr() const
 {
-if (aarch64)
-return mbits(data, 47, offsetBits());
-return mbits(data, 39, offsetBits());
+Addr addr = 0;
+if (aarch64) {
+addr = mbits(data, 47, offsetBits());
+if (physAddrRange == 52 && grainSize == Grain64KB) {
+addr |= bits(data, 15, 12) << 48;
+}
+} else {
+addr = mbits(data, 39, offsetBits());
+}
+return addr;
 }

 /** Return the address of the next page table */
 Addr nextTableAddr() const
 {
 assert(type() == Table);
-if (aarch64)
-return mbits(data, 47, grainSize);
-else
-return mbits(data, 39, 12);
+Addr table_address = 0;
+if (aarch64) {
+table_address = mbits(data, 47, grainSize);
+// Using 52bit if Armv8.2-LPA is implemented
+if (physAddrRange == 52 && grainSize == Grain64KB)
+table_address |= bits(data, 15, 12) << 48;
+} else {
+table_address = mbits(data, 39, 12);
+}
+
+return table_address;
 }

 /** Return the address of the next descriptor */
@@ -854,7 +886,7 @@
 bool haveSecurity;
 bool _haveLPAE;
 bool _haveVirtualization;
-uint8_t physAddrRange;
+uint8_t _physAddrRange;
 bool _haveLargeAsid64;

 /** Statistics */
@@ -896,6 +928,7 @@
 bool haveLPAE() const { return _haveLPAE; }
 bool haveVirtualization() const { return _haveVirtualization; }
 bool haveLargeAsid64() const { return _haveLargeAsid64; }
+uint8_t physAddrRange() const { return _physAddrRange; }
 /** Checks if all state is cleared and if so, completes drain */
 void completeDrain();
 DrainState drain() override;
@@ -962,7 +995,8 @@

 /// Returns true if the address exceeds the range permitted by the
 /// system-wide setting or by the TCR_ELx IPS/PS setting
-static bool checkAddrSizeFaultAArch64(Addr addr, int  
currPhysAddrRange);

+bool checkAddrSizeFaultAArch64(Addr addr, int pa_range);
+
 Fault processWalkAArch64();
 void processWalkWrapper();
 EventFunctionWrapper doProcessEvent;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a0f837d..700988e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -89,6 +89,7 @@
 haveLPAE = tableWalker->haveLPAE();
 haveVirtualization = tableWalker->haveVirtualization();
 haveLargeAsid64 = tableWalker->haveLargeAsid64();
+physAddrRange = tableWalker->physAddrRange();

 if (sys)
 m5opRange = sys->m5opRange();
@@ -949,7 +950,7 @@
 bool selbit = bits(vaddr, 55);
 TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
 int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1,  
currEL(tc));

-int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+int addr_sz = bits(vaddr, topbit, physAddrRange);
 if (addr_sz != 0){
 Fault f;
 if (is_fetch)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 63928cb..e46d400 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -431,6 +431,7 @@
 bool haveLPAE;
 bool haveVirtualization;
 bool haveLargeAsid64;
+uint8_t physAddrRange;

 AddrRange m5opRange;

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index bb4044a..c224a87 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1396,9 +1396,9 @@
   case 0x4:
 return 44;
   case 0x5:
-  case 0x6:
-  case 0x7:
 return 48;
+  case 0x6:
+return 52;
   default:
 panic("Invalid phys. address range encoding");
 }
@@ -1420,6 +1420,8 @@
 return 0x4;
   case 48:
 return 0x5;
+  case 52:
+return 0x6;
   default:
 panic("Invalid phys. address range");
 }

--
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Gerrit-Branch: develop
Gerrit-Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Gerrit-Change-Number: 35956
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LVA

[Jordi Vaquero (Gerrit) via gem5-dev]

te->tcr.irgn0 == 0;
+vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
+top_bit, tg, tsz, true);
+
+if (vaddr_fault)
 fault = true;
+break;
+  default:
+// invalid addr if top two bytes are not all 0s
+fault = true;
 }
 ps = currState->tcr.ps;
 break;
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 8f4aaef..ffb83ad 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -956,7 +956,10 @@

 Fault processWalk();
 Fault processWalkLPAE();
-static unsigned adjustTableSizeAArch64(unsigned tsz);
+
+bool checkVAddrSizeFaultAArch64(Addr addr, int top_bit,
+GrainSize granule, int tsz, bool low_range);
+
 /// Returns true if the address exceeds the range permitted by the
 /// system-wide setting or by the TCR_ELx IPS/PS setting
 static bool checkAddrSizeFaultAArch64(Addr addr, int  
currPhysAddrRange);

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 4d866d0..bb4044a 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -326,6 +326,13 @@
 return id_aa64mmfr1.vh;
 }

+bool
+HaveLVA(ThreadContext *tc)
+{
+const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
+return (bool)mm_fr2.varange;
+}
+
 ExceptionLevel
 s1TranslationRegime(ThreadContext* tc, ExceptionLevel el)
 {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 636625d..6ec6403 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -153,6 +153,7 @@

 bool HavePACExt(ThreadContext *tc);
 bool HaveVirtHostExt(ThreadContext *tc);
+bool HaveLVA(ThreadContext *tc);
 bool HaveSecureEL2Ext(ThreadContext *tc);
 bool IsSecureEL2Enabled(ThreadContext *tc);
 bool EL2Enabled(ThreadContext *tc);

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
Gerrit-Change-Number: 35955
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing SecureEL2 feature for Armv8

[Jordi Vaquero (Gerrit) via gem5-dev]

;& !isHyp && !isSecure;
+stage2DescReq  = hcr.vm && !isStage2 && !isHyp && sec;
 directToStage2 = stage2Req && !sctlr.m;
 } else {
 vmid   = 0;
@@ -1652,7 +1657,8 @@
 fault = checkPermissions(s1Te, req, mode);
 if (stage2Req & (fault == NoFault)) {
 Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb,  
*s1Te,

-req, translation, mode, timing, functional, curTranType);
+req, translation, mode, timing, functional, !(s1Te->ns),
+curTranType);
 fault = s2Lookup->getTe(tc, mergeTe);
 if (s2Lookup->isComplete()) {
 *te = mergeTe;
diff --git a/src/arch/arm/tracers/tarmac_record.cc  
b/src/arch/arm/tracers/tarmac_record.cc

index ee2e8e2..4b7f43d 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -118,7 +118,7 @@
 bool predicate)
   : InstEntry(tarmCtx.thread, tarmCtx.pc, tarmCtx.staticInst,  
predicate)

 {
-secureMode = inSecureState(tarmCtx.thread);
+secureMode = isSecure(tarmCtx.thread);

 auto arm_inst = static_cast(
 tarmCtx.staticInst.get()
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 07740a2..1c44834 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -171,12 +171,15 @@
 }

 bool
-inSecureState(ThreadContext *tc)
+isSecure(ThreadContext *tc)
 {
-SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
-tc->readMiscReg(MISCREG_SCR);
-return ArmSystem::haveSecurity(tc) && inSecureState(
-scr, tc->readMiscReg(MISCREG_CPSR));
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+if (ArmSystem::haveEL(tc, EL3) && !cpsr.width && currEL(tc) == EL3)
+return true;
+if (ArmSystem::haveEL(tc, EL3) && cpsr.width  && cpsr.mode == MODE_MON)
+return true;
+else
+return isSecureBelowEL3(tc);
 }

 bool
@@ -190,14 +193,14 @@
 debugTargetFrom(ThreadContext *tc, bool secure)
 {
 bool route_to_el2;
-if (ArmSystem::haveEL(tc, EL2) && !secure){
-if (ELIs32(tc, EL2)){
+if (ArmSystem::haveEL(tc, EL2) && (!secure || HaveSecureEL2Ext(tc))) {
+if (ELIs32(tc, EL2)) {
 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
-const HDCR hdcr  = tc->readMiscRegNoEffect(MISCREG_HDCR);
+const HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
 route_to_el2 = (hdcr.tde == 1 || hcr.tge == 1);
-}else{
+} else {
 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
+const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
 route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1);
 }
 }else{
@@ -206,10 +209,10 @@
 ExceptionLevel target;
 if (route_to_el2) {
 target = EL2;
-}else if (ArmSystem::haveEL(tc, EL3) && !ArmSystem::highestELIs64(tc)
-  && secure){
+} else if (ArmSystem::haveEL(tc, EL3) && !ArmSystem::highestELIs64(tc)
+  && secure) {
 target = EL3;
-}else{
+} else {
 target = EL1;
 }
 return target;
@@ -344,11 +347,12 @@
 IsSecureEL2Enabled(ThreadContext *tc)
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) {
+if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc) &&
+!ELIs32(tc, EL2)) {
 if (ArmSystem::haveEL(tc, EL3))
 return !ELIs32(tc, EL3) && scr.eel2;
 else
-return inSecureState(tc);
+return isSecure(tc);
 }
 return false;
 }
@@ -393,6 +397,20 @@
 return ELStateUsingAArch32K(tc, el, secure);
 }

+bool
+haveAArch32EL(ThreadContext *tc, ExceptionLevel el)
+{
+if (!ArmSystem::haveEL(tc, el))
+return false;
+else if (!ArmSystem::highestELIs64(tc))
+return true;
+else if (ArmSystem::highestEL(tc) == el)
+return false;
+else if (el == EL0)
+return true;
+return true;
+}
+
 std::pair
 ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
 {
@@ -405,30 +423,33 @@

 bool known, aarch32;
 known = aarch32 = false;
-if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
+if (!haveAArch32EL(tc, el)) {
 // Target EL is the highest one in a system where
 // the highest is using AArch64.
 known = true; aarch32 = false;
+} else if (secure && el == EL2) {
+known = true; aarch32 = false;
     } else if (!ArmSystem::highestELIs64(tc)) {
 // All ELs are using AArch32:
 known = true; aarch32 = true;
+} else if (ArmSystem:

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Trap to EL1 on register DC CVAU

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31774 )


Change subject: arch-arm: Fix Trap to EL1 on register DC CVAU
..

arch-arm: Fix Trap to EL1 on register DC CVAU

Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/insts/misc64.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 49cc6b0..f9f00f0 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -146,7 +146,7 @@
 break;
   case MISCREG_DC_CVAU_Xt:
 trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
-el == EL1;
+el == EL0;
 break;
   case MISCREG_CTR_EL0:
 trap_to_sup = el == EL0 && !sctlr.uct &&

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Gerrit-Change-Number: 31774
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Trap to EL1 on register DC CVAU

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31774 )



Change subject: arch-arm: Fix Trap to EL1 on register DC CVAU
..

arch-arm: Fix Trap to EL1 on register DC CVAU

Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
---
M src/arch/arm/insts/misc64.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 49cc6b0..f9f00f0 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -146,7 +146,7 @@
 break;
   case MISCREG_DC_CVAU_Xt:
 trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
-el == EL1;
+el == EL0;
 break;
   case MISCREG_CTR_EL0:
 trap_to_sup = el == EL0 && !sctlr.uct &&

--
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Gerrit-Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Gerrit-Change-Number: 31774
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add System register trap check for EL1

[Jordi Vaquero (Gerrit) via gem5-dev]

 (el == EL0 && !sctlr.uci)
-return false;
-}

 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
 bool el2_host = EL2Enabled(tc) && hcr.e2h;
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index d3787ff..3578f58 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -730,6 +730,7 @@
 Bitfield<14> hde;
 Bitfield<13> res0_;
 Bitfield<12> udccdis;
+Bitfield<12> tdcc;
 Bitfield<11, 7> res0_2;
 Bitfield<6> err;
 Bitfield<5, 2> moe;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Gerrit-Change-Number: 31694
Gerrit-PatchSet: 6
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add System register trap check for EL1

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31694 )



Change subject: arch-arm: Add System register trap check for EL1
..

arch-arm: Add System register trap check for EL1

Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/miscregs_types.hh
2 files changed, 27 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..cd6386a 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -114,9 +114,17 @@
   uint32_t ) const
 {
 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);

 bool trap_to_sup = false;
 switch (misc_reg) {
+  case MISCREG_DAIF:
+trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
+trap_to_sup = trap_to_sup ||
+(el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
+break;
   case MISCREG_FPCR:
   case MISCREG_FPSR:
   case MISCREG_FPEXC32_EL2:
@@ -127,6 +135,24 @@
 immediate = 0x1E0;
 }
 break;
+  case MISCREG_DC_CVAU_Xt:
+trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
+el == EL1;
+break;
+  case MISCREG_CTR_EL0:
+trap_to_sup = el == EL0 && !sctlr.uct &&
+(!hcr.tge || (!scr.ns && !scr.eel2));
+break;
+   case MISCREG_MDCCSR_EL0:
+ {
+ DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
+ trap_to_sup = el == EL0 && mdscr.tdcc &&
+ (hcr.tge == 0x0 || ( scr.ns == 0x0));
+ }
+ break;
+ case MISCREG_ZCR_EL1:
+trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
+break;
   // Generic Timer
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 trap_to_sup = el == EL0 &&
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index d3787ff..3578f58 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -730,6 +730,7 @@
 Bitfield<14> hde;
 Bitfield<13> res0_;
 Bitfield<12> udccdis;
+Bitfield<12> tdcc;
 Bitfield<11, 7> res0_2;
 Bitfield<6> err;
 Bitfield<5, 2> moe;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Gerrit-Change-Number: 31694
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Fault subsystem adding EL2Enable func

[Jordi Vaquero (Gerrit) via gem5-dev]

hcr.imo));
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
 }

 bool
@@ -1505,7 +1505,7 @@
 {
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
 return fromEL == EL2 ||
-   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
 }

 bool
@@ -1546,7 +1546,7 @@
 PCAlignmentFault::routeToHyp(ThreadContext *tc) const
 {
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
+return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && hcr.tge);
 }

 SPAlignmentFault::SPAlignmentFault()
@@ -1576,21 +1576,18 @@
 assert(ArmSystem::haveSecurity(tc));
 assert(from64);
 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
-return scr.ea;
+return scr.ea || fromEL == EL3;
 }

 bool
 SystemError::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
 assert(from64);

-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
-HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
+HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);

-toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
-(!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
-return toHyp;
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.amo));
 }


@@ -1601,13 +1598,11 @@
 bool
 SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
 {
-const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
-(hcr.tge || mdcr.tde);
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
 }

 ExceptionClass
@@ -1623,13 +1618,10 @@
 bool
 HardwareBreakpoint::routeToHyp(ThreadContext *tc) const
 {
-const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
-(hcr.tge || mdcr.tde);
+return EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde);
 }

 ExceptionClass
@@ -1704,8 +1696,8 @@
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 &&
- (hcr.tge || mdcr.tde));
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
 }

 void
@@ -1744,13 +1736,11 @@
 bool
 SoftwareStepFault::routeToHyp(ThreadContext *tc) const
 {
-const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
-(hcr.tge || mdcr.tde);
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
 }

 ExceptionClass
@@ -1825,6 +1815,13 @@
 {}

 bool
+IllegalInstSetStateFault::routeToHyp(ThreadContext *tc) const
+{
+const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+return EL2Enabled(tc) && fromEL == EL0 && hcr.tge;
+}
+
+bool
 getFaultVAddr(Fault fault, Addr )
 {
 auto arm_fault = dynamic_cast(fault.get());
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 7a2f69e..b911136 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -406,6 +406,8 @@
   public:
 HypervisorCall(ExtMachInst _machInst, uint32_t _imm);

+    bool routeToHyp(ThreadContext *tc) const override;
+bool routeToMonitor(ThreadContext *tc) const override;
 ExceptionClass ec(ThreadContext *tc) const override;
 uint32_t vectorCatchFlag() const override { return 0x; }
 };
@@ -677,6 +679,8 @@
 {
   public:
 IllegalInstSetStateFault();
+
+bool routeToHyp(ThreadContext *tc) const override;
 };

 /*

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Gerrit-Change-Number: 31374
Gerrit-PatchSet: 10
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing SecureEL2 feature for Armv8

[Jordi Vaquero (Gerrit) via gem5-dev]

tc, mergeTe);
 if (s2Lookup->isComplete()) {
 *te = mergeTe;
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index fe9d2eb..86a6777 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -180,17 +180,35 @@
 }

 bool
+isSecure(ThreadContext *tc)
+{
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+if (ArmSystem::haveEL(tc, EL3) && !cpsr.width && currEL(tc)==EL3)
+return true;
+if (ArmSystem::haveEL(tc, EL3) && cpsr.width  && cpsr.mode==MODE_MON)
+return true;
+else
+return isSecureBelowEL3(tc);
+}
+
+bool
 isSecureBelowEL3(ThreadContext *tc)
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
+if (ArmSystem::haveEL(tc, EL3))
+   return scr.ns == 0;
+else if (ArmSystem::haveEL(tc, EL2) &&
+ (!HaveSecureEL2Ext(tc) || !ArmSystem::highestELIs64(tc)))
+   return false;
+else
+   return scr.ns == 0;
 }

 ExceptionLevel
 debugTargetFrom(ThreadContext *tc, bool secure)
 {
 bool route_to_el2;
-if (ArmSystem::haveEL(tc, EL2) && !secure){
+if (ArmSystem::haveEL(tc, EL2) && (!secure || HaveSecureEL2Ext(tc))){
 if (ELIs32(tc, EL2)){
 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
 const HDCR hdcr  = tc->readMiscRegNoEffect(MISCREG_HDCR);
@@ -344,11 +362,12 @@
 IsSecureEL2Enabled(ThreadContext *tc)
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) {
+if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc) &&
+!ELIs32(tc, EL2)) {
 if (ArmSystem::haveEL(tc, EL3))
 return !ELIs32(tc, EL3) && scr.eel2;
 else
-return inSecureState(tc);
+return isSecure(tc);
 }
 return false;
 }
@@ -356,9 +375,8 @@
 bool
 EL2Enabled(ThreadContext *tc)
 {
-SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-return ArmSystem::haveEL(tc, EL2) &&
-   (!ArmSystem::haveEL(tc, EL3) || scr.ns ||  
IsSecureEL2Enabled(tc));

+return  IsSecureEL2Enabled(tc) || (ArmSystem::haveEL(tc, EL2) &&
+   !isSecure(tc));
 }

 bool
@@ -392,6 +410,19 @@
 return ELStateUsingAArch32K(tc, el, secure);
 }

+bool
+haveAArch32EL(ThreadContext *tc, ExceptionLevel el){
+if (!ArmSystem::haveEL(tc, el))
+return false;
+else if (!ArmSystem::highestELIs64(tc))
+return true;
+else if (ArmSystem::highestEL(tc) == el)
+return false;
+else if (el == EL0)
+return true;
+return true;
+}
+
 std::pair
 ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
 {
@@ -404,7 +435,7 @@

 bool known, aarch32;
 known = aarch32 = false;
-if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
+if (!haveAArch32EL(tc, el)) {
 // Target EL is the highest one in a system where
 // the highest is using AArch64.
 known = true; aarch32 = false;
@@ -416,12 +447,11 @@
 bool aarch32_below_el3 = (have_el3 && scr.rw == 0);

 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-bool secEL2 = false;
-bool aarch32_at_el1 = (aarch32_below_el3
- || (have_el2
- && (secEL2 || !isSecureBelowEL3(tc))
- && hcr.rw == 0 && !(hcr.e2h && hcr.tge
-&& HaveVirtHostExt(tc;
+bool secEL2 = HaveSecureEL2Ext(tc) && scr.eel2;
+bool aarch32_at_el1 = (aarch32_below_el3 ||
+   (have_el2 && (secEL2 || !secure) &&
+hcr.rw == 0 && !(hcr.e2h && hcr.tge &&
+ HaveVirtHostExt(tc;

 // Only know if EL0 using AArch32 from PSTATE
 if (el == EL0 && !aarch32_at_el1) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 971306f..e1f123a 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -128,6 +128,8 @@
 return !inUserMode(tc);
 }

+bool isSecure(ThreadContext *tc);
+
 bool isSecureBelowEL3(ThreadContext *tc);

 bool inAArch64(ThreadContext *tc);

--
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Gerrit-Change-Id: Ie59438b1828508e944334420da1d8f4745649056
Gerrit-Change-Number: 31394
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Fault subsystem adding EL2Enable func

[Jordi Vaquero (Gerrit) via gem5-dev]

 fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
 }

 bool
@@ -1546,7 +1546,7 @@
 PCAlignmentFault::routeToHyp(ThreadContext *tc) const
 {
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
+return EL2Enabled(tc) && fromEL <= EL1 && hcr.tge;
 }

 SPAlignmentFault::SPAlignmentFault()
@@ -1576,7 +1576,7 @@
 assert(ArmSystem::haveSecurity(tc));
 assert(from64);
 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
-return scr.ea;
+return scr.ea || fromEL == EL3;
 }

 bool
@@ -1586,11 +1586,9 @@
 assert(from64);

 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
-HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);

-toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
-(!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
-return toHyp;
+toHyp = EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.amo);
+return toHyp || fromEL == EL2;
 }


@@ -1601,13 +1599,11 @@
 bool
 SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
 {
-const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
-(hcr.tge || mdcr.tde);
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
 }

 ExceptionClass
@@ -1623,13 +1619,10 @@
 bool
 HardwareBreakpoint::routeToHyp(ThreadContext *tc) const
 {
-const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
-(hcr.tge || mdcr.tde);
+return EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde);
 }

 ExceptionClass
@@ -1744,13 +1737,11 @@
 bool
 SoftwareStepFault::routeToHyp(ThreadContext *tc) const
 {
-const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
 const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

-return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
-(hcr.tge || mdcr.tde);
+return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 &&
+ (hcr.tge || mdcr.tde));
 }

 ExceptionClass
@@ -1825,6 +1816,13 @@
 {}

 bool
+IllegalInstSetStateFault::routeToHyp(ThreadContext *tc) const
+{
+const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+return (EL2Enabled(tc) && hcr.tge==1 && currEL(tc)==EL0);
+}
+
+bool
 getFaultVAddr(Fault fault, Addr )
 {
 auto arm_fault = dynamic_cast(fault.get());
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 7a2f69e..b911136 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -406,6 +406,8 @@
   public:
 HypervisorCall(ExtMachInst _machInst, uint32_t _imm);

+bool routeToHyp(ThreadContext *tc) const override;
+    bool routeToMonitor(ThreadContext *tc) const override;
 ExceptionClass ec(ThreadContext *tc) const override;
 uint32_t vectorCatchFlag() const override { return 0x; }
 };
@@ -677,6 +679,8 @@
 {
   public:
 IllegalInstSetStateFault();
+
+bool routeToHyp(ThreadContext *tc) const override;
 };

 /*

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Gerrit-Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Gerrit-Change-Number: 31374
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Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix routeToHyp conditions for Excp Type

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30620 )


Change subject: arch-arm: Fix routeToHyp conditions for Excp Type
..

arch-arm: Fix routeToHyp conditions for Excp Type

Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30620
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
1 file changed, 10 insertions(+), 43 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ecc9e4d..743e08d 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -884,17 +884,8 @@
 bool
 SupervisorCall::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
 }

 ExceptionClass
@@ -1028,15 +1019,8 @@
 bool
 SupervisorTrap::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp = false;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge;
 }

 uint32_t
@@ -1323,6 +1307,7 @@

 // if in Hyp mode then stay in Hyp mode
 toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1) && hcr.tge;
 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
 toHyp |= (stage2 ||
   ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
@@ -1384,6 +1369,7 @@

 // if in Hyp mode then stay in Hyp mode
 toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
 toHyp |= (stage2 ||
   ((currEL(tc) != EL2) &&
@@ -1484,15 +1470,9 @@
 bool
 Interrupt::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.imo));
 }

 bool
@@ -1523,15 +1503,9 @@
 bool
 FastInterrupt::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return fromEL == EL2 ||
+   (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
 }

 bool
@@ -1571,15 +1545,8 @@
 bool
 PCAlignmentFault::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp = false;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
 }

 SPAlignmentFault::SPAlignmentFault()
@@ -1590,7 +1557,7 @@
 {
 assert(from64);
 HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && hcr.tge==1;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
 }

 SystemError::SystemError()

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add Check for AddressSize Fault

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30619 )


Change subject: arch-arm: Add Check for AddressSize Fault
..

arch-arm: Add Check for AddressSize Fault

This patch add a check for AddressSize Fault during translation when
MMU is disabled.

Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30619
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/arch/arm/tlb.cc
M src/arch/arm/utility.hh
2 files changed, 19 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f92f8e0..f007f93 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1011,12 +1011,30 @@
 TLB::ArmTranslationType tranType, Addr vaddr, bool  
long_desc_format)

 {
 bool is_fetch  = (mode == Execute);
+bool is_atomic = req->isAtomic();
 req->setPaddr(vaddr);
 // When the MMU is off the security attribute corresponds to the
 // security state of the processor
 if (isSecure)
 req->setFlags(Request::SECURE);

+bool selbit = bits(vaddr, 55);
+TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+if (addr_sz != 0){
+Fault f;
+if (is_fetch)
+f = std::make_shared(vaddr,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+else
+f = std::make_shared( vaddr,
+TlbEntry::DomainType::NoAccess,
+is_atomic ? false : mode==Write,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+return f;
+}
+
 // @todo: double check this (ARM ARM issue C B3.2.1)
 if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
 nmrr.or0 == 0 || prrr.tr0 != 0x2) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 04403fc..b61fc20 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -237,7 +237,7 @@
 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
   bool isInstr);
 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
-   TTBCR tcr, ExceptionLevel el);
+   TCR tcr, ExceptionLevel el);

 static inline bool
 inSecureState(SCR scr, CPSR cpsr)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Gerrit-Change-Number: 30619
Gerrit-PatchSet: 5
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Vector Catch debug exception

[Jordi Vaquero (Gerrit) via gem5-dev]

  bool addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel el);
+bool exceptionTrapping(ThreadContext *tc, ExceptionLevel el,
+   ArmFault* fault);
+bool isVCMatch()
+{
+return vcmatch;
+}
+
+  private:
+Addr getVectorBase(ThreadContext *tc, bool monitor)
+{
+if (monitor) {
+return tc->readMiscReg(MISCREG_MVBAR) & ~0x1F;
+}
+SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+if (sctlr.v) {
+return (Addr) 0x;
+} else {
+Addr vbar = tc->readMiscReg(MISCREG_VBAR) & ~0x1F;
+return vbar;
+}
+}
+
+};
+
 class SelfDebug
 {
   private:
 std::vector arBrkPoints;
 std::vector arWatchPoints;
 SoftwareStep * softStep;
+VectorCatch * vcExcpt;

 bool initialized;
 bool enableTdeTge; // MDCR_EL2.TDE || HCR_EL2.TGE
@@ -287,6 +324,7 @@
 ~SelfDebug()
 {
 delete softStep;
+delete vcExcpt;
 }

 Fault testBreakPoints(ThreadContext *tc, Addr vaddr);
@@ -387,6 +425,7 @@
 {
 softStep->setCPSRD(mask);
 }
+
 inline bool isAArch32()
 {
 return aarch32;
@@ -410,6 +449,12 @@
 return softStep;
 }

+VectorCatch* getVectorCatch(ThreadContext* tc)
+{
+if (!initialized)
+init(tc);
+return vcExcpt;
+}

 bool targetAArch32(ThreadContext * tc)
 {
@@ -468,6 +513,10 @@
 const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
 setenableTDETGE(hcr, mdcr);

+// Enable Vector Catch Exceptions
+const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
+vcExcpt = new VectorCatch(dvid.vectorcatch==0x0, this);
+
 }
 };

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1a26ab5..f92f8e0 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1196,10 +1196,13 @@
 if (fault == NoFault) {
 auto *isa = static_cast(tc->getIsaPtr());
 SelfDebug * sd = isa->getSelfDebug();
-if (mode == Execute) {
+if (mode == Execute)
+{
 const bool d_step = sd->getSstep()->advanceSS(tc);
 if (!d_step) {
-fault = sd->testBreakPoints(tc, req->getVaddr());
+fault = sd->testVectorCatch(tc, req->getVaddr(), nullptr);
+if (fault == NoFault)
+fault = sd->testBreakPoints(tc, req->getVaddr());
 }
 }
 else if (!req->isCacheMaintenance() ||
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 0119e4e..fa877be 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -693,6 +693,7 @@
 EC_WATCHPOINT_LOWER_EL = 0x34,
 EC_WATCHPOINT_CURR_EL  = 0x35,
     EC_SOFTWARE_BREAKPOINT = 0x38,
+    EC_VECTOR_CATCH    = 0x3A,
 EC_SOFTWARE_BREAKPOINT_64  = 0x3C,
 };


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idbef26b16eff059e94ff16fac13bf5708dfe647f
Gerrit-Change-Number: 30618
Gerrit-PatchSet: 8
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of SelfHosted Debug Software step

[Jordi Vaquero (Gerrit) via gem5-dev]

egalExec(false)
+_size(0), _illegalExec(false), _debugStep(false),
+_stepped(false)
 {}

 void
@@ -241,7 +248,8 @@
 }

 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
-_nextItstate(0), _size(0), _illegalExec(false)
+_nextItstate(0), _size(0), _illegalExec(false),
+_debugStep(false), _stepped(false)
 { set(val); }

 bool
@@ -257,6 +265,30 @@
 }

 bool
+debugStep() const
+{
+return _debugStep;
+}
+
+void
+debugStep(bool val)
+{
+_debugStep = val;
+}
+
+bool
+stepped() const
+{
+return _stepped;
+}
+
+void
+stepped(bool val)
+{
+_stepped = val;
+}
+
+bool
 thumb() const
 {
 return flags & ThumbBit;
@@ -491,7 +523,9 @@
 flags == opc.flags && nextFlags == opc.nextFlags &&
 _itstate == opc._itstate &&
 _nextItstate == opc._nextItstate &&
-_illegalExec == opc._illegalExec;
+_illegalExec == opc._illegalExec &&
+_debugStep == opc._debugStep &&
+_stepped == opc._stepped;
 }

 bool
@@ -510,6 +544,8 @@
 SERIALIZE_SCALAR(_itstate);
 SERIALIZE_SCALAR(_nextItstate);
 SERIALIZE_SCALAR(_illegalExec);
+SERIALIZE_SCALAR(_debugStep);
+SERIALIZE_SCALAR(_stepped);
 }

 void
@@ -522,6 +558,8 @@
 UNSERIALIZE_SCALAR(_itstate);
 UNSERIALIZE_SCALAR(_nextItstate);
 UNSERIALIZE_SCALAR(_illegalExec);
+UNSERIALIZE_SCALAR(_debugStep);
+UNSERIALIZE_SCALAR(_stepped);
 }
 };

@@ -648,6 +686,9 @@
 EC_HW_BREAKPOINT   = 0x30,
     EC_HW_BREAKPOINT_LOWER_EL  = 0x30,
     EC_HW_BREAKPOINT_CURR_EL   = 0x31,
+EC_SOFTWARE_STEP   = 0x32,
+EC_SOFTWARE_STEP_LOWER_EL  = 0x32,
+EC_SOFTWARE_STEP_CURR_EL   = 0x33,
 EC_WATCHPOINT  = 0x34,
 EC_WATCHPOINT_LOWER_EL = 0x34,
 EC_WATCHPOINT_CURR_EL  = 0x35,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a64507c64842c34c76ad7f6daa5f4306bd55d2c
Gerrit-Change-Number: 30617
Gerrit-PatchSet: 8
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix minor bug PAUTH comparision with 0

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30615 )


Change subject: arch-arm: Fix minor bug PAUTH comparision with 0
..

arch-arm: Fix minor bug PAUTH comparision with 0

Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30615
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 1c83d77..c88795f 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -706,7 +706,7 @@
 {
 case EL0:
 trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
-  (hcr.tge == '0' || hcr.e2h == 0));
+  (hcr.tge == 0 || hcr.e2h == 0));
 trapEL3 = have_el3 && sc3.api == 0;
 break;
 case EL1:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Gerrit-Change-Number: 30615
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SCR.NS compare to 0

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30614 )


Change subject: arch-arm: Fix SCR.NS compare to 0
..

arch-arm: Fix SCR.NS compare to 0

Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30614
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 82bf61d..8610f99 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -257,7 +257,7 @@
 validModeChange = false;
 // There is no Hyp mode ('11010') in Secure state, so  
that

 // is UNPREDICTABLE
-if (scr.ns == '0' && newMode == MODE_HYP)
+if (scr.ns == 0 && newMode == MODE_HYP)
 validModeChange = false;
 // Cannot move into Hyp mode directly from a Non-secure
 // PL1 mode

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Gerrit-Change-Number: 30614
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix routeToHyp conditions for Excp Type

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30620 )



Change subject: arch-arm: Fix routeToHyp conditions for Excp Type
..

arch-arm: Fix routeToHyp conditions for Excp Type

Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
---
M src/arch/arm/faults.cc
1 file changed, 8 insertions(+), 43 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba8369a..00a70ed 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -857,17 +857,8 @@
 bool
 SupervisorCall::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
 }

 ExceptionClass
@@ -999,15 +990,8 @@
 bool
 SupervisorTrap::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp = false;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return hcr.tge && (currEL(tc) <= EL1) && EL2Enabled(tc);
 }

 uint32_t
@@ -1289,6 +1273,7 @@

 // if in Hyp mode then stay in Hyp mode
 toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1) && hcr.tge;
 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
 toHyp |= (stage2 ||
   ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
@@ -1350,6 +1335,7 @@

 // if in Hyp mode then stay in Hyp mode
 toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
 toHyp |= (stage2 ||
   ((currEL(tc) != EL2) &&
@@ -1450,15 +1436,8 @@
 bool
 Interrupt::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return EL2Enabled(tc) &(tc) <= EL1 && (hcr.tge==1 || hcr.fmo);
 }

 bool
@@ -1489,15 +1468,8 @@
 bool
 FastInterrupt::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return EL2Enabled(tc) &(tc) <= EL1 && (hcr.tge == 1 || hcr.fmo);
 }

 bool
@@ -1537,15 +1509,8 @@
 bool
 PCAlignmentFault::routeToHyp(ThreadContext *tc) const
 {
-bool toHyp = false;
-
-SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
 HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
 }

 SPAlignmentFault::SPAlignmentFault()
@@ -1556,7 +1521,7 @@
 {
 assert(from64);
 HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && hcr.tge==1;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
 }

 SystemError::SystemError()

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add Check for AddressSize Fault

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30619 )



Change subject: arch-arm: Add Check for AddressSize Fault
..

arch-arm: Add Check for AddressSize Fault

This patch add a check for AddressSize Fault during translation when
MMU is disabled.

Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
---
M src/arch/arm/tlb.cc
1 file changed, 18 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a00cba8..8a6e684 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1011,12 +1011,30 @@
 TLB::ArmTranslationType tranType, Addr vaddr, bool  
long_desc_format)

 {
 bool is_fetch  = (mode == Execute);
+bool is_atomic = req->isAtomic();
 req->setPaddr(vaddr);
 // When the MMU is off the security attribute corresponds to the
 // security state of the processor
 if (isSecure)
 req->setFlags(Request::SECURE);

+bool selbit = bits(vaddr, 55);
+TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+if (addr_sz != 0){
+Fault f;
+if (is_fetch)
+f = std::make_shared(vaddr,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+else
+f = std::make_shared( vaddr,
+TlbEntry::DomainType::NoAccess,
+is_atomic ? false : mode==Write,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+return f;
+}
+
 // @todo: double check this (ARM ARM issue C B3.2.1)
 if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
 nmrr.or0 == 0 || prrr.tr0 != 0x2) {

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Vector Catch debug exception

[Jordi Vaquero (Gerrit) via gem5-dev]

  if (fault == NoFault)
+fault = sd->testBreakPoints(tc, req->getVaddr());
 }
 }
 else if (!req->isCacheMaintenance() ||
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 6e502bb..d3fd912 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -712,6 +712,7 @@
 EC_WATCHPOINT_LOWER_EL = 0x34,
 EC_WATCHPOINT_CURR_EL  = 0x35,
 EC_SOFTWARE_BREAKPOINT     = 0x38,
+EC_VECTOR_CATCH= 0x3A,
 EC_SOFTWARE_BREAKPOINT_64  = 0x3C,
 };


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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of SelfHosted Debug Software step

[Jordi Vaquero (Gerrit) via gem5-dev]

,
+EC_SOFTWARE_STEP       = 0x32,
+EC_SOFTWARE_STEP_LOWER_EL  = 0x32,
+EC_SOFTWARE_STEP_CURR_EL   = 0x33,
 EC_WATCHPOINT  = 0x34,
 EC_WATCHPOINT_LOWER_EL = 0x34,
 EC_WATCHPOINT_CURR_EL  = 0x35,

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix minor bug PAUTH comparision with 0

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30615 )



Change subject: arch-arm: Fix minor bug PAUTH comparision with 0
..

arch-arm: Fix minor bug PAUTH comparision with 0

Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 1c83d77..c88795f 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -706,7 +706,7 @@
 {
 case EL0:
 trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
-  (hcr.tge == '0' || hcr.e2h == 0));
+  (hcr.tge == 0 || hcr.e2h == 0));
 trapEL3 = have_el3 && sc3.api == 0;
 break;
 case EL1:

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SCR.NS compare to 0

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30614 )



Change subject: arch-arm: Fix SCR.NS compare to 0
..

arch-arm: Fix SCR.NS compare to 0

Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 82bf61d..8610f99 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -257,7 +257,7 @@
 validModeChange = false;
 // There is no Hyp mode ('11010') in Secure state, so  
that

 // is UNPREDICTABLE
-if (scr.ns == '0' && newMode == MODE_HYP)
+if (scr.ns == 0 && newMode == MODE_HYP)
 validModeChange = false;
 // Cannot move into Hyp mode directly from a Non-secure
 // PL1 mode

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SVE indx inst by sizeof error and dest overwrite

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28228 )


Change subject: arch-arm: Fix SVE indx inst by sizeof error and dest  
overwrite

..

arch-arm: Fix SVE indx inst by sizeof error and dest overwrite

This patch includes two fixes for SVE FMUL; FMLA FMLS AND FCMLA instructions

+ Fixes indexed functions like FMUL, FMLA, FMLS, FCMLA due to its
destination register overwrite with temporary values, wince the imm
can make changes in vector positions that will be read in the future.

+ sizeof return bytes not bits so division of 128 shouild be of 16 instead

Change-Id: I304d1b254a299069c85bbc3319e5a6d4119436d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28228
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 33 insertions(+), 21 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 16597d6..9314ba9 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1835,26 +1835,25 @@
 xc->tcBase());

 // Number of elements in a 128 bit segment
-constexpr unsigned ePerSegment = 128 / sizeof(Element);
+constexpr unsigned ePerSegment = 16 / sizeof(Element);

-'''
-
-code += '''
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
 for (unsigned i = 0; i < eCount; i++) {
-const auto segmentBase = i - i % ePerSegment;
-const auto segmentIdx = segmentBase + index;
+const auto segmentBase = i - i %% ePerSegment;
+const auto segmentIdx = segmentBase + index;

-const Element& srcElem1 = AA64FpOp1_x[i];
-const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
-Element destElem = 0;
+const Element& srcElem1 = AA64FpOp1_x[i];
+const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
+Element destElem = 0;

-'''
-
-code += '''
-%(op)s
-AA64FpDest_x[i] = destElem;
+%(op)s
+auxDest[i] = destElem;
 }
-''' % {'op': op}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
+}''' % {'op':op}

 baseClass = 'SveBinIdxUnpredOp'

@@ -2067,8 +2066,10 @@
 xc->tcBase());

 // Number of elements in a 128 bit segment
-constexpr unsigned ePerSegment = 128 / sizeof(Element);
+constexpr unsigned ePerSegment = 16 / sizeof(Element);

+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
 for (unsigned i = 0; i < eCount; i++) {
 const auto segmentBase = i - i % ePerSegment;
 const auto segmentIdx = segmentBase + index;
@@ -2077,10 +2078,13 @@
 const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
 Element destElem = AA64FpDestMerge_x[i];
 '''
-
 code += '''
 %(op)s
-AA64FpDest_x[i] = destElem;
+auxDest[i] = destElem;
+}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
 }''' % {'op': op}

 iop = InstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp',
@@ -3024,6 +3028,9 @@
 code += '''
 uint32_t eltspersegment = 16 / (2 * sizeof(Element));'''
 code += '''
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
+
 for (int i = 0; i < eCount / 2; ++i) {'''
 if predType == PredType.NONE:
 code += '''
@@ -3067,9 +3074,14 @@
 code += '''
 }'''
 code += '''
-AA64FpDest_x[2 * i] = addend_r;
-AA64FpDest_x[2 * i + 1] = addend_i;
-}'''
+auxDest[2 * i] = addend_r;
+auxDest[2 * i + 1] = addend_i;
+}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
+}
+'''
 iop = InstObjParams(name, 'Sve' + Name,
 'SveComplexIdxOp' if predType == PredType.NONE
   else 'SveComplexOp',

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Gerrit-Change-Number: 28228
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: FCVTZS instruction returns sign extension

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28229 )


Change subject: arch-arm: FCVTZS instruction returns sign extension
..

arch-arm: FCVTZS instruction returns sign extension

This patch fix Fcvtzs instruction adding sign extension instead of
zero extension

Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28229
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 29 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index aa4f194..16597d6 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1516,27 +1516,49 @@
 # Generates definitions for SVE floating-point conversions (always
 # unary, constructive, merging
 def sveCvtInst(name, Name, opClass, types, op, direction=CvtDir.Narrow,
-   decoder='Generic'):
+   decoder='Generic', signed=False):
 global header_output, exec_output, decoders
+
+if signed:
+mask = "SElement msk = mask(sizeof(DElement)*8);"
+assign_code = '''
+int sign_bit = bits(destElem, sizeof(DElement)*8 -1);
+AA64FpDest_x%(bigElemSuffix)s[i] =
+sign_bit? (destElem|~msk): destElem;
+  '''  % {
+   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+   }
+else:
+mask = "";
+assign_code = '''
+AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+'''  % {
+   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+   }
+
 code = sveEnabledCheckCode + '''
 unsigned eCount = ArmStaticInst::getCurSveVecLen<%(bigElemType)s>(
 xc->tcBase());
+%(mask)s
 for (unsigned i = 0; i < eCount; i++) {
 SElement srcElem1 = AA64FpOp1_x%(bigElemSuffix)s[i] &
 mask(sizeof(SElement) * 8);
 DElement destElem = 0;
 if (GpOp_x%(bigElemSuffix)s[i]) {
 %(op)s
-AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+%(assign)s;
 } else {
 AA64FpDest_x%(bigElemSuffix)s[i] =
 AA64FpDestMerge_x%(bigElemSuffix)s[i];
 }
 }
-''' % {'op': op,
-   'bigElemType': 'SElement' if direction == CvtDir.Narrow
+''' % {'bigElemType': 'SElement' if direction == CvtDir.Narrow
  else 'DElement',
-   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'}
+   'op': op, 'mask': mask,
+   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd',
+   'assign': assign_code
+   }
+
 iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
 {'code': code, 'op_class': opClass}, [])
 header_output += SveWideningUnaryPredOpDeclare.subst(iop)
@@ -2743,6 +2765,7 @@
 code = sveEnabledCheckCode + '''
 unsigned eCount = ArmStaticInst::getCurSveVecLen(
 xc->tcBase());
+
 ArmISA::VecRegContainer tmpVecC;
 auto auxDest = tmpVecC.as();
 int firstelem = -1, lastelem = -2;
@@ -3596,7 +3619,7 @@
 'uint32_t, uint32_t',
 'uint64_t, uint32_t',
 'uint64_t, uint64_t'),
-   fcvtzsCode, CvtDir.Narrow)
+   fcvtzsCode, CvtDir.Narrow, signed=True)
 sveCvtInst('fcvtzs', 'FcvtzsWiden', 'SimdCvtOp',
('uint16_t, uint32_t',
 'uint16_t, uint64_t',

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Gerrit-Change-Number: 28229
Gerrit-PatchSet: 3
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of ARMv8 SelfDebug Watchpoints

[Jordi Vaquero (Gerrit) via gem5-dev]

9,15 @@
 if (mode == Execute) {
 fault = sd->testBreakPoints(tc, req->getVaddr());
 }
+else if (!req->isCacheMaintenance() ||
+ (req->isCacheInvalidate() && !req->isCacheClean()))
+{
+bool md = mode == Write ? true: false;
+fault = sd->testWatchPoints(tc, req->getVaddr(), md,
+req->isAtomic(),
+req->getSize(),
+req->isCacheMaintenance());
+}
 }

 return fault;
diff --git a/src/arch/arm/tracers/tarmac_parser.cc  
b/src/arch/arm/tracers/tarmac_parser.cc

index fa7f1be..9ed5bf4 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -123,10 +123,34 @@
 { "dbgwvr1", MISCREG_DBGWVR1 },
 { "dbgwvr2", MISCREG_DBGWVR2 },
 { "dbgwvr3", MISCREG_DBGWVR3 },
+{ "dbgwvr4", MISCREG_DBGWVR4 },
+{ "dbgwvr5", MISCREG_DBGWVR5 },
+{ "dbgwvr6", MISCREG_DBGWVR6 },
+{ "dbgwvr7", MISCREG_DBGWVR7 },
+{ "dbgwvr8", MISCREG_DBGWVR8 },
+{ "dbgwvr9", MISCREG_DBGWVR9 },
+{ "dbgwvr10", MISCREG_DBGWVR10 },
+{ "dbgwvr11", MISCREG_DBGWVR11 },
+{ "dbgwvr12", MISCREG_DBGWVR12 },
+{ "dbgwvr13", MISCREG_DBGWVR13 },
+{ "dbgwvr14", MISCREG_DBGWVR14 },
+{ "dbgwvr15", MISCREG_DBGWVR15 },
 { "dbgwcr0", MISCREG_DBGWCR0 },
 { "dbgwcr1", MISCREG_DBGWCR1 },
 { "dbgwcr2", MISCREG_DBGWCR2 },
 { "dbgwcr3", MISCREG_DBGWCR3 },
+{ "dbgwcr4", MISCREG_DBGWCR4 },
+{ "dbgwcr5", MISCREG_DBGWCR5 },
+{ "dbgwcr6", MISCREG_DBGWCR6 },
+{ "dbgwcr7", MISCREG_DBGWCR7 },
+{ "dbgwcr8", MISCREG_DBGWCR8 },
+{ "dbgwcr9", MISCREG_DBGWCR9 },
+{ "dbgwcr10", MISCREG_DBGWCR10 },
+{ "dbgwcr11", MISCREG_DBGWCR11 },
+{ "dbgwcr12", MISCREG_DBGWCR12 },
+{ "dbgwcr13", MISCREG_DBGWCR13 },
+{ "dbgwcr14", MISCREG_DBGWCR14 },
+{ "dbgwcr15", MISCREG_DBGWCR15 },
 { "dbgdrar", MISCREG_DBGDRAR },
 { "dbgbxvr0", MISCREG_DBGBXVR0 },
 { "dbgbxvr1", MISCREG_DBGBXVR1 },
@@ -418,10 +442,34 @@
 { "dbgwvr1_el1", MISCREG_DBGWVR1_EL1 },
 { "dbgwvr2_el1", MISCREG_DBGWVR2_EL1 },
 { "dbgwvr3_el1", MISCREG_DBGWVR3_EL1 },
+{ "dbgwvr4_el1", MISCREG_DBGWVR4_EL1 },
+{ "dbgwvr5_el1", MISCREG_DBGWVR5_EL1 },
+{ "dbgwvr6_el1", MISCREG_DBGWVR6_EL1 },
+{ "dbgwvr7_el1", MISCREG_DBGWVR7_EL1 },
+{ "dbgwvr8_el1", MISCREG_DBGWVR8_EL1 },
+{ "dbgwvr9_el1", MISCREG_DBGWVR9_EL1 },
+{ "dbgwvr10_el1", MISCREG_DBGWVR10_EL1 },
+{ "dbgwvr11_el1", MISCREG_DBGWVR11_EL1 },
+{ "dbgwvr12_el1", MISCREG_DBGWVR12_EL1 },
+{ "dbgwvr13_el1", MISCREG_DBGWVR13_EL1 },
+{ "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
+{ "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
 { "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 },
 { "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 },
 { "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 },
 { "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 },
+{ "dbgwcr4_el1", MISCREG_DBGWCR4_EL1 },
+{ "dbgwcr5_el1", MISCREG_DBGWCR5_EL1 },
+{ "dbgwcr6_el1", MISCREG_DBGWCR6_EL1 },
+{ "dbgwcr7_el1", MISCREG_DBGWCR7_EL1 },
+{ "dbgwcr8_el1", MISCREG_DBGWCR8_EL1 },
+{ "dbgwcr9_el1", MISCREG_DBGWCR9_EL1 },
+{ "dbgwcr10_el1", MISCREG_DBGWCR10_EL1 },
+{ "dbgwcr11_el1", MISCREG_DBGWCR11_EL1 },
+{ "dbgwcr12_el1", MISCREG_DBGWCR12_EL1 },
+{ "dbgwcr13_el1", MISCREG_DBGWCR13_EL1 },
+{ "dbgwcr14_el1", MISCREG_DBGWCR14_EL1 },
+{ "dbgwcr15_el1", MISCREG_DBGWCR15_EL1 },
 { "mdccsr_el0", MISCREG_MDCCSR_EL0 },
 { "mddtr_el0", MISCREG_MDDTR_EL0 },
 { "mddtrtx_el0", MISCREG_MDDTRTX_EL0 },
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 0dd3dac..3a5e741 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -648,6 +648,9 @@
 EC_HW_BREAKPOINT   = 0x30,
 EC_HW_BREAKPOINT_LOWER_EL  = 0x30,
 EC_HW_BREAKPOINT_CURR_EL   = 0x31,
+EC_WATCHPOINT  = 0x34,
+EC_WATCHPOINT_LOWER_EL = 0x34,
+EC_WATCHPOINT_CURR_EL  = 0x35,
 EC_SOFTWARE_BREAKPOINT = 0x38,
 EC_SOFTWARE_BREAKPOINT_64  = 0x3C,
 };

--
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Gerrit-Change-Number: 28589
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Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix clasta/b and lasta/b simd instructions

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28247 )


Change subject: arch-arm: Fix clasta/b and lasta/b simd instructions
..

arch-arm: Fix clasta/b and lasta/b simd instructions

The simd version of this instructions required zeroing the result
vector except for the first element, that contains the result.

Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 10 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 06ff728..aa4f194 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2432,7 +2432,16 @@
 elif destType == DstRegType.SimdFpScalar:
 code += ''' else {
 AA64FpDest_x[0] = AA64FpDestMerge_x[0];
-}'''
+}
+'''
+if destType == DstRegType.SimdFpScalar:
+# This section will extend zeros to the simdFP scalar
+# intructions for lasta/b and Clasta/b
+code += '''
+for (int i = 1; i < eCount; ++i) {
+AA64FpDest_x[i] = (Element)0x0;
+}
+'''
 iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp',
 {'code': code, 'op_class': opClass,
  'isCond': 'true' if isCond else 'false',

--
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Gerrit-Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Gerrit-Change-Number: 28247
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix clasta/b and lasta/b simd instructions

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28247 )



Change subject: arch-arm: Fix clasta/b and lasta/b simd instructions
..

arch-arm: Fix clasta/b and lasta/b simd instructions

The simd version of this instructions required zeroing the result
vector except for the first element, that contains the result.

Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 612e3c7..2d4d60a 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2434,7 +2434,16 @@
 elif destType == DstRegType.SimdFpScalar:
 code += ''' else {
 AA64FpDest_x[0] = AA64FpDestMerge_x[0];
-}'''
+}
+'''
+if destType == DstRegType.SimdFpScalar:
+# This section will extend zeros to the simdFP scalar
+# intructions for lasta/b and Clasta/b
+code += '''
+for (int i = 1; i < eCount; ++i) {
+AA64FpDest_x[i] = (Element)0x0;
+}
+'''
 iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp',
 {'code': code, 'op_class': opClass,
  'isCond': 'true' if isCond else 'false',

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Sve Fcmla indexed instruction

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28227 )


Change subject: arch-arm: Fix Sve Fcmla indexed instruction
..

arch-arm: Fix Sve Fcmla indexed instruction

Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.

Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28227
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve.isa
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa  
b/src/arch/arm/isa/formats/sve_2nd_level.isa

index b6f8340..53fd80d 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2799,12 +2799,12 @@
 case 2:
 zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
 imm = bits(machInst, 20, 19);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
 zda, zn, zm, rot, imm);
 case 3:
 zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
 imm = bits(machInst, 20);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
 zda, zn, zm, rot, imm);
 }
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index deb12bc..06ff728 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3558,7 +3558,7 @@
 sveCmpInst('fcmuo', 'Fcmuo', 'SimdFloatCmpOp', fpTypes, fcmuoCode)
 # FCMLA (indexed)
 sveComplexMulAddInst('fcmla', 'Fcmlai', 'SimdFloatMultAccOp',
-fpTypes[1:], predType = PredType.NONE)
+fpTypes[:2], predType = PredType.NONE)
 # FCMLA (vectors)
 sveComplexMulAddInst('fcmla', 'Fcmlav', 'SimdFloatMultAccOp',
 fpTypes, predType = PredType.MERGE)

--
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Gerrit-Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Gerrit-Change-Number: 28227
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: FCVTZS instruction returns sign extension

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28229 )



Change subject: arch-arm: FCVTZS instruction returns sign extension
..

arch-arm: FCVTZS instruction returns sign extension

This patch fix Fcvtzs instruction adding sign extension instead of
zero extension

Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 28 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 612e3c7..01abe49 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1518,27 +1518,48 @@
 # Generates definitions for SVE floating-point conversions (always
 # unary, constructive, merging
 def sveCvtInst(name, Name, opClass, types, op, direction=CvtDir.Narrow,
-   decoder='Generic'):
+   decoder='Generic', signed=False):
 global header_output, exec_output, decoders
 code = sveEnabledCheckCode + '''
 unsigned eCount = ArmStaticInst::getCurSveVecLen<%(bigElemType)s>(
 xc->tcBase());
+''' % {'bigElemType': 'SElement' if direction == CvtDir.Narrow
+ else 'DElement'}
+if signed:
+code += '''
+SElement msk = mask(sizeof(DElement)*8);
+ '''
+assign_code = '''
+int sign_bit = bits(destElem, sizeof(DElement)*8 -1);
+AA64FpDest_x%(bigElemSuffix)s[i] =
+sign_bit? (destElem|~msk): destElem;
+  '''  % {
+   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+   }
+else:
+assign_code = '''
+AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+'''  % {
+   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+   }
+
+code += '''
 for (unsigned i = 0; i < eCount; i++) {
 SElement srcElem1 = AA64FpOp1_x%(bigElemSuffix)s[i] &
 mask(sizeof(SElement) * 8);
 DElement destElem = 0;
 if (GpOp_x%(bigElemSuffix)s[i]) {
 %(op)s
-AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+%(assign)s;
 } else {
 AA64FpDest_x%(bigElemSuffix)s[i] =
 AA64FpDestMerge_x%(bigElemSuffix)s[i];
 }
 }
 ''' % {'op': op,
-   'bigElemType': 'SElement' if direction == CvtDir.Narrow
- else 'DElement',
-   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'}
+   'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd',
+   'assign': assign_code
+   }
 iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
 {'code': code, 'op_class': opClass}, [])
 header_output += SveWideningUnaryPredOpDeclare.subst(iop)
@@ -2736,6 +2757,7 @@
 code = sveEnabledCheckCode + '''
 unsigned eCount = ArmStaticInst::getCurSveVecLen(
 xc->tcBase());
+
 ArmISA::VecRegContainer tmpVecC;
 auto auxDest = tmpVecC.as();
 int firstelem = -1, lastelem = -2;
@@ -3589,7 +3611,7 @@
 'uint32_t, uint32_t',
 'uint64_t, uint32_t',
 'uint64_t, uint64_t'),
-   fcvtzsCode, CvtDir.Narrow)
+   fcvtzsCode, CvtDir.Narrow, signed=True)
 sveCvtInst('fcvtzs', 'FcvtzsWiden', 'SimdCvtOp',
('uint16_t, uint32_t',
 'uint16_t, uint64_t',

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Gerrit-Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Gerrit-Change-Number: 28229
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SVE indx inst by sizeof error and dest overwrite

[Jordi Vaquero (Gerrit) via gem5-dev]

 sveComplexMulAddInst('fcmla', 'Fcmlav', 'SimdFloatMultAccOp',
 fpTypes, predType = PredType.MERGE)

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Sve Fcmla indexed instruction

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28227 )



Change subject: arch-arm: Fix Sve Fcmla indexed instruction
..

arch-arm: Fix Sve Fcmla indexed instruction

Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.

Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve.isa
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa  
b/src/arch/arm/isa/formats/sve_2nd_level.isa

index b6f8340..53fd80d 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2799,12 +2799,12 @@
 case 2:
 zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
 imm = bits(machInst, 20, 19);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
 zda, zn, zm, rot, imm);
 case 3:
 zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
 imm = bits(machInst, 20);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
 zda, zn, zm, rot, imm);
 }
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b4c7fe5..19c3a0f 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3558,7 +3558,7 @@
 sveCmpInst('fcmuo', 'Fcmuo', 'SimdFloatCmpOp', fpTypes, fcmuoCode)
 # FCMLA (indexed)
 sveComplexMulAddInst('fcmla', 'Fcmlai', 'SimdFloatMultAccOp',
-fpTypes[1:], predType = PredType.NONE)
+fpTypes[:2], predType = PredType.NONE)
 # FCMLA (vectors)
 sveComplexMulAddInst('fcmla', 'Fcmlav', 'SimdFloatMultAccOp',
 fpTypes, predType = PredType.MERGE)

--
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Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[develop]: arch: Fix VecReg container alignement to 128bits view

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27968 )


Change subject: arch: Fix VecReg container alignement to 128bits view
..

arch: Fix VecReg container alignement to 128bits view

This Patch will fix the alignment problem that appears sometimes
when we try to create a view of 128 bits over the VecRegContainer
object.

That container is initially created as std::array, so
there is no obligation to be aligned to 16 bytes. This patches forces
all containers to be aligned to 16 bytes.

The problem has been observed in the Jira Issue:
https://gem5.atlassian.net/browse/GEM5-320

Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27968
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ciro Santilli 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/generic/vec_reg.hh
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Ciro Santilli: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 4156ac5..e26cf8b 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -279,7 +279,8 @@
 static constexpr inline size_t size() { return SIZE; };
 using Container = std::array;
   private:
-Container container;
+// 16-byte aligned to support 128bit element view
+alignas(16) Container container;
 using MyClass = VecRegContainer;

   public:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Gerrit-Change-Number: 27968
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: Victor Soria 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Fix VecReg container alignement to 128bits view

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27968 )



Change subject: arch: Fix VecReg container alignement to 128bits view
..

arch: Fix VecReg container alignement to 128bits view

This Patch will fix the alignment problem that appears sometimes
when we try to create a view of 128 bits over the VecRegContainer
object.

That container is initially created as std::array, so
there is no obligation to be aligned to 16 bytes. This patches forces
all containers to be aligned to 16 bytes.

The problem has been observed in the Jira Issue:
https://gem5.atlassian.net/browse/GEM5-320

Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
---
M src/arch/generic/vec_reg.hh
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 4156ac5..e26cf8b 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -279,7 +279,8 @@
 static constexpr inline size_t size() { return SIZE; };
 using Container = std::array;
   private:
-Container container;
+// 16-byte aligned to support 128bit element view
+alignas(16) Container container;
 using MyClass = VecRegContainer;

   public:

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Gerrit-Change-Number: 27968
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Hardware Breakpoint exception

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27967 )



Change subject: arch-arm: Implementation of Hardware Breakpoint exception
..

arch-arm: Implementation of Hardware Breakpoint exception

This code implementes hardware breakpoint exception as part of
software debug explained in ARMv8 reference manual ChapterD2.

+ ArmISA.py: Modify register to allow up to 15 Breakpoint registers
+ Sconscript: Add new file self_debug
+ faults.cc/hh: Defintion and implementation of HardwareBreakpoint
exception inheriting ArmFault.
+ isa.cc/hh: ArmISA contains now an attribute pointing to the SelfDebug
 object that will be used to be access SelfDebug infrastructure
 Added special cases for setMiscReg to cache debug enable bits.
+ miscregs.hh/cc: Definition and initialization of DBGDCn and DBGDVn
  registers.
+ tlb.cc/hh: We include the access to check for breakpoint instruction as
 part of the tlb translation process, checking if it comes from  
a

 fetch in the itlb
+ types.hh: Definition of new bitwise register types.
+ utility.cc/hh: Definition and implementation of auxiliar functions for
the selfDebug.
+ self_debug.hh/cc: Main files that include the implemenattion of
breakpoint checks, selfdebug enable and auxiliar functions.

Change-Id: I0e2a4be7f778de560c512253a9148da61e3e7e7a
---
M src/arch/arm/ArmISA.py
M src/arch/arm/SConscript
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
A src/arch/arm/self_debug.cc
A src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
18 files changed, 1,682 insertions(+), 71 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 2641ec3..b030e6c 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -90,8 +90,8 @@
 id_aa64afr1_el1 = Param.UInt64(0x,
 "AArch64 Auxiliary Feature Register 1")

-# 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
-id_aa64dfr0_el1 = Param.UInt64(0x00101006,
+# 1 CTX CMPs | 2 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
+id_aa64dfr0_el1 = Param.UInt64(0x0010F006,
 "AArch64 Debug Feature Register 0")
 # Reserved for future expansion
 id_aa64dfr1_el1 = Param.UInt64(0x,
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index e51437e..958236e 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -83,6 +83,7 @@
 Source('stacktrace.cc')
 Source('system.cc')
 Source('table_walker.cc')
+Source('self_debug.cc')
 Source('stage2_mmu.cc')
 Source('stage2_lookup.cc')
 Source('tlb.cc')
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 22894f3..ba8369a 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -281,6 +281,10 @@
 "Software Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
 0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT
 );
+template<> ArmFault::FaultVals ArmFaultVals::vals(
+"Hardware Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
+0, 0, 0, 0, true, false, false,  EC_HW_BREAKPOINT
+);
 template<> ArmFault::FaultVals ArmFaultVals::vals(
 // Some dummy values
 "ArmSev Flush",  0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -1075,6 +1079,16 @@
 } else if (stage2) {
 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
 tc->setMiscReg(T::HFarIndex,  OVAddr);
+} else if (debug > ArmFault::NODEBUG) {
+DBGDS32 Rext =  tc->readMiscReg(MISCREG_DBGDSCRext);
+tc->setMiscReg(T::FarIndex, faultAddr);
+if (debug == ArmFault::BRKPOINT){
+Rext.moe = 0x1;
+}
+
+tc->setMiscReg(T::FsrIndex, fsr);
+tc->setMiscReg(MISCREG_DBGDSCRext, Rext);
+
 } else {
 tc->setMiscReg(T::FsrIndex, fsr);
 tc->setMiscReg(T::FarIndex, faultAddr);
@@ -1277,9 +1291,10 @@
 toHyp = scr.ns && (currEL(tc) == EL2);
 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
 toHyp |= (stage2 ||
-  ((source == DebugEvent) && hdcr.tde && (currEL(tc) != EL2)) | 
|

-   ((source == SynchronousExternalAbort) && hcr.tge &&
-(currEL(tc) == EL0))) && !inSecureState(tc);
+  ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
+   (currEL(tc) != EL2)) ||
+  ((source == SynchronousExternalAbort) && hcr.tge  &&
+   

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: ARMv8.3 CompNum, SIMD complex number support

[Jordi Vaquero (Gerrit)]

laCode % {'rot': '12, 11', 'index': 'i'}
+threeEqualRegInstX("fcmla", "FcmlaDX", "SimdFloatMultAccOp",
+   ("uint16_t", "uint32_t"), 2, fcmla_vec, True,
+   complex=True)
+threeEqualRegInstX("fcmla", "FcmlaQX", "SimdFloatMultAccOp",
+   floatTypes, 4, fcmla_vec, True, complex=True)
 # CLS
 clsCode = '''
 unsigned count = 0;
diff --git a/src/arch/arm/isa/templates/neon.isa  
b/src/arch/arm/isa/templates/neon.isa

index ee38c2b..39e6d22 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -215,12 +215,18 @@

 const unsigned rCount = %(r_count)d;
 const unsigned eCount = rCount * sizeof(uint32_t) /  
sizeof(Element);

+const unsigned eCountFull = 4 * sizeof(uint32_t) / sizeof(Element);

 union RegVect {
 uint32_t regs[rCount];
 Element elements[eCount];
 };

+union FullRegVect {
+uint32_t regs[4];
+Element elements[eCountFull];
+};
+
 if (%(predicate_test)s)
 {
 %(code)s;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7f11ce88137dad077d2cad698dcaa9a79a3f317b
Gerrit-Change-Number: 27183
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: ARMv8.3 CompNum, SIMD complex number support

[Jordi Vaquero (Gerrit)]

   floatTypes, 4, fcmla_vec, True, complex=True)
 # CLS
 clsCode = '''
 unsigned count = 0;
diff --git a/src/arch/arm/isa/templates/neon.isa  
b/src/arch/arm/isa/templates/neon.isa

index ee38c2b..39e6d22 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -215,12 +215,18 @@

 const unsigned rCount = %(r_count)d;
 const unsigned eCount = rCount * sizeof(uint32_t) /  
sizeof(Element);

+const unsigned eCountFull = 4 * sizeof(uint32_t) / sizeof(Element);

 union RegVect {
 uint32_t regs[rCount];
 Element elements[eCount];
 };

+union FullRegVect {
+uint32_t regs[4];
+Element elements[eCountFull];
+};
+
 if (%(predicate_test)s)
 {
 %(code)s;

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Gerrit-Branch: develop
Gerrit-Change-Id: I7f11ce88137dad077d2cad698dcaa9a79a3f317b
Gerrit-Change-Number: 27183
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.3-JSConv

[Jordi Vaquero (Gerrit)]

sa/formats/fp.isa  
b/src/arch/arm/isa/formats/fp.isa

index 133f918..42f0ee8 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -2761,6 +2761,14 @@
 return new VcvtSIntFpD(machInst, vd, vm);
 }
 }
+  case 0x9:
+if (bits(machInst, 31, 28) != 0xF
+&& bits(machInst, 27, 23) == 0x1D) {
+vd = (IntRegIndex)(bits(machInst, 22) |
+ (bits(machInst, 15, 12) << 1));
+return new VjcvtSFixedFpD(machInst, vd, vm);
+}
+break;
   case 0xa:
 {
 const bool half = (bits(machInst, 7) == 0);
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index df4d583..5e6a0a6 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -977,6 +977,24 @@
 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);

+vjcvtSFixedFpDCode = vfpEnabledCheckCode + '''
+FPSCR fpscr = (FPSCR) FpscrExc;
+VfpSavedState state = prepFpState(fpscr.rMode);
+uint64_t cOp1 = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw <<  
32));

+uint8_t nz;
+FpDest_uw = fplibFPToFixedJS(cOp1, fpscr, false, nz);
+finishVfp(fpscr, state, fpscr.fz);
+FpCondCodes = fpscr & FpCondCodesMask;
+FpscrExc = fpscr;
+'''
+vjcvtSFixedFpDIop =  
InstObjParams("vjcvt", "VjcvtSFixedFpD", "FpRegRegOp",

+ { "code": vjcvtSFixedFpDCode,
+   "predicate_test": predicateTest,
+   "op_class": "SimdFloatCvtOp" }, [])
+header_output += FpRegRegOpDeclare.subst(vjcvtSFixedFpDIop);
+decoder_output += FpRegRegOpConstructor.subst(vjcvtSFixedFpDIop);
+exec_output += PredOpExecute.subst(vjcvtSFixedFpDIop);
+
 vcvtFpUIntSRCode = vfpEnabledCheckCode + '''
 FPSCR fpscr = (FPSCR) FpscrExc;
 VfpSavedState state = prepFpState(fpscr.rMode);
diff --git a/src/arch/arm/isa/insts/fp64.isa  
b/src/arch/arm/isa/insts/fp64.isa

index 7decbac..409780a 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -837,6 +837,29 @@
 decoder_output +=  
AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop);

 exec_output+= BasicExecute.subst(fcvtFpFixedIop);

+def buildFpJsCvtFixedOp():
+global header_output, decoder_output, exec_output
+
+fcvtFpFixedCode = vfp64EnabledCheckCode + '''
+FPSCR fpscr = (FPSCR) FpscrExc;
+uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw <<  
32;

+uint8_t nz;
+WDest = fplibFPToFixedJS(cOp1, fpscr, true, nz);
+CondCodesNZ = nz;
+CondCodesV = 0;
+CondCodesC = 0;
+FpscrExc = fpscr;
+''';
+
+instName = "FJcvtFpSFixedDW"
+mnem = "fjcvtzs"
+fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegOp",
+   { "code": fcvtFpFixedCode,
+ "op_class": "FloatCvtOp" }, [])
+header_output  += FpRegRegOpDeclare.subst(fcvtFpFixedIop);
+decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFixedIop);
+exec_output+= BasicExecute.subst(fcvtFpFixedIop);
+
 # Generates the variants of the fixed to floating point instructions
 def buildFixedCvtFpOp(isSigned, isDouble, isXReg):
 global header_output, decoder_output, exec_output
@@ -886,6 +909,7 @@
 for isSigned in True, False:
 buildFpCvtFixedOp(isSigned, isDouble, isXReg)
 buildFixedCvtFpOp(isSigned, isDouble, isXReg)
+buildFpJsCvtFixedOp();
 }};

 let {{

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28
Gerrit-Change-Number: 25023
Gerrit-PatchSet: 7
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: This commit adds Pointer Authentication feature.

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25024 )



Change subject: arch-arm: This commit adds Pointer Authentication feature.
..

arch-arm: This commit adds Pointer Authentication feature.

+ ArmISA.py: Enabling the feature adding  QARMA algorithm as default.
+ faults.cc/faults.hh: Add PACTrapFault
+ includes/insts.isa: Adding new isa files.
+ aarch64.isa: Add decode part for PAC instructions
+ pauth.isa: Isa for PAC instructions
+ misc64.isa: PAC instructions templates
+ miscregs.cc/hh/types: New Registers for PAC Key low/high.
+ types.hh: Modification of system registers that were incomplete
for ARMv8
+ utility.hh: Add isSecureEL2 enabled. The function is there but will
  always return false for now.
+ pauth_helpers.hh/cc: Implementation of auxiliar functions and derivates.
+ qarma.hh/cc: This functions follow ARMv8 reference pseudo code
  implementing QARMA block cipher algorithms.

Change-Id: I3095a1279204206d9a816a4fb7fc176c18f9680b
---
M src/arch/arm/ArmISA.py
M src/arch/arm/SConscript
M src/arch/arm/faults.cc
M src/arch/arm/insts/branch64.cc
M src/arch/arm/insts/branch64.hh
M src/arch/arm/insts/misc.cc
M src/arch/arm/insts/misc.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/branch64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
A src/arch/arm/isa/insts/pauth.isa
M src/arch/arm/isa/templates/branch64.isa
M src/arch/arm/isa/templates/misc64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
A src/arch/arm/pauth_helpers.cc
A src/arch/arm/pauth_helpers.hh
A src/arch/arm/qarma.cc
A src/arch/arm/qarma.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
28 files changed, 2,252 insertions(+), 133 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 7b71895..c4b0250 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -102,8 +102,9 @@
 # !CRC32 | !SHA2 | !SHA1 | !AES
 id_aa64isar0_el1 = Param.UInt64(0x,
 "AArch64 Instruction Set Attribute Register 0")
-# Reserved for future expansion
-id_aa64isar1_el1 = Param.UInt64(0x,
+
+# GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1
+id_aa64isar1_el1 = Param.UInt64(0x0110,
 "AArch64 Instruction Set Attribute Register 1")

 # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index caea1c4..8e00ba9 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -76,8 +76,10 @@
 Source('freebsd/system.cc')
 Source('miscregs.cc')
 Source('nativetrace.cc')
+Source('pauth_helpers.cc')
 Source('pmu.cc')
 Source('process.cc')
+Source('qarma.cc')
 Source('remote_gdb.cc')
 Source('semihosting.cc')
 Source('stacktrace.cc')
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index bd38fdc..9b42d0c 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -693,7 +693,7 @@
 ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);

 // Set PC to start of exception handler
-Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
+Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true);
 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x  
PC:%#x "

 "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
 new_pc, arm_inst ? csprintf("inst: %#x",  
arm_inst->encoding()) :

diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc
index d0a4f29..1c47b42 100644
--- a/src/arch/arm/insts/branch64.cc
+++ b/src/arch/arm/insts/branch64.cc
@@ -100,6 +100,18 @@
 }

 std::string
+BranchRegReg64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printIntReg(ss, op1);
+ccprintf(ss, ", ");
+printIntReg(ss, op2);
+return ss.str();
+}
+
+std::string
 BranchRet64::generateDisassembly(
 Addr pc, const SymbolTable *symtab) const
 {
@@ -111,6 +123,17 @@
 }

 std::string
+BranchRetA64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+if (op1 != INTREG_X30)
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
 BranchEret64::generateDisassembly(
 Addr pc, const SymbolTable *symtab) const
 {
@@ -120,6 +143,15 @@
 }

 std::string
+BranchEretA64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+return ss.str();
+}
+
+std::string
 

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implementation for Javascript converstion float point instr...

[Jordi Vaquero (Gerrit)]

;& bits(machInst, 27, 23) == 0x1D) {
+vd = (IntRegIndex)(bits(machInst, 22) |
+ (bits(machInst, 15, 12) << 1));
+return new VjcvtSFixedFpD(machInst, vd, vm);
+}
+break;
   case 0xa:
 {
 const bool half = (bits(machInst, 7) == 0);
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index df4d583..5e6a0a6 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -977,6 +977,24 @@
 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);

+vjcvtSFixedFpDCode = vfpEnabledCheckCode + '''
+FPSCR fpscr = (FPSCR) FpscrExc;
+VfpSavedState state = prepFpState(fpscr.rMode);
+uint64_t cOp1 = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw <<  
32));

+uint8_t nz;
+FpDest_uw = fplibFPToFixedJS(cOp1, fpscr, false, nz);
+finishVfp(fpscr, state, fpscr.fz);
+FpCondCodes = fpscr & FpCondCodesMask;
+FpscrExc = fpscr;
+'''
+vjcvtSFixedFpDIop =  
InstObjParams("vjcvt", "VjcvtSFixedFpD", "FpRegRegOp",

+ { "code": vjcvtSFixedFpDCode,
+   "predicate_test": predicateTest,
+   "op_class": "SimdFloatCvtOp" }, [])
+header_output += FpRegRegOpDeclare.subst(vjcvtSFixedFpDIop);
+decoder_output += FpRegRegOpConstructor.subst(vjcvtSFixedFpDIop);
+exec_output += PredOpExecute.subst(vjcvtSFixedFpDIop);
+
 vcvtFpUIntSRCode = vfpEnabledCheckCode + '''
 FPSCR fpscr = (FPSCR) FpscrExc;
 VfpSavedState state = prepFpState(fpscr.rMode);
diff --git a/src/arch/arm/isa/insts/fp64.isa  
b/src/arch/arm/isa/insts/fp64.isa

index 7decbac..409780a 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -837,6 +837,29 @@
 decoder_output +=  
AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop);

 exec_output+= BasicExecute.subst(fcvtFpFixedIop);

+def buildFpJsCvtFixedOp():
+global header_output, decoder_output, exec_output
+
+fcvtFpFixedCode = vfp64EnabledCheckCode + '''
+FPSCR fpscr = (FPSCR) FpscrExc;
+uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw <<  
32;

+uint8_t nz;
+WDest = fplibFPToFixedJS(cOp1, fpscr, true, nz);
+CondCodesNZ = nz;
+CondCodesV = 0;
+CondCodesC = 0;
+FpscrExc = fpscr;
+''';
+
+instName = "FJcvtFpSFixedDW"
+mnem = "fjcvtzs"
+fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegOp",
+   { "code": fcvtFpFixedCode,
+ "op_class": "FloatCvtOp" }, [])
+header_output  += FpRegRegOpDeclare.subst(fcvtFpFixedIop);
+decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFixedIop);
+exec_output+= BasicExecute.subst(fcvtFpFixedIop);
+
 # Generates the variants of the fixed to floating point instructions
 def buildFixedCvtFpOp(isSigned, isDouble, isXReg):
 global header_output, decoder_output, exec_output
@@ -886,6 +909,7 @@
 for isSigned in True, False:
 buildFpCvtFixedOp(isSigned, isDouble, isXReg)
 buildFixedCvtFpOp(isSigned, isDouble, isXReg)
+buildFpJsCvtFixedOp();
 }};

 let {{

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix EL2 target exception level for SP alignment fault.

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24303 )


Change subject: arch-arm: Fix EL2 target exception level for SP alignment  
fault.

..

arch-arm: Fix EL2 target exception level for SP alignment fault.

This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.

Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 5a7b8e8..bd38fdc 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1541,6 +1541,14 @@
 SPAlignmentFault::SPAlignmentFault()
 {}

+bool
+SPAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+assert(from64);
+HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+return EL2Enabled(tc) && hcr.tge==1;
+}
+
 SystemError::SystemError()
 {}

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3f61bc7..508fd03 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -571,6 +571,7 @@
 {
   public:
 SPAlignmentFault();
+bool routeToHyp(ThreadContext *tc) const override;
 };

 /// System error (AArch64 only)

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Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
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Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix EL2 target exception level for SP alignment fault.

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24303 )



Change subject: arch-arm: Fix EL2 target exception level for SP alignment  
fault.

..

arch-arm: Fix EL2 target exception level for SP alignment fault.

This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.

Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 9 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 5a7b8e8..bd38fdc 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1541,6 +1541,14 @@
 SPAlignmentFault::SPAlignmentFault()
 {}

+bool
+SPAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+assert(from64);
+HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+return EL2Enabled(tc) && hcr.tge==1;
+}
+
 SystemError::SystemError()
 {}

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3f61bc7..508fd03 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -571,6 +571,7 @@
 {
   public:
 SPAlignmentFault();
+bool routeToHyp(ThreadContext *tc) const override;
 };

 /// System error (AArch64 only)

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implementation of Hardware Breakpoint exception

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23943 )



Change subject: arch-arm: Implementation of Hardware Breakpoint exception
..

arch-arm: Implementation of Hardware Breakpoint exception

This code implementes hardware breakpoint exception as part of
software debug explained in ARMv8 reference manual ChapterD2.

+ ArmISA.py: Modify register to allow up to 15 Breakpoint registers
+ Sconscript: Add new file self_debug
+ faults.cc/hh: Defintion and implementation of HardwareBreakpoint
exception inheriting ArmFault.
+ isa.cc/hh: ArmISA contains now an attribute pointing to the SelfDebug
 object that will be used to be access SelfDebug infrastructure
 Added special cases for setMiscReg to cache debug enable bits.
+ miscregs.hh/cc: Definition and initialization of DBGDCn and DBGDVn
  registers.
+ tlb.cc/hh: We include the access to check for breakpoint instruction as
 part of the tlb translation process, checking if it comes from  
a

 fetch in the itlb
+ types.hh: Definition of new bitwise register types.
+ utility.cc/hh: Definition and implementation of auxiliar functions for
the selfDebug.
+ self_debug.hh/cc: Main files that include the implemenattion of
breakpoint checks, selfdebug enable and auxiliar functions.

Change-Id: I0e2a4be7f778de560c512253a9148da61e3e7e7a
---
M src/arch/arm/ArmISA.py
M src/arch/arm/SConscript
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
A src/arch/arm/self_debug.cc
A src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
19 files changed, 1,805 insertions(+), 171 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 7b71895..b884c5b 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -92,8 +92,8 @@
 id_aa64afr1_el1 = Param.UInt64(0x,
 "AArch64 Auxiliary Feature Register 1")

-# 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
-id_aa64dfr0_el1 = Param.UInt64(0x00101006,
+# 1 CTX CMPs | 2 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
+id_aa64dfr0_el1 = Param.UInt64(0x0010F006,
 "AArch64 Debug Feature Register 0")
 # Reserved for future expansion
 id_aa64dfr1_el1 = Param.UInt64(0x,
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index caea1c4..c09cbe6 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -83,6 +83,7 @@
 Source('stacktrace.cc')
 Source('system.cc')
 Source('table_walker.cc')
+Source('self_debug.cc')
 Source('stage2_mmu.cc')
 Source('stage2_lookup.cc')
 Source('tlb.cc')
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 5a7b8e8..67abb62 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -286,6 +286,10 @@
 "Software Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
 0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT
 );
+template<> ArmFault::FaultVals ArmFaultVals::vals(
+"Hardware Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
+0, 0, 0, 0, true, false, false,  EC_HW_BREAKPOINT
+);
 template<> ArmFault::FaultVals ArmFaultVals::vals(
 // Some dummy values
 "ArmSev Flush",  0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -1080,6 +1084,16 @@
 } else if (stage2) {
 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
 tc->setMiscReg(T::HFarIndex,  OVAddr);
+} else if (debug > ArmFault::NODEBUG) {
+DBGDS32 Rext =  tc->readMiscReg(MISCREG_DBGDSCRext);
+tc->setMiscReg(T::FarIndex, faultAddr);
+if (debug == ArmFault::BRKPOINT){
+Rext.moe = 0x1;
+}
+
+tc->setMiscReg(T::FsrIndex, fsr);
+tc->setMiscReg(MISCREG_DBGDSCRext, Rext);
+
 } else {
 tc->setMiscReg(T::FsrIndex, fsr);
 tc->setMiscReg(T::FarIndex, faultAddr);
@@ -1282,9 +1296,10 @@
 toHyp = scr.ns && (currEL(tc) == EL2);
 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
 toHyp |= (stage2 ||
-  ((source == DebugEvent) && hdcr.tde && (currEL(tc) != EL2)) | 
|

-   ((source == SynchronousExternalAbort) && hcr.tge &&
-(currEL(tc) == EL0))) && !inSecureState(tc);
+   ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
+(currEL(tc) != EL2)) ||
+   ((source == SynchronousExternalAbort) && hcr.tge  &&
+

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implementation of ARMv8 SelfDebug Watchpoints

[Jordi Vaquero (Gerrit)]

}

 initialized = true ;

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index b2c64e9..a37d113 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1232,6 +1232,15 @@
 {
 fault = sd->testBreakPoints(tc, req->getVaddr());
 }
+else if (!req->isCacheMaintenance() ||
+ (req->isCacheInvalidate() && !req->isCacheClean()))
+{
+bool md = mode == Write ? true: false;
+fault = sd->testWatchPoints(tc, req->getVaddr(), md,
+req->isAtomic(),
+req->getSize(),
+req->isCacheMaintenance());
+}
 }

 return fault;
diff --git a/src/arch/arm/tracers/tarmac_parser.cc  
b/src/arch/arm/tracers/tarmac_parser.cc

index 39ac985..db41949 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -125,10 +125,34 @@
 { "dbgwvr1", MISCREG_DBGWVR1 },
 { "dbgwvr2", MISCREG_DBGWVR2 },
 { "dbgwvr3", MISCREG_DBGWVR3 },
+{ "dbgwvr4", MISCREG_DBGWVR4 },
+{ "dbgwvr5", MISCREG_DBGWVR5 },
+{ "dbgwvr6", MISCREG_DBGWVR6 },
+{ "dbgwvr7", MISCREG_DBGWVR7 },
+{ "dbgwvr8", MISCREG_DBGWVR8 },
+{ "dbgwvr9", MISCREG_DBGWVR9 },
+{ "dbgwvr10", MISCREG_DBGWVR10 },
+{ "dbgwvr11", MISCREG_DBGWVR11 },
+{ "dbgwvr12", MISCREG_DBGWVR12 },
+{ "dbgwvr13", MISCREG_DBGWVR13 },
+{ "dbgwvr14", MISCREG_DBGWVR14 },
+{ "dbgwvr15", MISCREG_DBGWVR15 },
 { "dbgwcr0", MISCREG_DBGWCR0 },
 { "dbgwcr1", MISCREG_DBGWCR1 },
 { "dbgwcr2", MISCREG_DBGWCR2 },
 { "dbgwcr3", MISCREG_DBGWCR3 },
+{ "dbgwcr4", MISCREG_DBGWCR4 },
+{ "dbgwcr5", MISCREG_DBGWCR5 },
+{ "dbgwcr6", MISCREG_DBGWCR6 },
+{ "dbgwcr7", MISCREG_DBGWCR7 },
+{ "dbgwcr8", MISCREG_DBGWCR8 },
+{ "dbgwcr9", MISCREG_DBGWCR9 },
+{ "dbgwcr10", MISCREG_DBGWCR10 },
+{ "dbgwcr11", MISCREG_DBGWCR11 },
+{ "dbgwcr12", MISCREG_DBGWCR12 },
+{ "dbgwcr13", MISCREG_DBGWCR13 },
+{ "dbgwcr14", MISCREG_DBGWCR14 },
+{ "dbgwcr15", MISCREG_DBGWCR15 },
 { "dbgdrar", MISCREG_DBGDRAR },
 { "dbgbxvr0", MISCREG_DBGBXVR0 },
 { "dbgbxvr1", MISCREG_DBGBXVR1 },
@@ -420,10 +444,34 @@
 { "dbgwvr1_el1", MISCREG_DBGWVR1_EL1 },
 { "dbgwvr2_el1", MISCREG_DBGWVR2_EL1 },
 { "dbgwvr3_el1", MISCREG_DBGWVR3_EL1 },
+{ "dbgwvr4_el1", MISCREG_DBGWVR4_EL1 },
+{ "dbgwvr5_el1", MISCREG_DBGWVR5_EL1 },
+{ "dbgwvr6_el1", MISCREG_DBGWVR6_EL1 },
+{ "dbgwvr7_el1", MISCREG_DBGWVR7_EL1 },
+{ "dbgwvr8_el1", MISCREG_DBGWVR8_EL1 },
+{ "dbgwvr9_el1", MISCREG_DBGWVR9_EL1 },
+{ "dbgwvr10_el1", MISCREG_DBGWVR10_EL1 },
+{ "dbgwvr11_el1", MISCREG_DBGWVR11_EL1 },
+{ "dbgwvr12_el1", MISCREG_DBGWVR12_EL1 },
+{ "dbgwvr13_el1", MISCREG_DBGWVR13_EL1 },
+{ "dbgwvr14_el1", MISCREG_DBGWVR14_EL1 },
+{ "dbgwvr15_el1", MISCREG_DBGWVR15_EL1 },
 { "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 },
 { "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 },
 { "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 },
 { "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 },
+{ "dbgwcr4_el1", MISCREG_DBGWCR4_EL1 },
+{ "dbgwcr5_el1", MISCREG_DBGWCR5_EL1 },
+{ "dbgwcr6_el1", MISCREG_DBGWCR6_EL1 },
+{ "dbgwcr7_el1", MISCREG_DBGWCR7_EL1 },
+{ "dbgwcr8_el1", MISCREG_DBGWCR8_EL1 },
+{ "dbgwcr9_el1", MISCREG_DBGWCR9_EL1 },
+{ "dbgwcr10_el1", MISCREG_DBGWCR10_EL1 },
+{ "dbgwcr11_el1", MISCREG_DBGWCR11_EL1 },
+{ "dbgwcr12_el1", MISCREG_DBGWCR12_EL1 },
+{ "dbgwcr13_el1", MISCREG_DBGWCR13_EL1 },
+{ "dbgwcr14_el1", MISCREG_DBGWCR14_EL1 },
+{ "dbgwcr15_el1", MISCREG_DBGWCR15_EL1 },
 { "mdccsr_el0", MISCREG_MDCCSR_EL0 },
 { "mddtr_el0", MISCREG_MDDTR_EL0 },
 { "mddtrtx_el0", MISCREG_MDDTRTX_EL0 },
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 4251292..cfd8dc6 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -649,6 +649,9 @@
 EC_HW_BREAKPOINT   = 0x30,
 EC_HW_BREAKPOINT_LOWER_EL  = 0x30,
 EC_HW_BREAKPOINT_CURR_EL   = 0x31,
+EC_WATCHPOINT  = 0x34,
+EC_WATCHPOINT_LOWER_EL = 0x34,
+EC_WATCHPOINT_CURR_EL  = 0x35,
 EC_SOFTWARE_BREAKPOINT = 0x38,
 EC_SOFTWARE_BREAKPOINT_64  = 0x3C,
 };

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[gem5-dev] Change in gem5/gem5[master]: cpu, mem: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

6 +463,16 @@
 }

 Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
- Request::Flags flags, AtomicOpFunctor *amo_op) override
+ Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 {
-return cpu->amoMem(addr, data, size, flags, amo_op);
+return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
 }

 Fault initiateMemAMO(Addr addr, unsigned int size,
  Request::Flags flags,
- AtomicOpFunctor *amo_op) override
+ AtomicOpFunctorPtr amo_op) override
 {
-return cpu->initiateMemAMO(addr, size, flags, amo_op);
+return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
 }

 /**
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4aa008e..d05eece 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -564,7 +564,7 @@
 Fault
 TimingSimpleCPU::initiateMemAMO(Addr addr, unsigned size,
 Request::Flags flags,
-AtomicOpFunctor *amo_op)
+AtomicOpFunctorPtr amo_op)
 {
 SimpleExecContext _info = *threadInfo[curThread];
 SimpleThread* thread = t_info.thread;
@@ -579,7 +579,8 @@
 traceData->setMem(addr, size, flags);

 RequestPtr req = make_shared(asid, addr, size, flags,
-dataMasterId(), pc, thread->contextId(),  
amo_op);

+dataMasterId(), pc, thread->contextId(),
+std::move(amo_op));

 assert(req->hasAtomicOpFunctor());

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 53e0ed7..27faa17 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -293,7 +293,7 @@
 override;

 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
- AtomicOpFunctor *amo_op) override;
+ AtomicOpFunctorPtr amo_op) override;

 void fetch();
 void sendFetch(const Fault ,
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 324ae38..5094493 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -389,7 +389,7 @@
 InstSeqNum _reqInstSeqNum;

 /** A pointer to an atomic operation */
-AtomicOpFunctor *atomicOpFunctor;
+AtomicOpFunctorPtr atomicOpFunctor;

   public:

@@ -470,9 +470,9 @@

 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
 MasterID mid, Addr pc, ContextID cid,
-AtomicOpFunctor *atomic_op)
+AtomicOpFunctorPtr atomic_op)
 {
-setVirt(asid, vaddr, size, flags, mid, pc, atomic_op);
+setVirt(asid, vaddr, size, flags, mid, pc, std::move(atomic_op));
 setContext(cid);
 }

@@ -489,18 +489,12 @@
   translateDelta(other.translateDelta),
   accessDelta(other.accessDelta), depth(other.depth)
 {
-if (other.atomicOpFunctor)
-atomicOpFunctor = (other.atomicOpFunctor)->clone();
-else
-atomicOpFunctor = nullptr;
+
+atomicOpFunctor.reset(other.atomicOpFunctor ?
+other.atomicOpFunctor->clone() : nullptr);
 }

-~Request()
-{
-if (hasAtomicOpFunctor()) {
-delete atomicOpFunctor;
-}
-}
+~Request() {}

 /**
  * Set up Context numbers.
@@ -533,7 +527,7 @@
  */
 void
 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
-MasterID mid, Addr pc, AtomicOpFunctor *amo_op = nullptr)
+MasterID mid, Addr pc, AtomicOpFunctorPtr amo_op = nullptr)
 {
 _asid = asid;
 _vaddr = vaddr;
@@ -549,7 +543,7 @@
 depth = 0;
 accessDelta = 0;
 translateDelta = 0;
-atomicOpFunctor = amo_op;
+atomicOpFunctor = std::move(amo_op);
 }

 /**
@@ -669,14 +663,14 @@
 bool
 hasAtomicOpFunctor()
 {
-return atomicOpFunctor != NULL;
+return (bool)atomicOpFunctor;
 }

 AtomicOpFunctor *
 getAtomicOpFunctor()
 {
-assert(atomicOpFunctor != NULL);
-return atomicOpFunctor;
+assert(atomicOpFunctor);
+return atomicOpFunctor.get();
 }

 /** Accessor for flags. */

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Gerrit-Branch: master
Gerrit-Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Gerrit-Change-Number: 20919
Gerrit-PatchSet: 7
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: Tuan Ta 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: cpu, mem: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini, Tuan Ta, Jason  
Lowe-Power,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20919

to look at the new patch set (#6).

Change subject: cpu, mem: Changing AtomicOpFunctor* for  
unique_ptr

..

cpu, mem: Changing AtomicOpFunctor* for unique_ptr

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
---
M src/arch/generic/memhelpers.hh
M src/base/types.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/mem/request.hh
18 files changed, 59 insertions(+), 58 deletions(-)


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Gerrit-Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Gerrit-Change-Number: 20919
Gerrit-PatchSet: 6
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: cpu, mem: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20919

to look at the new patch set (#5).

Change subject: cpu, mem: Changing AtomicOpFunctor* for  
unique_ptr

..

cpu, mem: Changing AtomicOpFunctor* for unique_ptr

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
---
M src/arch/generic/memhelpers.hh
M src/base/types.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/mem/request.hh
18 files changed, 59 insertions(+), 58 deletions(-)


--
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Gerrit-Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Gerrit-Change-Number: 20919
Gerrit-PatchSet: 5
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[master]: general: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20919

to look at the new patch set (#4).

Change subject: general: Changing AtomicOpFunctor* for  
unique_ptr

..

general: Changing AtomicOpFunctor* for unique_ptr

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
---
M src/arch/generic/memhelpers.hh
M src/base/types.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/mem/request.hh
18 files changed, 59 insertions(+), 58 deletions(-)


--
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Gerrit-Branch: master
Gerrit-Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Gerrit-Change-Number: 20919
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[master]: mem, cpu: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20919

to look at the new patch set (#3).

Change subject: mem,cpu: Changing AtomicOpFunctor* for  
unique_ptr

..

mem,cpu: Changing AtomicOpFunctor* for unique_ptr

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
---
M src/arch/generic/memhelpers.hh
M src/base/types.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/mem/request.hh
18 files changed, 59 insertions(+), 56 deletions(-)


--
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Gerrit-Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Gerrit-Change-Number: 20919
Gerrit-PatchSet: 3
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: general: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/20919 )


Change subject: general: Changing AtomicOpFunctor* for  
unique_ptr

..

general: Changing AtomicOpFunctor* for unique_ptr

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
---
M src/arch/generic/memhelpers.hh
M src/base/types.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/mem/request.hh
18 files changed, 59 insertions(+), 56 deletions(-)


--
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Gerrit-Branch: master
Gerrit-Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Gerrit-Change-Number: 20919
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: general: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

 dataMasterId(), pc, thread->contextId(),  
amo_op);

+dataMasterId(), pc, thread->contextId(),
+std::move(amo_op));

 assert(req->hasAtomicOpFunctor());

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 53e0ed7..27faa17 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -293,7 +293,7 @@
 override;

 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
- AtomicOpFunctor *amo_op) override;
+ AtomicOpFunctorPtr amo_op) override;

 void fetch();
 void sendFetch(const Fault ,
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 324ae38..5f1449a 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -389,7 +389,7 @@
 InstSeqNum _reqInstSeqNum;

 /** A pointer to an atomic operation */
-AtomicOpFunctor *atomicOpFunctor;
+AtomicOpFunctorPtr atomicOpFunctor;

   public:

@@ -470,9 +470,9 @@

 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
 MasterID mid, Addr pc, ContextID cid,
-AtomicOpFunctor *atomic_op)
+AtomicOpFunctorPtr atomic_op)
 {
-setVirt(asid, vaddr, size, flags, mid, pc, atomic_op);
+setVirt(asid, vaddr, size, flags, mid, pc, std::move(atomic_op));
 setContext(cid);
 }

@@ -490,17 +490,13 @@
   accessDelta(other.accessDelta), depth(other.depth)
 {
 if (other.atomicOpFunctor)
-atomicOpFunctor = (other.atomicOpFunctor)->clone();
+atomicOpFunctor = AtomicOpFunctorPtr(
+   other.atomicOpFunctor.get()->clone());
 else
 atomicOpFunctor = nullptr;
 }

-~Request()
-{
-if (hasAtomicOpFunctor()) {
-delete atomicOpFunctor;
-}
-}
+~Request() {}

 /**
  * Set up Context numbers.
@@ -533,7 +529,7 @@
  */
 void
 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags,
-MasterID mid, Addr pc, AtomicOpFunctor *amo_op = nullptr)
+MasterID mid, Addr pc, AtomicOpFunctorPtr amo_op = nullptr)
 {
 _asid = asid;
 _vaddr = vaddr;
@@ -549,7 +545,7 @@
 depth = 0;
 accessDelta = 0;
 translateDelta = 0;
-atomicOpFunctor = amo_op;
+atomicOpFunctor = std::move(amo_op);
 }

 /**
@@ -669,20 +665,20 @@
 bool
 hasAtomicOpFunctor()
 {
-return atomicOpFunctor != NULL;
+return atomicOpFunctor.get() != NULL;
 }

 AtomicOpFunctor *
 getAtomicOpFunctor()
 {
-assert(atomicOpFunctor != NULL);
-return atomicOpFunctor;
+assert(atomicOpFunctor.get() != NULL);
+return atomicOpFunctor.get;
 }

 /** Accessor for flags. */
 Flags
 getFlags()
-{
+
 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
 return _flags;
 }

--
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[gem5-dev] Change in gem5/gem5[master]: general: Changing AtomicOpFunctor* for unique_ptr

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/20919 )



Change subject: general: Changing AtomicOpFunctor* for  
unique_ptr

..

general: Changing AtomicOpFunctor* for unique_ptr

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
---
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
3 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 1871e24..0ba5b97 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -133,7 +133,7 @@

 Fault
 initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
-   AtomicOpFunctor *amo_op) override
+   AtomicOpFunctorPtr amo_op) override
 {
 // AMO requests are pushed through the store path
 return execute.getLSQ().pushRequest(inst, false /* amo */, nullptr,
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 1e5e896..81a4d37 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1573,7 +1573,7 @@
 Fault
 LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
  unsigned int size, Addr addr, Request::Flags flags,
- uint64_t *res, AtomicOpFunctor *amo_op,
+ uint64_t *res, AtomicOpFunctorPtr amo_op,
  const std::vector& byteEnable)
 {
 assert(inst->translationFault == NoFault || inst->inLSQ);
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index a7c7cb6..c4baad8 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -708,7 +708,7 @@
  *  the LSQ */
 Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
   unsigned int size, Addr addr, Request::Flags flags,
-  uint64_t *res, AtomicOpFunctor *amo_op,
+  uint64_t *res, AtomicOpFunctorPtr amo_op,
   const std::vector& byteEnable =
   std::vector());


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: implementation of AMO policy framework and in_mem policy.

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20208

to look at the new patch set (#6).

Change subject: mem-cache: implementation of AMO policy framework and  
in_mem policy.

..

mem-cache: implementation of AMO policy framework and in_mem policy.

Implementation of a framework that allows to create different policy
configurations. For this example we implemented a memory only
configuration where if the page is located in cache is invalidated and
move the request to the next level. We implemented a naive policy that
handles the amo operation in the first memory level its is a hit.

Change-Id: I2da1485a05f090267ea3cdf3d4d08a9d2be9296c
---
M src/mem/cache/Cache.py
A src/mem/cache/amo_policy/AmoPolicy.py
A src/mem/cache/amo_policy/SConscript
A src/mem/cache/amo_policy/base.hh
A src/mem/cache/amo_policy/in_mem.cc
A src/mem/cache/amo_policy/in_mem.hh
A src/mem/cache/amo_policy/naive.cc
A src/mem/cache/amo_policy/naive.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
10 files changed, 453 insertions(+), 3 deletions(-)


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Gerrit-Change-Number: 20208
Gerrit-PatchSet: 6
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding Atomic treatment in RUBY memory infrastructure.

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/20779 )



Change subject: arch-arm: Adding Atomic treatment in RUBY memory  
infrastructure.

..

arch-arm: Adding Atomic treatment in RUBY memory infrastructure.

RUBY was unable to work with AMO (Atomic memory operations) in a general  
way.

This change modifies the hitCallback function to detect if the
operation detected as ST is an AtomicOp and handles it accordingly.

Change-Id: Ia6c1c68e22748b1123b0ae7197884725b7a93ce7
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 16 insertions(+), 4 deletions(-)



diff --git a/src/mem/ruby/system/Sequencer.cc  
b/src/mem/ruby/system/Sequencer.cc

index 9d317aa..e2fb706 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -484,11 +484,23 @@
  getOffset(request_address), pkt->getSize());
 DPRINTF(RubySequencer, "swap data %s\n", data);
 } else if (type != RubyRequestType_Store_Conditional ||  
llscSuccess) {

-// Types of stores set the actual data here, apart from
-// failed Store Conditional requests
-data.setData(pkt->getConstPtr(),
+if (pkt->isAtomicOp()){
+
+std::vector overwrite_val(pkt->getSize());
+pkt->setData(
+data.getData(getOffset(request_address),  
pkt->getSize()));

+pkt->writeData(_val[0]);
+(*(pkt->getAtomicOp()))(_val[0]);
+data.setData(_val[0],
  getOffset(request_address), pkt->getSize());
-DPRINTF(RubySequencer, "set data %s\n", data);
+DPRINTF(RubySequencer, "AMO data %s\n", data);
+}else{
+// Types of stores set the actual data here, apart from
+// failed Store Conditional requests
+data.setData(pkt->getConstPtr(),
+ getOffset(request_address), pkt->getSize());
+DPRINTF(RubySequencer, "set data %s\n", data);
+}
 }
 }


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: implementation of AMO policy framework and in_mem policy.

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20208

to look at the new patch set (#5).

Change subject: mem-cache: implementation of AMO policy framework and  
in_mem policy.

..

mem-cache: implementation of AMO policy framework and in_mem policy.

Implementation of a framework that allows to create different policy
configurations. For this example we implemented a memory only
configuration where if the page is located in cache is invalidated and
move the request to the next level. We implemented a naive policy that
handles the amo operation in the first memory level its is a hit.

Change-Id: I2da1485a05f090267ea3cdf3d4d08a9d2be9296c
---
M src/mem/cache/Cache.py
A src/mem/cache/amo_policy/AmoPolicy.py
A src/mem/cache/amo_policy/SConscript
A src/mem/cache/amo_policy/base.hh
A src/mem/cache/amo_policy/in_mem.cc
A src/mem/cache/amo_policy/in_mem.hh
A src/mem/cache/amo_policy/naive.cc
A src/mem/cache/amo_policy/naive.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
10 files changed, 451 insertions(+), 3 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: implementation of AMO policy framework and in_mem policy. ...

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20208

to look at the new patch set (#4).

Change subject: mem-cache: implementation of AMO policy framework and  
in_mem policy. Implementation of a framework that allows to create  
different policy configurations. For this example we implemented a memory  
only configuration where if the page is located in cache is invalidated and  
move the request to the next level. We implemented a naive policy that  
handles the amo operation in the first memory level its is a hit.

..

mem-cache: implementation of AMO policy framework and in_mem policy.
Implementation of a framework that allows to create different policy
configurations. For this example we implemented a memory only
configuration where if the page is located in cache is invalidated and
move the request to the next level. We implemented a naive policy that
handles the amo operation in the first memory level its is a hit.

Change-Id: I2da1485a05f090267ea3cdf3d4d08a9d2be9296c
---
M src/mem/cache/Cache.py
A src/mem/cache/amo_policy/AmoPolicy.py
A src/mem/cache/amo_policy/SConscript
A src/mem/cache/amo_policy/base.hh
A src/mem/cache/amo_policy/in_mem.cc
A src/mem/cache/amo_policy/in_mem.hh
A src/mem/cache/amo_policy/naive.cc
A src/mem/cache/amo_policy/naive.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
10 files changed, 451 insertions(+), 3 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Implementation of AMO policy framework and in_mem policy.

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20208

to look at the new patch set (#3).

Change subject: mem-cache: Implementation of AMO policy framework and  
in_mem policy.

..

mem-cache: Implementation of AMO policy framework and in_mem policy.

Implementation of a framework that allows to create different policy
configurations for handling atomic operations in the memory subsystem.
For this example we implemented a memory only
configuration where if the page is located in cache is invalidated and
move the request to the next level

Change-Id: I2da1485a05f090267ea3cdf3d4d08a9d2be9296c
---
M src/mem/cache/Cache.py
A src/mem/cache/amo_policy/AmoPolicy.py
A src/mem/cache/amo_policy/SConscript
A src/mem/cache/amo_policy/base.hh
A src/mem/cache/amo_policy/in_mem.cc
A src/mem/cache/amo_policy/in_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
8 files changed, 336 insertions(+), 3 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: implementation of AMO policy framework and in_mem policy. ...

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Ciro Santilli, Giacomo Travaglini, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/20208

to look at the new patch set (#2).

Change subject: mem-cache: implementation of AMO policy framework and  
in_mem policy. Implementation of a framework that allows to create  
different policy configurations. For this example we implemented a memory  
only configuration where if the page is located in cache is invalidated and  
move the request to the next level

..

mem-cache: implementation of AMO policy framework and in_mem policy.
Implementation of a framework that allows to create different policy
configurations. For this example we implemented a memory only
configuration where if the page is located in cache is invalidated and
move the request to the next level

Change-Id: I2da1485a05f090267ea3cdf3d4d08a9d2be9296c
---
M src/mem/cache/Cache.py
A src/mem/cache/amo_policy/AmoPolicy.py
A src/mem/cache/amo_policy/SConscript
A src/mem/cache/amo_policy/base.hh
A src/mem/cache/amo_policy/in_mem.cc
A src/mem/cache/amo_policy/in_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
8 files changed, 336 insertions(+), 3 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: implementation of in_mem amo_policy.

[Jordi Vaquero (Gerrit)]

epl.hh"
 #include "debug/CacheVerbose.hh"
+#include "mem/cache/amo_policy/base.hh"
 #include "mem/cache/compressors/base.hh"
 #include "mem/cache/mshr.hh"
 #include "mem/cache/prefetch/base.hh"
@@ -88,6 +89,7 @@
   tags(p->tags),
   compressor(p->compressor),
   prefetcher(p->prefetcher),
+  amoPolicy(p->amo_policy),
   writeAllocator(p->write_allocator),
   writebackClean(p->writeback_clean),
   tempBlockWriteback(nullptr),
@@ -1299,11 +1301,17 @@
 } else {
 lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
 }
+if (!pkt->isAtomicOp() ||
+(pkt->isAtomicOp() && amoPolicy->checkPolicy(pkt, blk))){

-satisfyRequest(pkt, blk);
-maintainClusivity(pkt->fromCache(), blk);
+satisfyRequest(pkt, blk);
+maintainClusivity(pkt->fromCache(), blk);
+return amoPolicy->satisfyPolicy(pkt);
+} else if (pkt->isAtomicOp()){
+evictBlock(blk, writebacks);
+return false ;
+}

-return true;
 }

 // Can't satisfy access normally... either no block (blk == nullptr)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 8794829..8675718 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -87,6 +87,7 @@
 class MSHR;
 class MasterPort;
 class QueueEntry;
+class BaseAmoPolicy;
 struct BaseCacheParams;

 /**
@@ -331,6 +332,9 @@
 /** Prefetcher */
 BasePrefetcher *prefetcher;

+/** Atomic Memory operation Policy **/
+BaseAmoPolicy *amoPolicy;
+
 /** To probe when a cache hit occurs */
 ProbePointArg *ppHit;


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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19812 )


Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,032 insertions(+), 20 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index a9e645e..dbe7e28 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -541,6 +541,544 @@
 namespace Aarch64
 {
 StaticInstPtr
+decodeAtomicArithOp(ExtMachInst machInst)
+{
+uint8_t opc  = bits(machInst, 14, 12);
+uint8_t o3  = bits(machInst, 15);
+uint8_t size_ar = bits(machInst, 23, 22)<<0 | bits(machInst, 31,  
30)<<2;

+IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
+IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
+IntRegIndex rnsp = makeSP(rn);
+IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+uint8_t  A_rt = bits(machInst, 4, 0)<<0 | bits(machInst, 23)<<5;
+
+switch(opc) {
+case 0x0:
+switch(size_ar){
+case 0x0:
+if (o3 == 1)
+return new SWPB(machInst, rt, rnsp, rs);
+else if (A_rt == 0x1f)
+return new STADDB(machInst, rt, rnsp, rs);
+else
+return new LDADDB(machInst, rt, rnsp, rs);
+case 0x1 :
+if (o3 == 1)
+return new SWPLB(machInst, rt, rnsp, rs);
+else if (A_rt == 0x1f)
+return new STADDLB(machInst, rt, rnsp, rs);
+else
+return new LDADDLB(machInst, rt, rnsp, rs);
+case 0x2:
+if (o3 == 1)
+return new SWPAB(machInst, rt, rnsp, rs);
+else
+return new LDADDAB(machInst, rt, rnsp, rs);
+case 0x3:
+if (o3 == 1)
+return new SWPLAB(machInst, rt, rnsp, rs);
+else
+return new LDADDLAB(machInst, rt, rnsp, rs);
+case 0x4:
+if (o3 == 1)
+return new SWPH(machInst, rt, rnsp, rs);
+else if (A_rt == 0x1f)
+return new STADDH(machInst, rt, rnsp, rs);
+else
+return new LDADDH(machInst, rt, rnsp, rs);
+case 0x5 :
+if (o3 == 1)
+return new SWPLH(machInst, rt, rnsp, rs);
+else if (A_rt == 0x1f)
+return new STADDLH(machInst, rt, rnsp, rs);
+else
+return new LDADDLH(machInst, rt, rnsp, rs);
+case 0x6:
+if (o3 == 1)
+return new SWPAH(machInst, rt, rnsp, rs);
+else
+return new LDADDAH(machInst, rt, rnsp, rs);
+case 0x7:
+if (o3 == 1)
+return new SWPLAH(machInst, rt, rnsp, rs);
+else
+return new LDADDLAH(machInst, rt, rnsp, rs);
+case 0x8:
+if (o3 == 1)
+return new SWP(machInst, rt, rnsp, rs);
+else if (A_rt == 0x1f)
+return new STADD(machInst, rt, rnsp, rs);
+else
+return new LDADD(machInst, rt, rnsp, rs);
+case 0x9 :
+if (o3 == 1)
+return new SWPL(machInst, rt, rnsp, rs);
+else if (A_rt == 0x1f)
+

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

[Jordi Vaquero (Gerrit)]

Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+
+ // ARM instructions will not have a pkt if the predicate is false
+getMem(pkt, Mem, traceData);
+
+if (fault == NoFault) {
+%(postacc_code)s;
+}
+
+if (fault == NoFault) {
+%(op_wb)s;
+}
+
+ return fault;
+}
+
+}};
+
+def template AmoOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  public:
+
+/// Constructor.
+%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+   IntRegIndex _base, IntRegIndex _result);
+
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+Fault initiateAcc(ExecContext *, Trace::InstRecord *) const  
override;

+Fault completeAcc(PacketPtr, ExecContext *,
+  Trace::InstRecord *) const override;
+
+void
+annotateFault(ArmFault *fault) override
+{
+%(fa_code)s
+}
+};
+}};
+
+
+def template AmoOpConstructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst,
+IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+  _dest, _base, _result)
+{
+%(constructor)s;
+
+}
+}};
+
+def template AmoPairOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  public:
+uint32_t d2_src ;
+uint32_t r2_src ;
+uint32_t r2_dst ;
+/// Constructor.
+%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+   IntRegIndex _base, IntRegIndex _result);
+
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+Fault initiateAcc(ExecContext *, Trace::InstRecord *) const  
override;

+Fault completeAcc(PacketPtr, ExecContext *,
+  Trace::InstRecord *) const override;
+
+void
+annotateFault(ArmFault *fault) override
+{
+%(fa_code)s
+}
+};
+}};
+
+
+def template AmoPairOpConstructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst,
+IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+  _dest,  _base, _result)
+{
+%(constructor)s;
+
+uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ;
+uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
+
+d2_src = _numSrcRegs ;
+_srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
+r2_src = _numSrcRegs ;
+_srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
+r2_dst = _numDestRegs ;
+_destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
+
+}
+}};
+
+def template AmoArithmeticOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  public:
+bool isXZR ;
+/// Constructor.
+%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+   IntRegIndex _base, IntRegIndex _result);
+
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+Fault initiateAcc(ExecContext *, Trace::InstRecord *) const  
override;

+Fault completeAcc(PacketPtr, ExecContext *,
+  Trace::InstRecord *) const override;
+
+void
+annotateFault(ArmFault *fault) override
+{
+%(fa_code)s
+}
+};
+}};
+
+def template AmoArithmeticOpConstructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst,
+IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+  _dest,  _base, _result)
+{
+%(constructor)s;
+isXZR = false;
+uint32_t r2 = RegId(IntRegClass, dest).index() ;
+if (r2 == 31){
+flags[IsReadBarrier] = false;
+isXZR = true;
+}
+}
+}};

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Gerrit-Assignee: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#13).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,032 insertions(+), 20 deletions(-)


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Gerrit-PatchSet: 13
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, kokoro, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19811

to look at the new patch set (#8).

Change subject: arch-arm: Adding CAS/CASP AMO instr including new  
TypedAtomic func

..

arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/isa/formats/aarch64.isa
A src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/templates/mem64.isa
5 files changed, 695 insertions(+), 6 deletions(-)


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Gerrit-Change-Number: 19811
Gerrit-PatchSet: 8
Gerrit-Owner: Jordi Vaquero 
Gerrit-Assignee: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: mend

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19930 )



Change subject: mend
..

mend

Change-Id: I5a3a8cc7bf675b14e12fcb3ff6ed5ecb60dd552e
---
M src/arch/arm/isa/insts/amo64.isa
1 file changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/isa/insts/amo64.isa  
b/src/arch/arm/isa/insts/amo64.isa

index f42edfa..70604e9 100644
--- a/src/arch/arm/isa/insts/amo64.isa
+++ b/src/arch/arm/isa/insts/amo64.isa
@@ -41,14 +41,14 @@

 import math

-OP_DICT = { "CAS" : 'if (a == *b) *b = *c;',
-"SWP" : '*c = *b; *b = a;',
-"ADD" : '*c = *b; *b += a;',
-"EOR" : '*c = *b; *b ^= a;',
-"CLR" : '*c = *b; *b &= a;',
-"SET" : '*c = *b; *b |= a;',
-"MAX" : '*c = *b; *b = std::max(*b, a);',
-"MIN" : '*c = *b; *b = std::min(*b, a);', }
+OP_DICT = { "CAS" : 'if (a == *b){*b = c;}',
+"SWP" : '*b = c;',
+"ADD" : '*b += c;',
+"EOR" : '*b ^= c;',
+"CLR" : '*b &= ~c;',
+"SET" : '*b |= c;',
+"MAX" : '*b = std::max(*b, c);',
+"MIN" : '*b = std::min(*b, c);', }

 MASKS = { 1: 0xFF,
   2: 0x,

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[gem5-dev] Change in gem5/gem5[master]: mend

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19929 )



Change subject: mend
..

mend

Change-Id: Ic230ba61c527a00f3a2c92c2ede9d3e9cb379179
---
M src/arch/arm/isa/insts/amo64.isa
1 file changed, 9 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/isa/insts/amo64.isa  
b/src/arch/arm/isa/insts/amo64.isa

index f42edfa..8bccebf 100644
--- a/src/arch/arm/isa/insts/amo64.isa
+++ b/src/arch/arm/isa/insts/amo64.isa
@@ -41,14 +41,15 @@

 import math

-OP_DICT = { "CAS" : 'if (a == *b) *b = *c;',
-"SWP" : '*c = *b; *b = a;',
-"ADD" : '*c = *b; *b += a;',
-"EOR" : '*c = *b; *b ^= a;',
-"CLR" : '*c = *b; *b &= a;',
-"SET" : '*c = *b; *b |= a;',
-"MAX" : '*c = *b; *b = std::max(*b, a);',
-"MIN" : '*c = *b; *b = std::min(*b, a);', }
+OP_DICT = { "CAS" : 'if (a == *b){*b = c;}',
+"SWP" : '*b = c;',
+"ADD" : '*b += c;',
+"EOR" : '*b ^= c;',
+"CLR" : '*b &= ~c;',
+"SET" : '*b |= c;',
+"MAX" : '*b = std::max(*b, c);',
+"MIN" : '*b = std::min(*b, c);', }
+

 MASKS = { 1: 0xFF,
   2: 0x,

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#9).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,032 insertions(+), 21 deletions(-)


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Gerrit-Change-Number: 19812
Gerrit-PatchSet: 9
Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19811

to look at the new patch set (#7).

Change subject: arch-arm: Adding CAS/CASP AMO instr including new  
TypedAtomic func

..

arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/isa/formats/aarch64.isa
A src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/templates/mem64.isa
5 files changed, 695 insertions(+), 6 deletions(-)


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Gerrit-PatchSet: 7
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Gerrit-Assignee: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#7).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,040 insertions(+), 28 deletions(-)


--
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Gerrit-Change-Number: 19812
Gerrit-PatchSet: 7
Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[master]: mend

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19928 )



Change subject: mend
..

mend

Change-Id: Id112b56fd532e6a0a5a058e5fabb209f88c3c9dd
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/isa/formats/aarch64.isa
2 files changed, 7 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 5641919..4fbbe77 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -316,16 +316,16 @@
 {}
 AtomicOpFunctor* clone() override
 {
-  return new AtomicGenericPair3Op(*this);
+return new AtomicGenericPair3Op(*this);
 }
 void execute(T* b) override
 {
-  op(b, a, c);
+op(b, a, c);
 }
-private:
-  std::array a;
-  std::array c;
-  std::function&, std::array)> op;
+  private:
+std::array a;
+std::array c;
+std::function&, std::array)> op;
 };

 }
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index a6dc36f..a9e645e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -925,7 +925,7 @@
 M5_UNREACHABLE;
 }
 } else {
-return decodeAtomicArithOp(machInst);
+return new Unknown64(machInst);
 }
 }
   case 0x2:

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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: fix atomic instructions non-speculative

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19815 )


Change subject: cpu-o3: fix atomic instructions non-speculative
..

cpu-o3: fix atomic instructions non-speculative

Fix problem with O3 and AMO instructions. At initial stages amo
instruction is considered a type of non-speculative store. After
the instruction has been commited and during the squash step,
acquire_release version of the AMO operation is considered speculative,
that differents results in an assert fault. This fix ensures that AMO
instructions are always considered non-speculative, during early stages
and during squas/removal of the instruction.

Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/inst_queue_impl.hh
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index c3e3fdf..f3362f2 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1262,7 +1262,6 @@

 bool is_acq_rel = squashed_inst->isMemBarrier() &&
  (squashed_inst->isLoad() ||
-  squashed_inst->isAtomic() ||
   (squashed_inst->isStore() &&
  !squashed_inst->isStoreConditional()));


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Gerrit-Change-Number: 19815
Gerrit-PatchSet: 11
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tuan Ta 
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: added _amo_op parameter in o3 LSQ

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19814 )


Change subject: cpu-o3: added _amo_op parameter in o3 LSQ
..

cpu-o3: added _amo_op parameter in o3 LSQ

Fix bug with AMO (or RMW) instructions where the amo_op variable
is not being propagated to the LSQ request.

Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19814
Maintainer: Andreas Sandberg 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Reviewed-by: Anthony Gutierrez 
---
M src/cpu/o3/lsq.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 4701a8c..29c76f7 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -366,7 +366,7 @@
 isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
 auto request = std::make_shared(_inst->getASID(),
 addr, size, _flags, _inst->masterId(),
-_inst->instAddr(), _inst->contextId());
+_inst->instAddr(), _inst->contextId(), _amo_op);
 if (!byteEnable.empty()) {
 request->setByteEnable(byteEnable);
 }

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Gerrit-Change-Number: 19814
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Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19810 )


Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic  
instructions

..

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19810
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 8e21bb3..34eb43f 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -260,6 +260,52 @@
 std::string generateDisassembly(
 Addr pc, const SymbolTable *symtab) const override;
 };
+
+/**
+ * A generic atomic op class
+ */
+
+template
+class AtomicGeneric2Op : public TypedAtomicOpFunctor
+{
+  public:
+AtomicGeneric2Op(T _a, std::function _op)
+: a(_a), op(_op)
+{}
+AtomicOpFunctor* clone() override
+{
+return new AtomicGeneric2Op(*this);
+}
+void execute(T *b) override
+{
+op(b, a);
+}
+  private:
+T a;
+std::function op;
+ };
+
+template
+class AtomicGeneric3Op : public TypedAtomicOpFunctor
+{
+  public:
+AtomicGeneric3Op(T _a, T _c, std::function _op)
+: a(_a), c(_c), op(_op)
+{}
+AtomicOpFunctor* clone() override
+{
+return new AtomicGeneric3Op(*this);
+}
+void execute(T *b) override
+{
+op(b, a, c);
+}
+  private:
+T a;
+T c;
+std::function op;
+};
+
 }

 #endif //__ARCH_ARM_INSTS_MEM_HH__

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation

[Jordi Vaquero (Gerrit)]

it-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Gerrit-Change-Number: 19809
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, kokoro, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19810

to look at the new patch set (#4).

Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic  
instructions

..

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Gerrit-Change-Number: 19810
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19811

to look at the new patch set (#6).

Change subject: arch-arm: Adding CAS/CASP AMO instr including new  
TypedAtomic func

..

arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/isa/formats/aarch64.isa
A src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/templates/mem64.isa
5 files changed, 696 insertions(+), 7 deletions(-)


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Gerrit-Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
Gerrit-Change-Number: 19811
Gerrit-PatchSet: 6
Gerrit-Owner: Jordi Vaquero 
Gerrit-Assignee: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, kokoro, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19810

to look at the new patch set (#3).

Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic  
instructions

..

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)


--
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Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Gerrit-Change-Number: 19810
Gerrit-PatchSet: 3
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#5).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,039 insertions(+), 27 deletions(-)


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Gerrit-Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Gerrit-Change-Number: 19812
Gerrit-PatchSet: 5
Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: added _amo_op parameter in o3 LSQ

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Anthony Gutierrez,  
Jason Lowe-Power,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19814

to look at the new patch set (#7).

Change subject: cpu-o3: added _amo_op parameter in o3 LSQ
..

cpu-o3: added _amo_op parameter in o3 LSQ

Fix bug with AMO (or RMW) instructions where the amo_op variable
is not being propagated to the LSQ request.

Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
---
M src/cpu/o3/lsq.hh
1 file changed, 1 insertion(+), 1 deletion(-)


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Gerrit-Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Gerrit-Change-Number: 19814
Gerrit-PatchSet: 7
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, kokoro,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19809

to look at the new patch set (#3).

Change subject: arch-arm: adding register control flags enabling LSE  
implementation

..

arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.

Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Gerrit-Change-Number: 19809
Gerrit-PatchSet: 3
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/19849 )


Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic  
instructions

..

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: I8b6d9d3738bec5cfaf7449fd787551be2db8cd81
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)


--
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#4).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,039 insertions(+), 27 deletions(-)


--
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Gerrit-Change-Number: 19812
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19811

to look at the new patch set (#4).

Change subject: arch-arm: Adding CAS/CASP AMO instr including new  
TypedAtomic func

..

arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/isa/formats/aarch64.isa
A src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/templates/mem64.isa
5 files changed, 695 insertions(+), 7 deletions(-)


--
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Gerrit-Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
Gerrit-Change-Number: 19811
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Assignee: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/19848 )


Change subject: arch-arm: adding register control flags enabling LSE  
implementation

..

arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.

Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)


--
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Gerrit-Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19848 )



Change subject: arch-arm: adding register control flags enabling LSE  
implementation

..

arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in control registers and add have_lse variable into arm system.

Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a9..a92ae4f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,8 @@
 "True if SVE is implemented (ARMv8)")
 sve_vl = Param.SveVectorLength(1,
 "SVE vector length in quadwords (128-bit)")
+have_lse = Param.Bool(True,
+"True if LSE is implemented (ARMv8.1)")
 have_pan = Param.Bool(True,
 "True if Priviledge Access Never is implemented (ARMv8.1)")

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 23738c6..299698d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -93,6 +93,7 @@
 haveSVE = system->haveSVE();
 havePAN = system->havePAN();
 sveVL = system->sveVL();
+haveLSE = system->haveLSE();
 } else {
 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
 haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@
 haveSVE = true;
 havePAN = false;
 sveVL = p->sve_vl_se;
+haveLSE = true;
 }

 // Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@
 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
 haveCrypto ? 0x1112 : 0x0);
+// LSE
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+haveLSE ? 0x2 : 0x0);
 // PAN
 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 63051cd..5e337c2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -95,6 +95,7 @@
 bool haveGICv3CPUInterface;
 uint8_t physAddrRange;
 bool haveSVE;
+bool haveLSE;
 bool havePAN;

 /** SVE vector length in quadwords */
@@ -687,6 +688,7 @@
 SERIALIZE_SCALAR(physAddrRange);
 SERIALIZE_SCALAR(haveSVE);
 SERIALIZE_SCALAR(sveVL);
+SERIALIZE_SCALAR(haveLSE);
 SERIALIZE_SCALAR(havePAN);
 }
 void unserialize(CheckpointIn )
@@ -704,6 +706,7 @@
 UNSERIALIZE_SCALAR(physAddrRange);
 UNSERIALIZE_SCALAR(haveSVE);
 UNSERIALIZE_SCALAR(sveVL);
+UNSERIALIZE_SCALAR(haveLSE);
 UNSERIALIZE_SCALAR(havePAN);
 }

diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 874e3b0..4ea0d1a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -73,6 +73,7 @@
   _haveLargeAsid64(p->have_large_asid_64),
   _haveSVE(p->have_sve),
   _sveVL(p->sve_vl),
+  _haveLSE(p->have_lse),
   _havePAN(p->have_pan),
   _m5opRange(p->m5ops_base ?
  RangeSize(p->m5ops_base, 0x1) :
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f477..46c58e8 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@
 /** SVE vector length at reset, in quadwords */
 const unsigned _sveVL;

+/**
+ * True if LSE is implemented (ARMv8.1)
+ */
+const bool _haveLSE;
+
 /** True if Priviledge Access Never is implemented */
 const unsigned _havePAN;

@@ -244,6 +249,9 @@
 /** Returns the SVE vector length at reset, in quadwords */
 unsigned sveVL() const { return _sveVL; }

+/** Returns true if LSE is implemented (ARMv8.1) */
+bool haveLSE() const { return _haveLSE; }
+
 /** Returns true if Priviledge Access Never is implemented */
 bool havePAN() const { return _havePAN; }


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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: fix atomic instructions non-speculative

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19850 )



Change subject: cpu-o3: fix atomic instructions non-speculative
..

cpu-o3: fix atomic instructions non-speculative

Fix problem with O3 and AMO instructions. At initial stages amo
instruction is considered a type of non-speculative store. After
the instruction has been commited and during the squash step,
acquire_release version of the AMO operation is considered speculative,
that differents results in an assert fault. This fix ensures that AMO
instructions are always considered non-speculative, during early stages
and during squas/removal of the instruction.

Change-Id: Iccd981bc6d271b8259399ae668b3c1851562fb84
---
M src/cpu/o3/inst_queue_impl.hh
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index c3e3fdf..f3362f2 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1262,7 +1262,6 @@

 bool is_acq_rel = squashed_inst->isMemBarrier() &&
  (squashed_inst->isLoad() ||
-  squashed_inst->isAtomic() ||
   (squashed_inst->isStore() &&
  !squashed_inst->isStoreConditional()));


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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19849 )



Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic  
instructions

..

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: I8b6d9d3738bec5cfaf7449fd787551be2db8cd81
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 8e21bb3..57328a7 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -260,6 +260,52 @@
 std::string generateDisassembly(
 Addr pc, const SymbolTable *symtab) const override;
 };
+
+/**
+ * A generic atomic op class
+ */
+
+template
+class AtomicGenericOp : public TypedAtomicOpFunctor
+{
+  public:
+AtomicGenericOp(T _a, std::function _op)
+: a(_a), op(_op)
+{}
+AtomicOpFunctor* clone()
+{
+  return new AtomicGenericOp(*this);
+}
+void execute(T *b)
+{
+  op(b, a);
+}
+  private:
+T a;
+std::function op;
+ };
+
+template
+class AtomicGenericOp3Param : public TypedAtomicOpFunctor
+{
+  public:
+AtomicGenericOp3Param(T _a, T _c, std::function _op)
+  : a(_a), c(_c), op(_op)
+{}
+AtomicOpFunctor* clone()
+{
+  return new AtomicGenericOp3Param(*this);
+}
+void execute(T *b)
+{
+  op(b, a, c);
+}
+  private:
+T a;
+T c;
+std::function op;
+};
+
 }

 #endif //__ARCH_ARM_INSTS_MEM_HH__

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I8b6d9d3738bec5cfaf7449fd787551be2db8cd81
Gerrit-Change-Number: 19849
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Gerrit-Owner: Jordi Vaquero 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Andreas Sandberg, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#3).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,039 insertions(+), 27 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Gerrit-Change-Number: 19812
Gerrit-PatchSet: 3
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/19809 )


Change subject: arch-arm: adding register control flags enabling LSE  
implementation

..

arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in control registers and add have_lse variable into arm system.

Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Gerrit-Change-Number: 19809
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-CC: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

[Jordi Vaquero (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19810

to look at the new patch set (#2).

Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic  
instructions

..

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)


--
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Gerrit-Branch: master
Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Gerrit-Change-Number: 19810
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

[Jordi Vaquero (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19811

to look at the new patch set (#2).

Change subject: arch-arm: Adding CAS/CASP AMO instr including new  
TypedAtomic func

..

arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/isa/formats/aarch64.isa
A src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/templates/mem64.isa
5 files changed, 695 insertions(+), 7 deletions(-)


--
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Gerrit-Branch: master
Gerrit-Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
Gerrit-Change-Number: 19811
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[Jordi Vaquero (Gerrit)]

Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19812

to look at the new patch set (#2).

Change subject: arch-arm: Added LD/ST atomic instruction family and SWP  
instrs

..

arch-arm: Added LD/ST atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/templates/mem64.isa
3 files changed, 1,039 insertions(+), 27 deletions(-)


--
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Gerrit-Branch: master
Gerrit-Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Gerrit-Change-Number: 19812
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: added _amo_op parameter in o3 LSQ

[Jordi Vaquero (Gerrit)]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19814 )



Change subject: cpu-o3: added _amo_op parameter in o3 LSQ
..

cpu-o3: added _amo_op parameter in o3 LSQ

Fix bug with AMO (or RMW) instructions where the amo_op variable
is not being propagated to the LSQ request.

Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
---
M src/cpu/o3/lsq.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 4701a8c..29c76f7 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -366,7 +366,7 @@
 isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
 auto request = std::make_shared(_inst->getASID(),
 addr, size, _flags, _inst->masterId(),
-_inst->instAddr(), _inst->contextId());
+_inst->instAddr(), _inst->contextId(), _amo_op);
 if (!byteEnable.empty()) {
 request->setByteEnable(byteEnable);
 }

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Gerrit-Branch: master
Gerrit-Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Gerrit-Change-Number: 19814
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero 
Gerrit-MessageType: newchange
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