[gem5-dev] [XS] Change in gem5/gem5[develop]: cpu-o3: add decode stall in fetch stage

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71998?usp=email ) Change subject: cpu-o3: add decode stall in fetch stage .. cpu-o3: add decode stall in fetch stage

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Declear vecElemClass for RISC-V vector extensions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71999?usp=email ) Change subject: arch-riscv: Declear vecElemClass for RISC-V vector extensions .. arch-riscv:

[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Pass the DISPLAY environment variable through to SCons.

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/56952?usp=email ) Change subject: scons: Pass the DISPLAY environment variable through to SCons. .. scons: Pass the DISPLAY

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix unexpected behavior of float operations in Mac OS

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71578?usp=email ) Change subject: arch-riscv: Fix unexpected behavior of float operations in Mac OS .. arch-riscv: Fix

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix unexpected behavior of float operations in Mac OS

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71578?usp=email ) Change subject: arch-riscv: Fix unexpected behavior of float operations in Mac OS .. arch-riscv:

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor fmax and fmin instructions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71479?usp=email ) Change subject: arch-riscv: Refactor fmax and fmin instructions .. arch-riscv: Refactor fmax and fmin

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor fmax and fmin instructions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71479?usp=email ) Change subject: arch-riscv: Refactor fmax and fmin instructions .. arch-riscv: Refactor fmax and fmin

[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add extra parent dir to CPPPATH if --no-duplicate-sources

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71478?usp=email ) Change subject: scons: Add extra parent dir to CPPPATH if --no-duplicate-sources .. scons: Add

[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Fix grpc protobuf actions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71318?usp=email ) Change subject: scons: Fix grpc protobuf actions .. scons: Fix grpc protobuf actions The change will fix the

[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Fix grpc protobuf actions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71318?usp=email ) Change subject: scons: Fix grpc protobuf actions .. scons: Fix grpc protobuf actions The change will

[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Add U74VecFU to U74CPU

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71238?usp=email ) Change subject: stdlib: Add U74VecFU to U74CPU .. stdlib: Add U74VecFU to U74CPU This change is to elimilate the

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67295?usp=email ) Change subject: arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext .. arch-riscv,cpu-minor: Add

[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Add U74VecFU to elimilate warning from minor cpu

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71238?usp=email ) Change subject: stdlib: Add U74VecFU to elimilate warning from minor cpu .. stdlib: Add U74VecFU to

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71198?usp=email ) Change subject: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp .. arch-riscv: Check FPU

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71198?usp=email ) Change subject: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp .. arch-riscv:

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add BS format isa

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70598?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: Add BS format isa

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Simplify the rev8 and brev8 instructions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70599?usp=email ) Change subject: arch-riscv: Simplify the rev8 and brev8 instructions .. arch-riscv: Simplify the rev8 and brev8

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70600?usp=email ) Change subject: arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8 .. arch-riscv: Merge rv32 and rv64

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70597?usp=email ) Change subject: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions .. arch-riscv: Simplify amd

[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Update riscv/fs_linux.py script

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70177?usp=email ) Change subject: configs: Update riscv/fs_linux.py script .. configs: Update riscv/fs_linux.py script This change

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: merge rv32 and rv64 version of xperm4 and xperm8

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70600?usp=email ) Change subject: arch-riscv: merge rv32 and rv64 version of xperm4 and xperm8 .. arch-riscv: merge rv32

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70597?usp=email ) Change subject: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions .. arch-riscv:

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: simply the rev8 and brev8 instruction

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70599?usp=email ) Change subject: arch-riscv: simply the rev8 and brev8 instruction .. arch-riscv: simply the rev8 and

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add BS format isa

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70598?usp=email ) Change subject: arch-riscv: Add BS format isa .. arch-riscv: Add BS format isa This format is helper

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add missing zbkb instructions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email ) Change subject: arch-riscv: Add missing zbkb instructions .. arch-riscv: Add missing zbkb instructions Add the

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Treat RVC HINT as nops rather than trap

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70357?usp=email ) Change subject: arch-riscv: Treat RVC HINT as nops rather than trap .. arch-riscv: Treat RVC HINT as nops rather

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fc...

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70377?usp=email ) Change subject: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fcvt_d_lu .. arch-riscv:

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70358?usp=email ) Change subject: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2 .. arch-riscv: Refactor

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add missing zbkb instructions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email ) Change subject: arch-riscv: Add missing zbkb instructions .. arch-riscv: Add missing zbkb instructions

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add RV32 only Zk instruction extensions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69937?usp=email ) Change subject: arch-riscv: Add RV32 only Zk instruction extensions .. arch-riscv: Add RV32 only Zk instruction

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: seperate RV32 and RV64 Zk extensions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66191?usp=email ) Change subject: arch-riscv: seperate RV32 and RV64 Zk extensions .. arch-riscv: seperate RV32 and RV64 Zk

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Remove Riscv32CPU instance

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66871?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: Remove Riscv32CPU instance

[gem5-dev] [L] Change in gem5/gem5[develop]: tests: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70097?usp=email ) Change subject: tests: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests" .. tests: Revert

[gem5-dev] [L] Change in gem5/gem5[develop]: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"

Attention is currently required from: Bobby Bruce, Yu-hsin Wang. Hello kokoro, Bobby Bruce, Yu-hsin Wang, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70097?usp=email to review the following change. Change subject: Revert

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: refactor bitfields of insts

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68417?usp=email ) Change subject: arch-riscv: refactor bitfields of insts .. arch-riscv: refactor bitfields of insts + move

[gem5-dev] [S] Change in gem5/gem5[develop]: arch: Add vector function unit and OpClass enums

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67293?usp=email ) Change subject: arch: Add vector function unit and OpClass enums .. arch: Add vector function unit and OpClass

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Insert symbol table of bootloader into debug symbol table...

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69697?usp=email ) Change subject: arch-riscv: Insert symbol table of bootloader into debug symbol table in bare metal workload ..

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Insert symbol table of into debug symbol table

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69697?usp=email ) Change subject: arch-riscv: Insert symbol table of into debug symbol table .. arch-riscv: Insert

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor the shouldCheckPMP function

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69497?usp=email ) Change subject: arch-riscv: Refactor the shouldCheckPMP function .. arch-riscv: Refactor the shouldCheckPMP

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the address check of pmp

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69577?usp=email ) Change subject: arch-riscv: Fix the address check of pmp .. arch-riscv: Fix the address check of pmp Fix the

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the address check of pmp

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69577?usp=email ) Change subject: arch-riscv: Fix the address check of pmp .. arch-riscv: Fix the address check of pmp

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the behavior of pmp

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69497?usp=email ) Change subject: arch-riscv: Fix the behavior of pmp .. arch-riscv: Fix the behavior of pmp 1.

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add pmp index checking

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69117?usp=email ) Change subject: arch-riscv: Add pmp index checking .. arch-riscv: Add pmp index checking Check the index is

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add pmp index checking

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69117?usp=email ) Change subject: arch-riscv: Add pmp index checking .. arch-riscv: Add pmp index checking Check the

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Remove CLINT parameter of HiFiveBase

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69017?usp=email ) Change subject: arch-riscv,dev: Remove CLINT parameter of HiFiveBase .. arch-riscv,dev: Remove CLINT

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add new misa bit union

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68917?usp=email ) Change subject: arch-riscv: Add new misa bit union .. arch-riscv: Add new misa bit union The new misa bit union

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add new misa bit union

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68917?usp=email ) Change subject: arch-riscv: Add new misa bit union .. arch-riscv: Add new misa bit union The new misa

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Support PMP lock feature

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68057?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: Support PMP lock feature

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add HiFive Base Platform

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68199?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv,dev: Add HiFive Base

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv,dev: Add PLIC abstract class

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Fix behavior issues of PLIC

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68198?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv,dev: Fix behavior issues of

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add HiFive Base Platform

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68199?usp=email ) Change subject: arch-riscv,dev: Add HiFive Base Platform .. arch-riscv,dev: Add HiFive Base Platform

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Fix reserved size between enable memory map and thres...

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68198?usp=email ) Change subject: arch-riscv,dev: Fix reserved size between enable memory map and threshold memory map

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email ) Change subject: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC implementation ..

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Support PMP lock feature

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68057?usp=email ) Change subject: arch-riscv: Support PMP lock feature .. arch-riscv: Support PMP lock feature The lock

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix incorrect trap value of instruction fault

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67677?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: Fix incorrect trap value

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the behavior of write to status CSR

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67897?usp=email ) Change subject: arch-riscv: Fix the behavior of write to status CSR .. arch-riscv: Fix the behavior of write to

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the behavior of write to status CSR

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67897?usp=email ) Change subject: arch-riscv: Fix the behavior of write to status CSR .. arch-riscv: Fix the behavior of

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix incorrect trap value of instruction fault

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67677?usp=email ) Change subject: arch-riscv: Fix incorrect trap value of instruction fault .. arch-riscv: Fix incorrect

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,sim-se: Support RV32 register ABI call

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65532?usp=email ) ( 20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv,sim-se: Support RV32

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct interrupt order

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67211?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: Correct interrupt order

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email ) Change subject: arch-riscv: Check RISCV process run in matched CPU .. arch-riscv: Check RISCV process run in

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email ) Change subject: arch-riscv: Check RISCV process run in matched CPU .. arch-riscv: Check RISCV process

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: add RV32 ADFIMU_Zfh instruction tests

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65533?usp=email ) ( 35 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: add RV32 ADFIMU_Zfh

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct the IllegalInstFault messege of instruction c.add...

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email ) Change subject: arch-riscv: Correct the IllegalInstFault messege of instruction c.addi4spn .. arch-riscv:

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct the IllegalInstFault messege of instruction c.add...

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email ) Change subject: arch-riscv: Correct the IllegalInstFault messege of instruction c.addi4spn ..

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor compressed instructions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66732?usp=email ) Change subject: arch-riscv: Refactor compressed instructions .. arch-riscv: Refactor compressed instructions 1.

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor template JumpConstructor

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66811?usp=email ) Change subject: arch-riscv: Refactor template JumpConstructor .. arch-riscv: Refactor template JumpConstructor

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor template JumpConstructor

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66811?usp=email ) Change subject: arch-riscv: Refactor template JumpConstructor .. arch-riscv: Refactor template

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66211?usp=email ) Change subject: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64 .. arch-riscv: Fork Zba,

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, tests: Refactor SimpleProcessor and SimpleCore

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66592?usp=email ) Change subject: stdlib, tests: Refactor SimpleProcessor and SimpleCore .. stdlib, tests: Refactor

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Add basic features toward rv32 support

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63091?usp=email ) Change subject: arch-riscv: Add basic features toward rv32 support .. arch-riscv: Add basic features toward rv32

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66211?usp=email ) Change subject: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64 .. arch-riscv:

[gem5-dev] [L] Change in gem5/gem5[develop]: Add another instructions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66191?usp=email ) Change subject: Add another instructions .. Add another instructions Change-Id:

[gem5-dev] [L] Change in gem5/gem5[develop]: Implement rv32 zicsr extension

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65733?usp=email ) Change subject: Implement rv32 zicsr extension .. Implement rv32 zicsr extension 1. Add misc register

[gem5-dev] [L] Change in gem5/gem5[develop]: RV32 tests

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65533?usp=email ) Change subject: RV32 tests .. RV32 tests Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9 --- M

[gem5-dev] [M] Change in gem5/gem5[develop]: Add rv32 Syscall ABI

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65532?usp=email ) Change subject: Add rv32 Syscall ABI .. Add rv32 Syscall ABI 1. Change default value of arch to

[gem5-dev] [S] Change in gem5/gem5[develop]: sim-se: change sizeof output pid buffer to 4

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65531?usp=email ) Change subject: sim-se: change sizeof output pid buffer to 4 .. sim-se: change sizeof output pid