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changeset 54ed46881217 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=54ed46881217
description:
CPU: Prepare CPU models for the new in-order CPU model.
Some new functions and forward declarations are necessary to make
things work
diffstat:
3 files changed, 17
changeset 303e409d88d9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=303e409d88d9
description:
ExeTrace: Allow subclasses of the tracer to define their own prefix to
dump
diffstat:
2 files changed, 8 insertions(+), 1 deletion(-)
src/cpu/exetrace.cc |8 +++-
changeset c3e4371d37a8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c3e4371d37a8
description:
syscall: Expose ioctl for MIPS
diffstat:
2 files changed, 10 insertions(+), 10 deletions(-)
src/arch/mips/linux/linux.hh | 18 +-
changeset 09ab46bfa914 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=09ab46bfa914
description:
InOrder: Import new inorder CPU model from MIPS.
This model currently only works in MIPS_SE mode, so it will take some
effort
to clean it up and make it
changeset acbe11bbfe68 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=acbe11bbfe68
description:
Configs: Add support for the InOrder CPU model
diffstat:
6 files changed, 174 insertions(+), 151 deletions(-)
configs/common/Options.py |1
changeset 09ab46bfa914 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=09ab46bfa914
description:
InOrder: Import new inorder CPU model from MIPS.
This model currently only works in MIPS_SE mode, so it will take some
effort
to clean it up and make it
Thanks for the helping in pushing this out Nate.
There is a short and long version of the thread support in MIPS and why it
varies.
I'll give the short version here: MIPS was implemented ot use the MT ISA
extension
which requires the ability to read/write registers from other threads. I
designed
Thanks Korey! Nice to see all this get in.
Just one little nit to pick: this function definition here should be in
static_inst.cc and not static_inst.hh. It certainly doesn't need to be
inlined for performance reasons, and since it's virtual it won't get inlined
anyway, so there's no point in
Just one little nit to pick: this function definition here should be in
static_inst.cc and not static_inst.hh. It certainly doesn't need to be
inlined for performance reasons, and since it's virtual it won't get inlined
anyway, so there's no point in cluttering the header file with it.
That
I'll give the short version here: MIPS was implemented ot use the MT ISA
extension
which requires the ability to read/write registers from other threads. I
designed the register file
to be on size fits all. It can be instantiated multiple times as a
per-thread register file (Simple-CPU) OR
changeset 5645632d594c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5645632d594c
description:
style
diffstat:
2 files changed, 63 insertions(+), 47 deletions(-)
src/cpu/static_inst.cc | 43 --
src/cpu/static_inst.hh | 67
Hi everybody. I can't contribute to M5's x86 support right now
because I'm still blocked on supporting TLB misses correctly. Until
that's dealt with, all of my patches will stay in my queue behind it and
none of them will make it into the head. If Nate, Steve, etc. could
please help figure out
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