[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick

2009-09-14 Thread Cron Daemon
scons: *** [build/ALPHA_SE/python/swig/random_wrap.fo] Error 1 scons: *** [build/ALPHA_SE/python/swig/event_wrap.fo] Error 1 scons: *** [build/ALPHA_SE/python/swig/trace_wrap.fo] Error 1 scons: *** [build/ALPHA_SE/python/swig/stats_wrap.fo] Error 1 scons: ***

[m5-dev] [PATCH 01 of 18] ruby: added random seed option to config scripts

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1250630649 18000 # Node ID 79d81f0b6217455b4f7586f53693f139285771a6 # Parent 64bf776c5e704cd92fd6a1e286014bc39e96c90f ruby: added random seed option to config scripts diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb

[m5-dev] [PATCH 04 of 18] [mq]: first_patch

2009-09-14 Thread Derek Hower
# HG changeset patch # User pdud...@gmail.com # Date 1250887966 18000 # Node ID 104115ebc206686948736edaf517718bbdfd3cd5 # Parent f9e065561d5cd8b98a88290a418381e667026a10 [mq]: first_patch diff --git a/src/mem/ruby/libruby.cc b/src/mem/ruby/libruby.cc --- a/src/mem/ruby/libruby.cc +++

[m5-dev] [PATCH 06 of 18] ruby: fixed config assertion failure

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1251815748 18000 # Node ID 2431d803c3550be385ee82293cd45d3a61851ca3 # Parent 0cfcb218a18a4cbdefe3bdd1e0c16efddeb79714 ruby: fixed config assertion failure diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb ---

[m5-dev] [PATCH 05 of 18] merge

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1251214641 18000 # Node ID 0cfcb218a18a4cbdefe3bdd1e0c16efddeb79714 # Parent 19e532a296e0975cf7918b4d7e9ef80f1d392cac # Parent 104115ebc206686948736edaf517718bbdfd3cd5 merge diff --git a/src/mem/ruby/libruby.cc

[m5-dev] [PATCH 08 of 18] ruby: made Locked read/write atomic requests within ruby

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252517950 18000 # Node ID 4169f24434efe4648be94d96c058d331b68c9b33 # Parent 74af2e1a7480a3098bc899a31796b45d02fb637b ruby: made Locked read/write atomic requests within ruby diff --git a/src/mem/ruby/system/Sequencer.cc

[m5-dev] [PATCH 09 of 18] ruby: made L2 request/response latency based on cache latency by default

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252607536 18000 # Node ID 0173532b03f076dd9b089a6e4c6b2839cdff3f1b # Parent 4169f24434efe4648be94d96c058d331b68c9b33 ruby: made L2 request/response latency based on cache latency by default diff --git

[m5-dev] [PATCH 15 of 18] ruby: cleaned up unified MESI/MOESI configuration

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252704179 18000 # Node ID 1a01f799bd7636f41cb864f99dd8d9184034cf72 # Parent ec28f4e6df9e636e78abbeec745afaee806375a3 ruby: cleaned up unified MESI/MOESI configuration diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb

[m5-dev] [PATCH 10 of 18] protocol: made MI_example work with unordered networks

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252635489 18000 # Node ID f1ee92cfcc10a8192f6955d6798ed50044c36609 # Parent 0173532b03f076dd9b089a6e4c6b2839cdff3f1b protocol: made MI_example work with unordered networks diff --git a/src/mem/protocol/MI_example-cache.sm

[m5-dev] [PATCH 11 of 18] ruby: made randomization true by default

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252635574 18000 # Node ID 576153b639d0384524fe1404f6fd12205ff1c362 # Parent f1ee92cfcc10a8192f6955d6798ed50044c36609 ruby: made randomization true by default diff --git a/src/mem/ruby/config/defaults.rb

[m5-dev] [PATCH 12 of 18] ruby: removed SMT-related Sequencer assert

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252635594 18000 # Node ID 38da844de1148e391dc67779e3dcb4fed8fb5400 # Parent 576153b639d0384524fe1404f6fd12205ff1c362 ruby: removed SMT-related Sequencer assert diff --git a/src/mem/ruby/system/Sequencer.cc

[m5-dev] [PATCH 13 of 18] Automated merge with ssh://h...@m5sim.org/m5

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252638133 18000 # Node ID 1bf54187d685859f3e39942c03429d220eca627c # Parent dad8671f8769f10de29445c0a25b572e961697b1 # Parent 38da844de1148e391dc67779e3dcb4fed8fb5400 Automated merge with ssh://h...@m5sim.org/m5 diff --git

[m5-dev] [PATCH 18 of 18] ruby: configuration updates

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252966262 18000 # Node ID 0bf5c598c9c5221632044a222d47a67f30ae38cd # Parent 829892ec644cf1ac856fdb610ba81053dc593902 ruby: configuration updates diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb

[m5-dev] [PATCH 16 of 18] merge

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252704197 18000 # Node ID a72eab4bdf6c8492831b72fe5d056da43b83d290 # Parent 1a01f799bd7636f41cb864f99dd8d9184034cf72 # Parent 3b2d7fdff6b1adf0473759965ed08a7c8e0edad1 merge diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm

[m5-dev] [PATCH 17 of 18] ruby: removed stray printf

2009-09-14 Thread Derek Hower
# HG changeset patch # User Derek Hower d...@cs.wisc.edu # Date 1252966166 18000 # Node ID 829892ec644cf1ac856fdb610ba81053dc593902 # Parent a72eab4bdf6c8492831b72fe5d056da43b83d290 ruby: removed stray printf diff --git a/src/mem/ruby/network/simple/Topology.cc

Re: [m5-dev] [PATCH 02 of 18] ruby: CacheMemory tag lookup uses a hash instead of a loop

2009-09-14 Thread nathan binkert
One of my personal pet peeves is having code in the tree that's commented out. Is there any reason to do this with a revision control system? Either the code is good and should be kept, or it should just be deleted and live in the history. Nate On Mon, Sep 14, 2009 at 3:14 PM, Derek Hower

Re: [m5-dev] [PATCH 01 of 18] ruby: added random seed option to config scripts

2009-09-14 Thread nathan binkert
This code reminds me that we really need to start having a plan to merge ruby/m5 code more. There are many things in both code bases and this is yet another example. Perhaps we can try to target that we all put some effort into this after ISCA. Nate On Mon, Sep 14, 2009 at 3:14 PM, Derek

Re: [m5-dev] [PATCH 04 of 18] [mq]: first_patch

2009-09-14 Thread Polina Dudnik
On Mon, Sep 14, 2009 at 6:07 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: I notice you have several patches that change around style.py. You probably shouldn't have that in a commit ready patch, and you shouldn't change it back and forth throughout the series. You are right and

Re: [m5-dev] [PATCH 03 of 18] Automated merge with ssh://h...@m5sim.org/m5

2009-09-14 Thread nathan binkert
Are you not using mercurial queues? Generally, you don't get merge changesets when you do. Either way, it's not a major problem, but you can keep the history cleaner if you do. Nate On Mon, Sep 14, 2009 at 3:14 PM, Derek Hower d...@cs.wisc.edu wrote: # HG changeset patch # User Derek Hower

Re: [m5-dev] [PATCH 04 of 18] [mq]: first_patch

2009-09-14 Thread nathan binkert
You are right and that's probably more my mistake than Dereks. What happens is that mercurial crashes whenever it would detect a white-space issue. So, for me to make a patch or commit I hacked the style file, and these changes made it into the patch. Send me the error message and I'll fix it.

Re: [m5-dev] [PATCH 03 of 18] Automated merge with ssh://h...@m5sim.org/m5

2009-09-14 Thread Derek Hower
No, I'm not using mercurial queues. It's on the things I need to do but don't yet list. On Mon, Sep 14, 2009 at 6:21 PM, nathan binkert n...@binkert.org wrote: Are you not using mercurial queues? Generally, you don't get merge changesets when you do. Either way, it's not a major problem,

[m5-dev] [PATCH] implement sysinfo() syscall

2009-09-14 Thread Vince Weaver
Hello the patch below implements the linux sysinfo() syscall on the SE targets. Currently it only really implements the memory size parameter. This allows a set of qemu regression tests I have run to completion ( http://deater.net/weave/vmwprod/asm/ll/qemu_tests.html ) The patch has been tested

[m5-dev] [PATCH] fix x86 loop instruction

2009-09-14 Thread Vince Weaver
Hello the loop instructions on x86 are broken, they seem to be using a 16-bit immediate for the offset instead of the proper signed 8-bit one. This very obviously breaks instructions trying to loop backward. The patch below fixes things on my regression test, though I might have something

[m5-dev] [PATCH] hook up some X86_SE syscalls

2009-09-14 Thread Vince Weaver
Hello various common 32-bit x86 syscalls were not hooked up. The patch below fixes this, allowing the 32-bit x86 version of my regression test to run. Vince diff -r 3b2d7fdff6b1 src/arch/x86/linux/syscalls.cc --- a/src/arch/x86/linux/syscalls.ccFri Sep 11 16:19:31 2009 -0500 +++

Re: [m5-dev] [PATCH] fix x86 loop instruction

2009-09-14 Thread Gabriel Michael Black
Thank you for your patches. I'm a little buried right now, but they are important, I -will- get to them eventually, and they'll more than likely end up in the tree. Thanks! Gabe Quoting Vince Weaver vi...@csl.cornell.edu: Hello the loop instructions on x86 are broken, they seem to be

Re: [m5-dev] [PATCH] fix x86 loop instruction

2009-09-14 Thread nathan binkert
Gabe, If you didn't know, you can just take his patches and stick them in your queue and use the -u option to qref to add his name to the patch so he gets credit when you push. Also, when people use hg email, you can just take the patch as is and stick it in your queue since it contains all of

[m5-dev] changeset in m5: Add an I/O cache to FS config even if there's j...

2009-09-14 Thread Steve Reinhardt
changeset 8c68656b8564 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=8c68656b8564 description: Add an I/O cache to FS config even if there's just an L2 cache. diffstat: 1 file changed, 1 insertion(+), 1 deletion(-) configs/example/fs.py |2 +- diffs (12 lines):

[m5-dev] [PATCH] fix SPARC udivcc instruction

2009-09-14 Thread Vince Weaver
Hello the SPARC udivcc instruction was attempting to read bits 63:32 of a uint32_t, which didn't work very well. The below patch changes the value to uint64_t which fixes my test case. Vince diff -r 3b2d7fdff6b1 src/arch/sparc/isa/decoder.isa --- a/src/arch/sparc/isa/decoder.isaFri Sep 11

[m5-dev] changeset in m5: inorder-alpha-fs: edit inorder model to compile...

2009-09-14 Thread Korey Sewell
changeset cd671122f09c in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=cd671122f09c description: inorder-alpha-fs: edit inorder model to compile FS mode diffstat: 10 files changed, 354 insertions(+), 24 deletions(-) src/cpu/inorder/SConscript |1