Re: [m5-dev] Review Request: ruby: dbg: use system ticks instead of cycles

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Re: [m5-dev] Review Request: ruby: dbg: use system ticks instead of cycles

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Re: [m5-dev] Interpreting and "Fixing" Ruby Stats??

> > I realize the documentation is still under way for gem5, but I was > > wondering if there are any plans to document how users should  be > > interpreting the Ruby stats file? (Particularly, the miss latency > > histograms) Not all protocols support the miss latency histograms. Specifically,

Re: [m5-dev] Running Ruby w/32 Cores

On Thu, 7 Apr 2011, Gabriel Michael Black wrote: Quoting Nilay Vaish : On Thu, 7 Apr 2011, Gabriel Michael Black wrote: When you say this is portable, what do you mean? Portable between compilers? We usually use gcc, but we have at least partial support for other compilers. I think this is

Re: [m5-dev] Running Ruby w/32 Cores

Quoting Nilay Vaish : On Thu, 7 Apr 2011, Gabriel Michael Black wrote: When you say this is portable, what do you mean? Portable between compilers? We usually use gcc, but we have at least partial support for other compilers. I think this is necessary on some platforms. Gabe I would st

Re: [m5-dev] Running Ruby w/32 Cores

The problem is that LONG_BITS is 31, ie std::numeric_limits::digits returns 31 and not 32 which is what the writer expected. -- Nilay From: koreylsew...@gmail.com [mailto:koreylsew...@gmail.com] On Behalf Of Korey Sewell Sent: Tuesday, April 05, 2011 7:14 AM To: Beckmann, Brad Subject: Re: [

Re: [m5-dev] Running Ruby w/32 Cores

On Thu, 7 Apr 2011, Gabriel Michael Black wrote: When you say this is portable, what do you mean? Portable between compilers? We usually use gcc, but we have at least partial support for other compilers. I think this is necessary on some platforms. Gabe I would still root for using popcoun

Re: [m5-dev] Running Ruby w/32 Cores

Hi, I'd be willing to take a stab at this (but admittedly, If I have to do some major fiddling with the Stats infrastructure, this would be on the backburner for a week or so). On Thu, Apr 7, 2011 at 12:20 PM, Beckmann, Brad wrote: > Currently Ruby does dynamically set the size of the bitsets and

Re: [m5-dev] Interpreting and "Fixing" Ruby Stats??

Hi, not to push and prod, but if anyone has any ideas or thoughts on this, please speak up! Thanks! -Korey On Tue, Apr 5, 2011 at 12:54 PM, Korey Sewell wrote: > Hi All, > I realize the documentation is still under way for gem5, but I was wondering > if there are any plans to document how users

Re: [m5-dev] Running Ruby w/32 Cores

Currently Ruby does dynamically set the size of the bitsets and assigns bitsets of different lengths to each other. However, I don't think that is really necessary. Rather it is just convenient because Ruby uses the machineCount function to set the bitset size and that function is not availab

Re: [m5-dev] Memory dependency error

I understand what you are saying and I am checking when there is a forwarding, so it's definitely not the case. I will turn on the trace flags in cache and see what happens there. I am wondering if it's possible that those two operations are receiving the acknowledge/data from cache at the same cy

Re: [m5-dev] Memory dependency error

Actually, disregard the scenario I placed below. I think my original point about LSQ forwarding and Ali's extension of that point make sense here. On Thu, Apr 7, 2011 at 9:55 AM, Korey Sewell wrote: > Have you turned on the trace flags in the Cache? > > Try m5 --trace-help for a listing of flags

Re: [m5-dev] Memory dependency error

Assuming the store had it's address available it might not be complete, things can stay in the store buffer a while, but it would still be able to forward its data to the load, which it sounds like what is going on. Ali Sent from my ARM powered device On Apr 7, 2011, at 8:50 AM, Eberle wrote

Re: [m5-dev] Memory dependency error

Have you turned on the trace flags in the Cache? Try m5 --trace-help for a listing of flags. If you are talking about things that are happening in the memory system, then you may want to observe how things are being handled w/the MSHRS. Particularly, what if you have store to A misses in the cac

Re: [m5-dev] Memory dependency error

I've observed that with other loads closer to the store. But this one is not the case. -- Eberle A. Rambo. Mastering in Computer Science System Design Automation Lab (LAPS) and Interdepartmental Core of Microelectronics (NIME) Department of Informatics and Statistics (INE) Federal University of S

Re: [m5-dev] Memory dependency error

The O3 model does have load-store forwarding, so yes, if you have a store to A in the LSQ and another load comes to that same address A while the store is still in the LSQ, then the load can save time and just pull the data from the LSQ instead of going out to memory. I'm not sure if this is what

[m5-dev] Memory dependency error

Hi there, I've been facing a situation that I suppose it shouldn't happen. Using the O3 model and SPARC ISA, in the middle of the execution there are some memory operations: Store to address A followed by other accesses to other addresses and then a Load to address A. What happens is that this Loa

[m5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/