changeset 2b2efc67f6df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2b2efc67f6df
description:
ARM: Rename registers used as temporary state by microops.
diffstat:
src/arch/arm/isa/insts/macromem.isa | 32
changeset 7449084b1612 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7449084b1612
description:
ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:
URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;
changeset 02450f4443ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02450f4443ce
description:
O3: Fixes the way prefetches are handled inside the iew unit.
This patch prevents the prefetch being added to the instCommit queue
twice.
diffstat:
changeset bb38f0c47ade in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bb38f0c47ade
description:
O3: Fix mispredicts from non control instructions.
The squash inside the fetch unit should not attempt to remove them from
the
branch predictor as
changeset 69aae4379062 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=69aae4379062
description:
ARM: The ARM decoder should not panic when decoding undefined holes is
arch.
This can abort simulations when the fetch unit runs ahead and
speculatively
changeset d25827665112 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d25827665112
description:
O3: Don't test misprediction on load instructions until executed.
diffstat:
src/cpu/o3/iew_impl.hh | 6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diffs (16
changeset b2c7e56572a4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b2c7e56572a4
description:
O3: Fix some variable length instruction issues with the O3 CPU and ARM
ISA.
diffstat:
src/arch/arm/predecoder.cc | 15 +++
src/arch/arm/predecoder.hh | 22
On 2010-12-08 23:39:28, Gabe Black wrote:
src/cpu/simple/base.cc, line 399
http://reviews.m5sim.org/r/344/diff/1/?file=5467#file5467line399
The braces are wrong.
Have you tried this with x86? X86_FS? This looks like it will reset the
predecoder constantly because the
On 2010-12-09 00:05:46, Gabe Black wrote:
src/cpu/o3/iew_impl.hh, line 1298
http://reviews.m5sim.org/r/349/diff/1/?file=5479#file5479line1298
Wouldn't just checking !inst-isExecuted be sufficient? If it hasn't
executed yet I don't think it shouldn't be checked for a mispredict no
