[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
* do-regression: qsub timed out, retrying locally * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed. See /z/m5/regression/regress-2009-04-08-03:00:02 for details. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] IDE panic
I don't know much about IDE either, but it may have more to do with DMA in
general than with IDE specifically. What is the specific panic that you're
getting (i.e., the actual output)?
Steve
On Wed, Apr 8, 2009 at 1:36 AM, Gabe Black gbl...@eecs.umich.edu wrote:
Anybody? The ATA spec I have is -really- long and I'm not feeling
ambitious enough to read it :). I don't know if this would be covered in
there anyway.
Gabe
Gabe Black wrote:
I have an SMP kernel booting and running the init process, but I'm
getting the following panic from the IDE disk on line 321 in
dev/ide_disk.cc:
void
IdeDisk::doDmaTransfer()
{
if (dmaState != Dma_Transfer || devState != Transfer_Data_Dma)
panic(Inconsistent DMA transfer state: dmaState = %d devState =
%d\n,
dmaState, devState);
I'm not familiar with the details of IDE. Could someone please give me a
30 second explanation of what this is checking?
Gabe
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Re: [m5-dev] IDE panic
It's a panic that is supposed to check that the state machine in
operating correctly. To start a dma transfer the device is supposed to
be in Transfer_Data_Dma (which some device access writes put in in)
and the dmaState is supposed to be in Dma_Transfer (as opposed to some
other phase of the DMA). Which one is incorrect in the panic?
Are you identifying the device (PCI device/vendor IDs) exactly as we
do for Alpha (it ends up being a Intel PIIX IDE controller or
something). If you're not you might be stumbling on some un-
implemented feature. If you are, then I would guess that it's
something to do with I/O writes not getting to the device correctly
(either order or just disappearing). You can boot the Alpha version
with DPRINTFs and see the correct sequence of commands and then
compare that to the DMA that dies for some more insight.
Ali
On Apr 8, 2009, at 5:46 PM, Steve Reinhardt wrote:
I don't know much about IDE either, but it may have more to do with
DMA in general than with IDE specifically. What is the specific
panic that you're getting (i.e., the actual output)?
Steve
On Wed, Apr 8, 2009 at 1:36 AM, Gabe Black gbl...@eecs.umich.edu
wrote:
Anybody? The ATA spec I have is -really- long and I'm not feeling
ambitious enough to read it :). I don't know if this would be
covered in
there anyway.
Gabe
Gabe Black wrote:
I have an SMP kernel booting and running the init process, but
I'm
getting the following panic from the IDE disk on line 321 in
dev/ide_disk.cc:
void
IdeDisk::doDmaTransfer()
{
if (dmaState != Dma_Transfer || devState != Transfer_Data_Dma)
panic(Inconsistent DMA transfer state: dmaState = %d
devState =
%d\n,
dmaState, devState);
I'm not familiar with the details of IDE. Could someone please
give me a
30 second explanation of what this is checking?
Gabe
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Re: [m5-dev] MIPS O3 fault
Thanks for your kind reply of this problem. You're so nice. Using the MIPS architecture on M5 for some system performance evaluation is our recent research interest. I will report on what we find for you, hope it useful for you and other developers to perfect the MIPS architecture on M5. Thanks for your kind reply again. Best wishes. --- 09年4月8日，周三, Korey Sewell ksew...@umich.edu 写道： 发件人: Korey Sewell ksew...@umich.edu 主题: Re: [m5-dev] MIPS O3 fault 收件人: pengfeida...@yahoo.com.cn 日期: 2009年4月8日,周三,上午12:59 I looked into this closer and made some progress but no permanent fix yet. It looks like adding the code for other ISAs (x86,SPARC,etc.) broke the branch prediction in MIPS code. I have to figure out a way to fix the MIPS things but simultaneously keep everything else working. This is nontrivial BUT I'm working on it. Using the instruction traces I mentioned earlier, I'm starting to track down some of the problems. I'll keep you posted on the progress, but I should be done in a couple of days. Thanks for your patience, I'll get it working again as soon as possible. -korey 2009/4/5 苟鹏飞 pengfeida...@yahoo.com.cn Hello, everybody. We're very interesting in M5 simulator and wanna do something with such an excellent tool. But, we find that the MIPS O3CPU model doesn't work well because of some assertion faults. Firstly, the assertion information is as follows: Assertion 'params-numPhysIntRegs = numThreads * MipsISA::NumIntRegs' params-numPhysIntRegs equals 256 while MipsISA::NumIntRegs equals 521, so it's obviously an fate error. After I change the value of numPhysIntRegs from 256 to 1024, this assertion disappear, but there comes another assertion fault as follows: Assertion 'pred_hist.front().seqNum == squashed_sn' I have no idea about this assertion. It looks like something goes wrong in BTB, but i don't know what to do and how to solve it. Could anybody give some suggestion about this? Is a bug of mips o3cpu model? or have i miss some steps when i run mips in o3 mode? Thank you guys. ___ 好玩贺卡等你发，邮箱贺卡全新上线！ http://card.mail.cn.yahoo.com/ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ 好玩贺卡等你发，邮箱贺卡全新上线！ http://card.mail.cn.yahoo.com/ ___ 好玩贺卡等你发，邮箱贺卡全新上线！ http://card.mail.cn.yahoo.com/ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: style: fix style hook for some newer versions o...
changeset 6df0633d883b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6df0633d883b
description:
style: fix style hook for some newer versions of mercurial.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
util/style.py |4 ++--
diffs (21 lines):
diff -r 0647c8b31a99 -r 6df0633d883b util/style.py
--- a/util/style.py Mon Apr 06 10:19:36 2009 -0700
+++ b/util/style.py Wed Apr 08 22:21:25 2009 -0700
@@ -347,7 +347,7 @@
if prompt(fname, fixonly):
return True
-def check_whitespace(ui, repo, hooktype, node, parent1, parent2):
+def check_whitespace(ui, repo, hooktype, node, parent1, parent2, **kwargs):
if hooktype != 'pretxncommit':
raise AttributeError, \
This hook is only meant for pretxncommit, not %s % hooktype
@@ -355,7 +355,7 @@
args = { 'tabsize' : 8 }
do_check_whitespace(ui, repo, **args)
-def check_format(ui, repo, hooktype, node, parent1, parent2):
+def check_format(ui, repo, hooktype, node, parent1, parent2, **kwargs):
if hooktype != 'pretxncommit':
raise AttributeError, \
This hook is only meant for pretxncommit, not %s % hooktype
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[m5-dev] changeset in m5: tlb: Don't separate the TLB classes into an ins...
changeset 410194bb3049 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=410194bb3049
description:
tlb: Don't separate the TLB classes into an instruction TLB and a data
TLB
diffstat:
34 files changed, 310 insertions(+), 601 deletions(-)
src/arch/alpha/AlphaTLB.py| 14 -
src/arch/alpha/tlb.cc | 253 +++--
src/arch/alpha/tlb.hh | 68 +++-
src/arch/mips/MipsTLB.py | 20 --
src/arch/mips/tlb.cc | 97 ++--
src/arch/mips/tlb.hh | 32
src/arch/sparc/SparcTLB.py| 14 -
src/arch/sparc/tlb.cc | 96
src/arch/sparc/tlb.hh | 59 +--
src/arch/sparc/vtophys.cc |4
src/arch/x86/X86TLB.py| 14 -
src/arch/x86/pagetable_walker.cc |2
src/arch/x86/tlb.cc | 61 +--
src/arch/x86/tlb.hh | 50 +-
src/cpu/BaseCPU.py| 26 +--
src/cpu/checker/cpu.hh|7
src/cpu/checker/thread_context.hh |4
src/cpu/inorder/cpu.hh|4
src/cpu/inorder/resources/tlb_unit.cc |2
src/cpu/inorder/thread_context.hh |4
src/cpu/o3/cpu.hh |4
src/cpu/o3/fetch_impl.hh |3
src/cpu/o3/thread_context.hh |4
src/cpu/ozone/cpu.hh | 11 -
src/cpu/ozone/front_end_impl.hh |2
src/cpu/ozone/simple_params.hh|5
src/cpu/simple/atomic.cc |2
src/cpu/simple/timing.cc |2
src/cpu/simple/timing.hh |6
src/cpu/simple_thread.cc |4
src/cpu/simple_thread.hh | 12 -
src/cpu/thread_context.hh | 11 -
src/sim/tlb.cc|7
src/sim/tlb.hh|7
diffs (truncated from 1715 to 300 lines):
diff -r 6df0633d883b -r 410194bb3049 src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.pyWed Apr 08 22:21:25 2009 -0700
+++ b/src/arch/alpha/AlphaTLB.pyWed Apr 08 22:21:27 2009 -0700
@@ -33,15 +33,5 @@
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
-abstract = True
-size = Param.Int(TLB size)
-
-class AlphaDTB(AlphaTLB):
-type = 'AlphaDTB'
-cxx_class = 'AlphaISA::DTB'
-size = 64
-
-class AlphaITB(AlphaTLB):
-type = 'AlphaITB'
-cxx_class = 'AlphaISA::ITB'
-size = 48
+cxx_class = 'AlphaISA::TLB'
+size = Param.Int(64, TLB size)
diff -r 6df0633d883b -r 410194bb3049 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Apr 08 22:21:25 2009 -0700
+++ b/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -72,6 +72,90 @@
delete [] table;
}
+void
+TLB::regStats()
+{
+fetch_hits
+.name(name() + .fetch_hits)
+.desc(ITB hits);
+fetch_misses
+.name(name() + .fetch_misses)
+.desc(ITB misses);
+fetch_acv
+.name(name() + .fetch_acv)
+.desc(ITB acv);
+fetch_accesses
+.name(name() + .fetch_accesses)
+.desc(ITB accesses);
+
+fetch_accesses = fetch_hits + fetch_misses;
+
+read_hits
+.name(name() + .read_hits)
+.desc(DTB read hits)
+;
+
+read_misses
+.name(name() + .read_misses)
+.desc(DTB read misses)
+;
+
+read_acv
+.name(name() + .read_acv)
+.desc(DTB read access violations)
+;
+
+read_accesses
+.name(name() + .read_accesses)
+.desc(DTB read accesses)
+;
+
+write_hits
+.name(name() + .write_hits)
+.desc(DTB write hits)
+;
+
+write_misses
+.name(name() + .write_misses)
+.desc(DTB write misses)
+;
+
+write_acv
+.name(name() + .write_acv)
+.desc(DTB write access violations)
+;
+
+write_accesses
+.name(name() + .write_accesses)
+.desc(DTB write accesses)
+;
+
+data_hits
+.name(name() + .data_hits)
+.desc(DTB hits)
+;
+
+data_misses
+.name(name() + .data_misses)
+.desc(DTB misses)
+;
+
+data_acv
+.name(name() + .data_acv)
+.desc(DTB access violations)
+;
+
+data_accesses
+.name(name() + .data_accesses)
+.desc(DTB accesses)
+;
+
+data_hits = read_hits + write_hits;
+data_misses = read_misses + write_misses;
+data_acv = read_acv + write_acv;
+data_accesses = read_accesses + write_accesses;
+}
+
// look up an entry in the TLB
TlbEntry *
TLB::lookup(Addr vpn, uint8_t asn)
@@ -288,36 +372,8 @@
}
}
-///
-//
-// Alpha ITB
-//
-ITB::ITB(const Params *p)
-: TLB(p)
-{}
-
-
-void
-ITB::regStats()
-{
-hits
-.name(name() + .hits)
-.desc(ITB hits);
-misses
-.name(name() +
[m5-dev] changeset in m5: tlb: More fixing of unified TLB
changeset 47b4fcb10c11 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=47b4fcb10c11
description:
tlb: More fixing of unified TLB
diffstat:
20 files changed, 130 insertions(+), 129 deletions(-)
src/arch/alpha/AlphaTLB.py |8 +-
src/arch/alpha/tlb.cc| 13 --
src/arch/alpha/tlb.hh|6 +
src/arch/mips/tlb.cc | 12 --
src/arch/mips/tlb.hh |5 +---
src/arch/sparc/tlb.cc| 12 --
src/arch/sparc/tlb.hh|5 +---
src/arch/x86/faults.hh |9 ---
src/arch/x86/pagetable_walker.cc | 18 +++
src/arch/x86/pagetable_walker.hh |5 ++--
src/arch/x86/tlb.cc | 33 +++
src/arch/x86/tlb.hh |8 ++
src/cpu/BaseCPU.py | 13 +-
src/cpu/base_dyn_inst.hh |5 ++--
src/cpu/o3/fetch_impl.hh |2 -
src/cpu/simple/atomic.cc |7 +++--
src/cpu/simple/timing.cc | 28 +++
src/cpu/simple/timing.hh | 45 +-
src/sim/tlb.cc |7 ++---
src/sim/tlb.hh | 18 +--
diffs (truncated from 738 to 300 lines):
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.pyWed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/AlphaTLB.pyWed Apr 08 22:21:27 2009 -0700
@@ -34,4 +34,10 @@
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
-size = Param.Int(64, TLB size)
+size = Param.Int(TLB size)
+
+class AlphaDTB(AlphaTLB):
+size = 64
+
+class AlphaITB(AlphaTLB):
+size = 48
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -607,23 +607,20 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
-if (execute)
+if (mode == Execute)
return translateInst(req, tc);
else
-return translateData(req, tc, write);
+return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation,
-bool write, bool execute)
+Translation *translation, Mode mode)
{
assert(translation);
-translation-finish(translateAtomic(req, tc, write, execute),
-req, tc, write, execute);
+translation-finish(translateAtomic(req, tc, mode), req, tc, mode);
}
/* end namespace AlphaISA */ }
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -141,11 +141,9 @@
Fault translateInst(RequestPtr req, ThreadContext *tc);
public:
-Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write = false, bool execute = false);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation,
-bool write = false, bool execute = false);
+ Translation *translation, Mode mode);
};
} // namespace AlphaISA
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/mips/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -562,22 +562,20 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
-if (execute)
+if (mode == Execute)
return translateInst(req, tc);
else
-return translateData(req, tc, write);
+return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation, bool write, bool execute)
+Translation *translation, Mode mode)
{
assert(translation);
-translation-finish(translateAtomic(req, tc, write, execute),
-req, tc, write, execute);
+translation-finish(translateAtomic(req, tc, mode), req, tc, mode);
}
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/mips/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -138,10 +138,9 @@
void regStats();
-Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write=false, bool execute=false);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation, bool write=false, bool
[m5-dev] changeset in m5: tests: update tests for TLB unification
changeset 0555121b5c5f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0555121b5c5f description: tests: update tests for TLB unification diffstat: 197 files changed, 1885 insertions(+), 1171 deletions(-) tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |4 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |8 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 40 +- tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini |4 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout | 10 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt | 40 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini |4 tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout | 10 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt | 40 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini |4 tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |8 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |8 tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini |4 tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout | 10 tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt |8 tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini |4 tests/long/00.gzip/ref/sparc/linux/simple-timing/simout |8 tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt |8 tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini |4 tests/long/00.gzip/ref/x86/linux/simple-atomic/simout | 10 tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt |8 tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini |4 tests/long/00.gzip/ref/x86/linux/simple-timing/simout | 10 tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 72 +++-- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |4 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 40 +- tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini |4 tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout | 10 tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt |8 tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini |4 tests/long/10.mcf/ref/sparc/linux/simple-timing/simout |8 tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt |8 tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini |4 tests/long/10.mcf/ref/x86/linux/simple-atomic/simout | 10 tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt |8 tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini |4 tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 10 tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt |8 tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini |4 tests/long/20.parser/ref/x86/linux/simple-atomic/simout | 10 tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt |8 tests/long/20.parser/ref/x86/linux/simple-timing/config.ini |4 tests/long/20.parser/ref/x86/linux/simple-timing/simout | 10 tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt |8 tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini |4 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |8
