Re: [m5-dev] [PATCH 2 of 3] BaseDynInst: Make the TLB translation timing instead of atomic

On Tue, 01 Dec 2009 20:37:57 -, Steve Reinhardt ste...@gmail.com wrote: It looks like you lost the initialization of isUncacheable... is that safe? Hm, yes I'll fix that. Actually I'm not sure why we need that variable, and don't just have BaseDynInst::uncacheable() call

Re: [m5-dev] [PATCH 2 of 3] BaseDynInst: Make the TLB translation timing instead of atomic

Hi Tim, It looks like you lost the initialization of isUncacheable... is that safe? diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -861,29 +871,14 @@     Request *req = new Request(asid, addr, sizeof(T),

Re: [m5-dev] [PATCH 2 of 3] BaseDynInst: Make the TLB translation timing instead of atomic

More or less, yes I did. I made some modifications though. I can definitely try to incorporate this into Timing too though. Tim On Mon, 09 Nov 2009 18:26:25 -, nathan binkert n...@binkert.org wrote: Did you pull the code in translation.hh out of cpu/simple/timing.hh? If so, does it

[m5-dev] [PATCH 2 of 3] BaseDynInst: Make the TLB translation timing instead of atomic

# HG changeset patch # User Timothy M. Jones tjon...@inf.ed.ac.uk # Date 1257772288 0 # Node ID da27e67385cca6cf4dd6d18cdead5cfd54559afb # Parent 861198113ecaf172b6d1e874cda4d13c92bdb38a BaseDynInst: Make the TLB translation timing instead of atomic. This initiates a timing translation and

Re: [m5-dev] [PATCH 2 of 3] BaseDynInst: Make the TLB translation timing instead of atomic

Did you pull the code in translation.hh out of cpu/simple/timing.hh? If so, does it need to remain? I'd prefer not to have to copies of the same code floating around. Nate On Mon, Nov 9, 2009 at 5:30 AM, Timothy M. Jones tjon...@inf.ed.ac.uk wrote: # HG changeset patch # User Timothy M.