# HG changeset patch
# User Timothy M. Jones <tjon...@inf.ed.ac.uk>
# Date 1257772288 0
# Node ID da27e67385cca6cf4dd6d18cdead5cfd54559afb
# Parent 861198113ecaf172b6d1e874cda4d13c92bdb38a
BaseDynInst: Make the TLB translation timing instead of atomic.
This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this. The idea is taken from the
implementation of timing translations in TimingSimpleCPU by Gabe Black.
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * Copyright (c) 2009 The University of Edinburgh
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,6 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Timothy M. Jones
*/
#ifndef __CPU_BASE_DYN_INST_HH__
@@ -45,6 +47,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
+#include "cpu/translation.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
#include "sim/tlb.hh"
@@ -126,8 +129,15 @@
* @return Returns any fault due to the write.
*/
template <class T>
- Fault write(T data, Addr addr, unsigned flags,
- uint64_t *res);
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+
+ /** Initiate a DTB address translation. */
+ void initiateTranslation(RequestPtr req, uint64_t *res,
+ BaseTLB::Mode mode);
+
+ /** Finish a DTB address translation. */
+ void finishTranslation(Fault translate_fault, RequestPtr &req,
+ uint64_t *res, bool read);
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
@@ -861,29 +871,14 @@
Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
thread->contextId(), threadNumber);
- fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
+ initiateTranslation(req, NULL, BaseTLB::Read);
- if (req->isUncacheable())
- isUncacheable = true;
+ effAddr = req->getVaddr();
+ effAddrValid = true;
+ if (fault == NoFault) {
+ cpu->read(req, data, lqIdx);
+ } else {
- if (fault == NoFault) {
- effAddr = req->getVaddr();
- effAddrValid = true;
- physEffAddr = req->getPaddr();
- memReqFlags = req->getFlags();
-
-#if 0
- if (cpu->system->memctrl->badaddr(physEffAddr)) {
- fault = TheISA::genMachineCheckFault();
- data = (T)-1;
- this->setExecuted();
- } else {
- fault = cpu->read(req, data, lqIdx);
- }
-#else
- fault = cpu->read(req, data, lqIdx);
-#endif
- } else {
// Return a fixed value to keep simulation deterministic even
// along misspeculated paths.
data = (T)-1;
@@ -891,7 +886,6 @@
// Commit will have to clean up whatever happened. Set this
// instruction as executed.
this->setExecuted();
- delete req;
}
if (traceData) {
@@ -916,14 +910,37 @@
Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
thread->contextId(), threadNumber);
- fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
+ initiateTranslation(req, res, BaseTLB::Write);
+ effAddr = req->getVaddr();
+ effAddrValid = true;
+ if (fault == NoFault) {
+ cpu->write(req, data, sqIdx);
+ }
+
+ return fault;
+}
+
+template<class Impl>
+inline void
+BaseDynInst<Impl>::initiateTranslation(RequestPtr req, uint64_t *res,
+ BaseTLB::Mode mode)
+{
+ DataTranslation<Impl> *trans =
+ new DataTranslation<Impl>(this, res, mode);
+ cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
+}
+
+template<class Impl>
+inline void
+BaseDynInst<Impl>::finishTranslation(Fault translate_fault, RequestPtr &req,
+ uint64_t *res, bool read)
+{
+ fault = translate_fault;
if (req->isUncacheable())
isUncacheable = true;
if (fault == NoFault) {
- effAddr = req->getVaddr();
- effAddrValid = true;
physEffAddr = req->getPaddr();
memReqFlags = req->getFlags();
@@ -931,20 +948,10 @@
assert(res);
req->setExtraData(*res);
}
-#if 0
- if (cpu->system->memctrl->badaddr(physEffAddr)) {
- fault = TheISA::genMachineCheckFault();
- } else {
- fault = cpu->write(req, data, sqIdx);
- }
-#else
- fault = cpu->write(req, data, sqIdx);
-#endif
+
} else {
delete req;
}
-
- return fault;
}
#endif // __CPU_BASE_DYN_INST_HH__
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -46,6 +46,7 @@
#include "config/use_checker.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
+#include "cpu/base_dyn_inst.hh"
#include "cpu/simple_thread.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
new file mode 100644
--- /dev/null
+++ b/src/cpu/translation.hh
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Timothy M. Jones
+ */
+
+#ifndef __CPU_TRANSLATION_HH__
+#define __CPU_TRANSLATION_HH__
+
+#include "sim/tlb.hh"
+
+// Forward declaration
+template <class Impl>
+class BaseDynInst;
+
+template <class Impl>
+class DataTranslation : public BaseTLB::Translation
+{
+ protected:
+ typedef BaseDynInst<Impl> DynInst;
+ typedef RefCountingPtr<DynInst> DynInstPtr;
+
+ DynInstPtr inst;
+ uint64_t *res;
+ BaseTLB::Mode mode;
+
+ public:
+ DataTranslation(DynInstPtr _inst, uint64_t *_res, BaseTLB::Mode _mode)
+ : inst(_inst), res(_res), mode(_mode)
+ {
+ assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
+ }
+
+ void
+ finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ BaseTLB::Mode mode)
+ {
+ assert(mode == this->mode);
+ inst->finishTranslation(fault, req, res, mode == BaseTLB::Read);
+ delete this;
+ }
+};
+
+#endif // __CPU_TRANSLATION_HH__
--
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Scotland, with registration number SC005336.
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