We will take a look at these issues and try to rework our code to keep the flag
size 32b.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas Hansson
Sent: Saturday, August 01, 2015 11:20 AM
To: gem5 Developer List; gem5-...@m5sim.org
Subject: Re: [ge
Thanks for this clarification, Andreas. We were mostly confused by the flags,
cmd, and attributes because - as you pointed out - there seems to be a lot of
overlap with no clear division between the three objects. I think this patch is
going in a good direction.
For our particular case it seems
Hi Andreas,
While we agree there should be a better long term solution, this is what we
have now and what our GPU model - that we plan to release publicly very soon -
relies upon. If we added the flags to currently unused bits in the flags and
kept the flag size to 32 bits, would you mind if we
it is
probably ok as a stop-gap solution. Please ensure it stops at the two
flags though, and I would suggest also adding a @todo and comment
regarding this not being final.
Andreas
On 27/08/2015 10:09, "gem5-dev on behalf of Gutierrez, Anthony"
wrote:
>Hi Andreas,
>
>While we
We can do either hg mv, or hg rm and hg add. What is preferred?
From: Nilay Vaish [mailto:nore...@gem5.org] On Behalf Of Nilay Vaish
Sent: Thursday, September 03, 2015 1:51 PM
To: Nilay Vaish; Gutierrez, Anthony; Hashe, David; Default
Subject: Re: Review Request 2965: rename System.{hh,cc} to
.org] On Behalf Of Nilay Vaish
Sent: Thursday, September 03, 2015 1:56 PM
To: Nilay Vaish; Gutierrez, Anthony; Default; Jieming Yin
Subject: Re: Review Request 3014: ruby: set: reimplement using std::bitset
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3014
I like that idea. Or at least the review number, for brevity's sake.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Steve Reinhardt
Sent: Friday, September 04, 2015 10:32 AM
To: gem5 Developer List
Subject: [gem5-dev] including reviewboard URL in commit m
, September 09, 2015 10:32 AM
To: gem5 Developer List; Hashe, David; Che, Shuai; Gutierrez, Anthony
Subject: Re: [gem5-dev] changeset in gem5: syscall: Add readlink to x86 with
special cas...
Hey David, Shuai, and Tony,
It appears that this patch can introduce simulator non-determinism due to
: Joel Hestness [mailto:jthestn...@gmail.com]
Sent: Wednesday, September 09, 2015 11:14 AM
To: Gutierrez, Anthony
Cc: gem5 Developer List; Hashe, David; Che, Shuai
Subject: Re: [gem5-dev] changeset in gem5: syscall: Add readlink to x86 with
special cas...
If any codes use readlink() in this way
Nilay,
The Address to Addr patch changed the formatting of the DPRINTs that used
Address, will you submit a change that addresses this by making them print
statements behave exactly as before?
Thanks,
Tony
___
gem5-dev mailing list
gem5-dev@gem5.org
h
I see these changes were pushed around Feb 2015, but can you point to the rb
posts? I am unable to find them in your history.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas Sandberg
Sent: Friday, November 20, 2015 8:36 AM
To: gem5 Developer List
Yeah, there was a companion patch to the one I pushed that should have been
folded first. Sorry, I'll take care of it.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas Hansson
Sent: Friday, December 11, 2015 6:59 AM
To: gem5 Developer List
Subject
I think these ran before I pushed the latest changeset. They were all "CHANGED"
when I ran manually, but none failed. They should be ok the next time the
tester runs. I'll update the stats too.
From: gem5-dev on behalf of Cron Daemon
Sent: Saturday, De
Hello All,
As many of you probably know we (AMD) recently made our APU/compute-GPU model
publically available, and it should be pushed to the gem5 source tree soon. We
also hosted a very successful tutorial on our APU model at MICRO-48 on December
6th. We've had a lot of requests for our slides
It looks like you took care of all issues. If nobody objects by the end of the
week, I will commit them during the weekend.
From: Mohammad Alian [mailto:al...@wisc.edu]
Sent: Wednesday, January 20, 2016 9:51 AM
To: gem5 Developer List ; Gutierrez, Anthony
Subject: Re: [gem5-dev] On ReviewBoard
I also vote in favor of adding this mandate to the style guide, and enforcing
it in the style checker.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas Sandberg
Sent: Friday, January 29, 2016 1:30 AM
To: gem5 Developer List
Subject: Re: [gem5-dev]
Since we've been discussing style/coding standards lately, I thought it would
be a good time to bring up a long-standing gripe I have: the use of unsigned
types. I'd like to suggest that the style guide mandate that the use of
unsigned types is forbidden unless there is an explicit need for it (
Sorry, I ran quick only before pushing this. We're looking into it.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas Hansson
Sent: Tuesday, February 16, 2016 1:16 AM
To: gem5-dev@gem5.org
Subject: [gem5-dev] Failing Ruby regression
Hi all,
With th
I just pushed a fix.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas Hansson
Sent: Tuesday, February 16, 2016 1:16 AM
To: gem5-dev@gem5.org
Subject: [gem5-dev] Failing Ruby regression
Hi all,
With the push of:
changeset: 11339:c45bfadcd51b
use
The sequencer originally did this because it maintained its own slave port,
because it wasn't derived from RubyPort. Now that it is, it no longer has its
own slave port, instead using RubyPorts slave_ports vector. RubyPort didn't
send the ranges for the slave_ports, and it is private, so any der
and just send the range change from DMASequencer::init(). This
> shouldn't cause any code duplication, as you suggest.
>
> Thank you,
> Joel
>
>
> On Wed, Feb 17, 2016 at 11:22 AM, Gutierrez, Anthony <
> anthony.gutier...@amd.com> wrote:
>
>> The sequen
Nilay,
Sorry I didn't review this before it went out, but would you mind reverting
this patch? I do believe that issueLat should remain Cycles be allowed to be
set to any value. One can certainly imagine a FU where you have a latency of X,
and yet a throughput of 1 op / Y cycles, where Y != X o
Would it make sense for me to ship the EtherSwitch patch first, since it has
utility on its own, and then we can decide which of the "multi-gem5" approaches
is best, or if it's some combination of both?
The only reason I never shipped it was because Steve raised an issue that I
didn't have a go
>> >>
>> >> pd-gem5 implements this in Python (not a problem in itself;
>> >>aesthetically
>> >>this is nice, but...). The issue is that pd-gem5's data
>> >>packets
>>and
>> >>barrier messages travel
That binary is for HSAIL, so it will not run for GCN3. The model currently only
supports GCN3 ISA binaries and host apps which use the ROCm stack.
The config issue is due to this change:
https://gem5.googlesource.com/amd/gem5/+/a0d42e05f700048b3a77d673ca992e227ac982e0,
which changed those param
Xianwei has posted some changes to fix the problem. The one most directly
related to your issue has been merged. You may need to cherry pick the other.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Sanchari Sen
Sent: Thursday, June 28, 2018 6:47 AM
To:
I've posted the change that adds v_div_scale_f32 here:
https://gem5-review.googlesource.com/c/amd/gem5/+/11889
From: Tsungtai Yeh
Sent: Friday, July 27, 2018 4:24 AM
To: gem5-dev@gem5.org
Cc: Gutierrez, Anthony ; Sinclair, Matthew
Subject: [gem5-dev] Encountered unimplemented GCN3 instru
Looking at apu_se.py, it seems that is the only option to set # of CUs. Does it
not work for you? From that file, it seems like it should be the only option
you need.
From: Tsungtai Yeh
Sent: Friday, July 27, 2018 4:21 AM
To: gem5-dev@gem5.org
Cc: Gutierrez, Anthony
Subject: [gem5-dev] How to
It looks like the number of CUs is being set to 8. The simulator is segfaulting
for some other reason, and you haven't shown enough info to know why it is
segfaulting.
-Original Message-
From: gem5-dev On Behalf Of Tsungtai Yeh
Sent: Saturday, July 28, 2018 5:41 PM
To: gem5-dev@gem5.org
That seems right, Tsung. The idea is that the # of CUs and the objects that
interact with, or contain, the CUs must match certain ratios.
Can you post your changes as a full patch so I can review them?
-Tony
-Original Message-
From: gem5-dev On Behalf Of Tsungtai Yeh
Sent: Wednesday, A
To: gem5 Developer List ; Gutierrez, Anthony
Subject: Re: [gem5-dev] Gem5 Compile issue : Commit :
e02ec0c24d56bce4a0d8636a340e15cd223d1930
Hi Sampad,
It looks like you've found a hole in our testing ;). We don't compile HSAIL
regularly, and it looks like some bugs have worked th
ese issues since it's easier to
use.
Cheers,
Jason
On Thu, Aug 16, 2018 at 9:55 AM Gutierrez, Anthony < anthony.gutier...@amd.com>
wrote:
> Sampad, are you trying to run our GPU model? If so, HSAIL is deprecated.
> We released an updated version of our GPU simulator at
> gem5.
s.
>
> Regards,
> Brandon
>
> P.S. Buy EPYC instead of Xeon.
>
> -Original Message-
> From: Gutierrez, Anthony
> Sent: Thursday, August 16, 2018 1:24 PM
> To: gem5 Developer List
> Cc: Potter, Brandon
> Subject: RE: [gem5-dev] Gem5 Compile issue : Commit :
> e
The address that is failing seems suspect. You may want to get a GPUALL trace
to see which GPU instruction is sending the faulty address, as well as which
instructions generate the offending memory instruction's address operands.
Tony
-Original Message-
From: gem5-dev On Behalf Of Sung
Hi All,
I am getting a segfault almost immediately after simulation starts, I think due
to this change: https://gem5-review.googlesource.com/c/public/gem5/+/13105/5,
as I'm attempting to merge master into our internal master branch.
What I see happening is that LSQUnit::executeStore() calls
LS
I forgot to mention, I am on RHEL 7.3 using gcc 5.4.0
From: Gutierrez, Anthony
Sent: Wednesday, December 5, 2018 2:52 PM
To: gem5-dev@gem5.org
Subject: Problem with dyn insts/refcnt pointers in O3 LSQ.
Hi All,
I am getting a segfault almost immediately after simulation starts, I think due
to
change and we didn't find any
issue. I will rerun them again just to double check
2) Are you running with upstream master or with your internal branch?
Thanks
Giacomo
From: gem5-dev on behalf of Gutierrez, Anthony
Sent: 05 December 2018 22:54:53
To:
t seems to me that there is an unwanted MOVE
(since you have nullptr and the patch is adding move semantics)
Regards
Giacomo
*There is an arm only failure caused by another patch, we are currently looking
into
that.
From: gem5-dev on behalf of Gutierre
Hi All,
I am trying to replace our GPU model's vector register implementation with the
one recently release by ARM:
https://gem5.googlesource.com/public/gem5/+/0747a432d25ade2c197ca6393270e12606419872,
and I noticed an issue I didn't catch when I previously reviewed the patch.
From the code, i
Hi All,
I have a question about using branches in the mainline gem5 repo. I see ARM
have a separate repo here:
https://gem5-review.googlesource.com/admin/projects/arm/gem5. It is used for
staging ARM features under development. At AMD we would like to do something
similar, as we have some sign
using separate repositories gives most of the benefits of branches
(simple to pull changes from others and see others work, better organization,
etc) without the downsides.
I'm open to other points of view, of course!
Cheers,
Jason
On Thu, Dec 14, 2017 at 8:30 AM Gutierrez, Anthony < antho
ssage-
From: Andreas Sandberg [mailto:andreas.sandb...@arm.com]
Sent: Thursday, December 14, 2017 10:01 AM
To: gem5 Developer List ; Gutierrez, Anthony
Subject: Re: [gem5-dev] Using branching in gem5 public
Hi Tony,
I'm generally all for using branches, we use them extensively internally.
Thanks, Andreas. I'll take a look.
-Original Message-
From: Andreas Sandberg [mailto:andreas.sandb...@arm.com]
Sent: Tuesday, December 19, 2017 9:22 AM
To: Gutierrez, Anthony ; gem5 Developer List
Subject: Re: [gem5-dev] Using branching in gem5 public
Hi Tony,
Both you and
We've started experiencing some heisenbugs in our benchmarks that use
to generate input data randomly. It's been a bit painful to get a trace, as
that seems to perturb things enough such that the bug won't trigger. Based on
what we know, however, we suspect that the below unimplemented instruct
This question is mostly for Gabe. In the ROCm runtime we see some inline asm
for specific CPUID functions. They first use CPUID to determine the name string
for the processor, and when it seems the "M5 Simulator" as the vendor it
defaults to Intel and sends along the CPUID request with the Intel
ld be relatively accessible and easier to
customize on a per CPU basis.
What do you think?
Gabe
On Thu, May 3, 2018 at 2:55 PM, Gutierrez, Anthony < anthony.gutier...@amd.com>
wrote:
> This question is mostly for Gabe. In the ROCm runtime we see some
> inline asm for specific
Hi Dibakar,
It's not so surprising that dynamic vs. static binaries show some difference in
instruction fetch behavior, however these numbers do seem drastic, and also
seem counter intuitive as I would expect a dynamic binary to have more accesses
due to trampoline calls. Have you looked at the
Which benchmarks are you trying to build, how are you trying to build them, and
what is the error? Please provide more details about the issues you are facing.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Wang Xu
Sent: Monday, July 18, 2016 12:33 PM
To
Sorry, this all worked fine on my RHEL6 machine. I have a patch and am
re-running the regressions on zizzer. Basically I'm adding unistd.h and
changing the host call from pwrite64() => pwrite(), and I verified it can at
least compile on zizzer now.
-Original Message-
From: gem5-dev [mai
You can reproduce the error if you run apu_se.py by hand. For example:
# build the HSAIL GPU
scons -jN ./build/HSAIL_X86/gem5.opt
# run the GPU hello test
./build/HSAIL_X86/gem5.opt configs/example/apu_se.py -c
tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello -k
tests/test-progs/gpu-hello/bin
looks like the CPU-GPU system creates the topology in a somewhat different
manner than the pure CPU protocols that I am familiar with (and tested all my
changes with).
Let me dig deeper into it and then send out a patch.
Thanks,
Tushar
> On Oct 7, 2016, at 6:37 PM, Gutierrez, Anthony
>
I would like to see this clarified before we ask Brandon to go work on fixing
ALPHA. If it is going to be phased out in a matter of months, I don't think we
should be asking him to waste his time on fixing it.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf
is week if we decide that’s the right thing to
do?
Andreas
On 17/10/2016, 16:37, "gem5-dev on behalf of Gutierrez, Anthony"
wrote:
>I would like to see this clarified before we ask Brandon to go work on
>fixing ALPHA. If it is going to be phased out in a matter of months, I
Yes, I agree the _name designations are meant for clashes between private
members and their accessors. I would also prefer that members still use camel
case, and I'm not a fan of m_ to designate members. We could think about
prepending get/set in front of accessors, but I doubt that will be popu
Hi Andreas,
I agree with this sentiment overall as I think our collection of regressions
currently are pretty ad-hoc; they are basically just the benchmarks that people
want to ensure run for their in gem5, i.e, SPEC etc. I think smaller LLVM unit
tests would provide more directed testing, simi
We do not have access to BSD or OSX, so unless somebody can give Brandon access
to such a machine he would have no way to test any potential fix.
From a high level, the only easy solution I see is to guard OS-specific code
with #ifdefs or something similar. It seems that if we are going to suppo
Here are some ideas we at AMD have for the sprint.
1) Adding checkpointing support to the GPU model
2) Fixing the structure and design of the GPU coalescer
3) Adding x86 inst tests
4) Properly supporting atomics
5) Add support for event-based scheduling in the GPU model, and FUPool-style
function
Another possibility is that we could use the Git Repo tool from Google. If any
of these external libs have corresponding Git repos out there somewhere, it
could automatically pull those (even at specific revs if need be), or we could
mirror them in separate Git repos on googlesource.
-Tony
---
As an aside, I would prefer to avoid sub repos if at all possible. I am not
sure how sub-repos work in Git, but if it is anything like HG they are a pain
IMO.
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gutierrez,
Anthony
Sent: Friday, March 03
There are a three ways to fix this as far as I can tell:
1) Modify our Scons setup to use staged linking.
2) Recompile your kernel to allow for larger ARG_MAX.
3) Modify your paths etc to avoid long names
1) seems to be the best option, but seems like it could be a lot of work.
-Original Mes
Hi gem5 Devs,
Has anybody noticed that some of the uploaded images referenced using File or
Media seem to be missing from the wiki? Maybe it was updated recently?
E.g., see this page: http://gem5.org/TraceCPU
I noticed this when someone pointed out that our gem5 GPU MICRO tutorial slides
were
t can be accessed through the wiki
>> seem to live in ${HTDOCS}/wiki/images, while the broken ones live in
>> ${HTDOCS}/wiki/images/images.
>>
>> Ali, could you have a look? IIRC, you used to handle these sort of
>> things in the past.
>>
>> //Andreas
>&g
other
issues that mostly manifested as bogus application output (i.e., silent data
corruption in the app under test’s results).
From: Gabe Black [mailto:gabebl...@google.com]
Sent: Monday, May 15, 2017 2:44 PM
To: Jason Lowe-Power
Cc: Gross, Joe ; gem5 Developer List ;
Gutierrez, Anthony
That benchmark was for HSAIL ISA, and therefore doesn't run with the GCN3 ISA.
I removed that test from our repo
(https://gem5.googlesource.com/amd/gem5/+/b021dd69fef50a0ccd8883d65225af9ff8bb6682).
Currently we provide no benchmarks that run out of the box on the APU model.
Tony
-Original
There are some instructions about how to build the software stack for the GPU
model here: http://gem5.org/GPU_Models
You’ll need to build the ROCr (runtime) ROCt (thunk) and HCC (clang/llvm
compiler), and probably HIP too as most available codes are in HIP. For
example, the Rodinia benchmarks h
I am fine with this.
Tony
-Original Message-
From: gem5-dev On Behalf Of Gabe Black
Sent: Monday, April 29, 2019 7:39 PM
To: gem5 Developer List
Cc: Rahul Thakur
Subject: Re: [gem5-dev] gerrit pickiness interacting with kokoro
[CAUTION: External Email]
Hello again. I asked the gurus,
[AMD Public Use]
Hey, Jason perhaps you mentioned this somewhere but what is the reason for such
a strong aversion to the template approach? It seems to solve the issue nicely
with what seems to be a minor change in syntax. gem5 is C++, so we should allow
users to write C++.
Tony
From: Jason
[AMD Official Use Only - Internal Distribution Only]
Hi All,
Jason asked me to send a heads up since I plan to push a bunch of GPU changes,
mostly the ones seen on the first page of the log for my staging branch:
https://gem5.googlesource.com/amd/gem5/+log/refs/heads/agutierr/master-gcn3-stagin
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