[gem5-dev] changeset in gem5: isa: Add parameter to pick different decoder ...

changeset d90aec9435bd in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d90aec9435bd description: isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that differ

[gem5-dev] changeset in gem5: cpu: Change literal integer constants to mean...

changeset 83c3e117464e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=83c3e117464e description: cpu: Change literal integer constants to meaningful labels fu_pool and inst_queue were using -1 for "no such FU" and -2 for "all those FUs are busy at the

[gem5-dev] changeset in gem5: mem: Add priority to QueuedPrefetcher

changeset d0368996f1e0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d0368996f1e0 description: mem: Add priority to QueuedPrefetcher Queued prefetcher entries now count with a priority field. The idea is to add packets ordered by priority and then b

[gem5-dev] changeset in gem5: mem: Handful extra features for BasePrefetcher

changeset 3c9fd319a982 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3c9fd319a982 description: mem: Handful extra features for BasePrefetcher Some common functionality added to the base prefetcher, mainly dealing with extracting the block address, p

[gem5-dev] changeset in gem5: mem: Add unused prefetch counter in caches

changeset f351b7f248db in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f351b7f248db description: mem: Add unused prefetch counter in caches Added stat to the cache to account for HardPF'ed blocks that are evicted before being referenced (over-prefetchi

[gem5-dev] changeset in gem5: cpu: Fix the O3 CPU Drain

changeset fe601d7bd955 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fe601d7bd955 description: cpu: Fix the O3 CPU Drain The drain did not wait until stages were ready again. Therefore, as a result of messages in the TimeBuffer being drain, the state

[gem5-dev] changeset in gem5: util: git pre-commit hook to check staged files

changeset 95a34c2188f2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=95a34c2188f2 description: util: git pre-commit hook to check staged files This patch updates the git-pre-commit hook to check the files as they will be after the commit, instead of

[gem5-dev] Futex support in SE mode

Hi everyone, I am interested in running code that uses futexes in SE mode. My understanding is that those syscalls are currently not supported. Before starting anything, I would like to know if there is any ongoing effort of supporting them, and what is the status of it. Cheers, Rekai IMPORT

[gem5-dev] Review Request 3755: cpu: Simplify the rename interface and use RegId

c/cpu/exec_context.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3755/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3756: cpu: Result refactoring

Diff: http://reviews.gem5.org/r/3756/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3758: cpu: Added interface for vector reg file

ecd81 src/cpu/checker/thread_context.hh 78ef8daecd81 configs/common/O3_ARM_v7a.py 78ef8daecd81 src/arch/SConscript 78ef8daecd81 src/arch/alpha/isa.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3758/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberq

[gem5-dev] Review Request 3760: arch: ISA parser additions of vector registers

cpu/simple/exec_context.hh 78ef8daecd81 src/cpu/static_inst.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3760/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailma

[gem5-dev] Review Request 3757: arch: added generic vector register

s Sandberg Diffs - src/arch/generic/vec_reg.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3757/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.o

[gem5-dev] Vector register file

Hi folks, Yesterday I submitted five patches to the review board. The idea of the patches is to implement a proper vector register file. To enable cleaner implementations of the SIMD ISAs. The first patch extends what Nathanael Premillieu did in spring, taking the hierarchical RegIds, and

Re: [gem5-dev] Review Request 3760: arch: ISA parser additions of vector registers

src/cpu/o3/inst_queue_impl.hh 78ef8daecd81 src/cpu/simple/base.cc 78ef8daecd81 src/cpu/simple/exec_context.hh 78ef8daecd81 src/cpu/static_inst.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3760/diff/ Testing (updated) --- Builtin regressions, some fail, addressing the failures Thanks, Reka

[gem5-dev] Review Request 3754: cpu: Simplify the rename interface and use RegId

/arch/x86/insts/microfpop.hh 78ef8daecd81 src/arch/x86/insts/microldstop.hh 78ef8daecd81 src/arch/x86/insts/micromediaop.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3754/diff/ Testing (updated) --- Built in regressions passing Thanks, Rekai Gonzalez Alberq

Re: [gem5-dev] Review Request 3756: cpu: Result refactoring

/cpu_impl.hh 78ef8daecd81 src/cpu/inst_res.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3756/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman

Re: [gem5-dev] Review Request 3757: arch: added generic vector register

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b Reviewed-by: Andreas Sandberg Diffs (updated) - src/arch/generic/vec_reg.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3757/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla __

Re: [gem5-dev] Review Request 3758: cpu: Added interface for vector reg file

iltin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3758: cpu: Added interface for vector reg file

sa.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3758/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3760: arch: ISA parser additions of vector registers

src/arch/sparc/faults.hh 78ef8daecd81 src/arch/sparc/faults.cc 78ef8daecd81 src/arch/sparc/isa/base.isa 78ef8daecd81 src/cpu/StaticInstFlags.py 78ef8daecd81 Diff: http://reviews.gem5.org/r/3760/diff/ Testing --- Builtin regressions, some fail, addressing the failures Thanks, Reka

[gem5-dev] Vector register file

://reviews.gem5.org/r/3756/ http://reviews.gem5.org/r/3757/ http://reviews.gem5.org/r/3758/ http://reviews.gem5.org/r/3760/ From: Rekai Gonzalez Alberquilla Sent: 10 December 2016 15:46 To: gem5-dev@gem5.org Subject: Vector register file Hi folks, Yesterday I submitted five patches to the

Re: [gem5-dev] Review Request 3757: arch: added generic vector register

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3757/#review9286 ------- On Jan. 16, 2017, 11:54 a.m., Rekai Gonzalez Alberquilla wrote: > > --

Re: [gem5-dev] Review Request 3757: arch: added generic vector register

------ On Jan. 16, 2017, 11:54 a.m., Rekai Gonzalez Alberquilla wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3757/ >

Re: [gem5-dev] Review Request 3754: cpu: Simplify the rename interface and use RegId

an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3754/#review9284 --- On Jan. 16, 2017, 11:46 a.m., Rekai Gonzalez Alberquilla wrote: > > --- > This i

Re: [gem5-dev] Review Request 3757: arch: added generic vector register

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b Reviewed-by: Andreas Sandberg Diffs (updated) - src/arch/generic/vec_reg.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3757/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla __

Re: [gem5-dev] Review Request 3756: cpu: Result refactoring

/cpu_impl.hh 78ef8daecd81 src/cpu/inst_res.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3756/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman

Re: [gem5-dev] Review Request 3756: cpu: Result refactoring

ause I made a mistake :) Thanks for spotting it! - Rekai --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3756/#review9285 ------- On

Re: [gem5-dev] Review Request 3758: arch: ISA parser additions of vector registers

src/cpu/o3/inst_queue_impl.hh 3c38d3e74980 src/cpu/simple/base.cc 3c38d3e74980 src/cpu/simple/exec_context.hh 3c38d3e74980 src/cpu/static_inst.hh 3c38d3e74980 Diff: http://reviews.gem5.org/r/3758/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez A

Re: [gem5-dev] Review Request 3758: cpu: Added interface for vector reg file

xt.cc 3c38d3e74980 src/sim/serialize.cc 3c38d3e74980 Diff: http://reviews.gem5.org/r/3758/diff/ Testing --- Builtin regressions Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3760: arch: ISA parser additions of vector registers

cpu/simple/exec_context.hh 3c38d3e74980 src/cpu/static_inst.hh 3c38d3e74980 Diff: http://reviews.gem5.org/r/3760/diff/ Testing --- Builtin regressions, some fail, addressing the failures Thanks, Rekai Gonzalez Alberquilla ___ gem5-dev mailing

Re: [gem5-dev] Review Request 3760: arch: ISA parser additions of vector registers

src/cpu/o3/inst_queue_impl.hh 3c38d3e74980 src/cpu/simple/base.cc 3c38d3e74980 src/cpu/simple/exec_context.hh 3c38d3e74980 src/cpu/static_inst.hh 3c38d3e74980 Diff: http://reviews.gem5.org/r/3760/diff/ Testing (updated) --- Builtin regressions, passing Thanks, Rekai Gonzalez A