[m5-dev] Review Request: garnet: rename and rearrange config parameters

2011-05-09 Thread Tushar Krishna
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/688/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan Binkert,

Re: [m5-dev] Review Request: ARM: Break up condition codes into normal flags, saturation, and simd.

2011-05-09 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/679/#review1213 --- Ship it! It looks ok to me, assuming it passes all your tests. - Gabe

Re: [m5-dev] Review Request: ARM: Remove the saturating (Q) condition code from the renamed register.

2011-05-09 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/680/#review1214 --- You need to be careful here since miscregs won't forward results back to

Re: [m5-dev] Review Request: ARM: Further break up condition code into NZ, C, V bits.

2011-05-09 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/681/#review1215 --- src/arch/arm/faults.cc http://reviews.m5sim.org/r/681/#comment1661

Re: [m5-dev] Review Request: Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

2011-05-09 Thread Gabe Black
On 05/04/11 22:17, Ali Saidi wrote: On 2011-05-04 21:08:25, Gabe Black wrote: CR3 might work. Does the kernel change it on every context switch (user program)? The main reason for having it is when tracing user code the kernel can context switch on you. If you want to see all the code that

[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-05-09 Thread Cron Daemon
* build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing passed. *

Re: [m5-dev] Review Request: ARM: Remove the saturating (Q) condition code from the renamed register.

2011-05-09 Thread Ali Saidi
On 2011-05-08 23:48:49, Gabe Black wrote: You need to be careful here since miscregs won't forward results back to later instructions. Anything that depends on the q bit (and by extension the CPSR as a whole) needs to wait for all earlier instructions to complete before executing. I

Re: [m5-dev] Review Request: ARM: Further break up condition code into NZ, C, V bits.

2011-05-09 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/681/#review1217 --- src/arch/arm/faults.cc http://reviews.m5sim.org/r/681/#comment1673

[m5-dev] gem5 Tutorial @ ISCA 2011

2011-05-09 Thread nathan binkert
Call for Participation: ISCA 2011 Tutorial gem5: A Multiple-ISA Full System Simulator with Detailed Memory Modeling Sunday, June 5, 2011 http://www.gem5.org The gem5 simulator is a merger of two of the computer architecture community’s most popular, open source simulators: M5 and GEMS. The best

[m5-dev] changeset in m5: work around gcc 4.5 warning

2011-05-09 Thread Nathan Binkert
changeset 44f8c2507d85 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=44f8c2507d85 description: work around gcc 4.5 warning diffstat: src/cpu/inorder/resource_pool.cc | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diffs (21 lines): diff -r db269e704d07

Re: [m5-dev] Review Request: slicc: added vnet_type field to identify response vnets from others

2011-05-09 Thread Tushar Krishna
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/686/#review1218 --- Hey Brad, We will need some way for the total number of virtual networks