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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, Nathan
Binkert,
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Ship it!
It looks ok to me, assuming it passes all your tests.
- Gabe
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You need to be careful here since miscregs won't forward results back to
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src/arch/arm/faults.cc
http://reviews.m5sim.org/r/681/#comment1661
On 05/04/11 22:17, Ali Saidi wrote:
On 2011-05-04 21:08:25, Gabe Black wrote:
CR3 might work. Does the kernel change it on every context switch (user
program)? The main reason for having it is when tracing user code the kernel
can context switch on you. If you want to see all the code that
* build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic
passed.
* build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing
passed.
* build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing passed.
*
On 2011-05-08 23:48:49, Gabe Black wrote:
You need to be careful here since miscregs won't forward results back to
later instructions. Anything that depends on the q bit (and by extension
the CPSR as a whole) needs to wait for all earlier instructions to complete
before executing. I
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src/arch/arm/faults.cc
http://reviews.m5sim.org/r/681/#comment1673
Call for Participation: ISCA 2011 Tutorial
gem5: A Multiple-ISA Full System Simulator with Detailed Memory Modeling
Sunday, June 5, 2011
http://www.gem5.org
The gem5 simulator is a merger of two of the computer architecture
community’s most popular, open source simulators: M5 and GEMS. The
best
changeset 44f8c2507d85 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44f8c2507d85
description:
work around gcc 4.5 warning
diffstat:
src/cpu/inorder/resource_pool.cc | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (21 lines):
diff -r db269e704d07
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Hey Brad,
We will need some way for the total number of virtual networks
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